205 lines
5.0 KiB
C
205 lines
5.0 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2014 Samsung Electronics Co., Ltd.
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* Author: Naveen Krishna Ch <naveenkrishna.ch@gmail.com>
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*/
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#ifndef _DT_BINDINGS_CLOCK_EXYNOS7_H
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#define _DT_BINDINGS_CLOCK_EXYNOS7_H
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/* TOPC */
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#define DOUT_ACLK_PERIS 1
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#define DOUT_SCLK_BUS0_PLL 2
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#define DOUT_SCLK_BUS1_PLL 3
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#define DOUT_SCLK_CC_PLL 4
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#define DOUT_SCLK_MFC_PLL 5
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#define DOUT_ACLK_CCORE_133 6
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#define DOUT_ACLK_MSCL_532 7
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#define ACLK_MSCL_532 8
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#define DOUT_SCLK_AUD_PLL 9
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#define FOUT_AUD_PLL 10
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#define SCLK_AUD_PLL 11
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#define SCLK_MFC_PLL_B 12
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#define SCLK_MFC_PLL_A 13
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#define SCLK_BUS1_PLL_B 14
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#define SCLK_BUS1_PLL_A 15
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#define SCLK_BUS0_PLL_B 16
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#define SCLK_BUS0_PLL_A 17
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#define SCLK_CC_PLL_B 18
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#define SCLK_CC_PLL_A 19
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#define ACLK_CCORE_133 20
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#define ACLK_PERIS_66 21
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#define TOPC_NR_CLK 22
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/* TOP0 */
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#define DOUT_ACLK_PERIC1 1
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#define DOUT_ACLK_PERIC0 2
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#define CLK_SCLK_UART0 3
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#define CLK_SCLK_UART1 4
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#define CLK_SCLK_UART2 5
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#define CLK_SCLK_UART3 6
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#define CLK_SCLK_SPI0 7
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#define CLK_SCLK_SPI1 8
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#define CLK_SCLK_SPI2 9
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#define CLK_SCLK_SPI3 10
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#define CLK_SCLK_SPI4 11
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#define CLK_SCLK_SPDIF 12
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#define CLK_SCLK_PCM1 13
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#define CLK_SCLK_I2S1 14
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#define CLK_ACLK_PERIC0_66 15
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#define CLK_ACLK_PERIC1_66 16
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#define TOP0_NR_CLK 17
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/* TOP1 */
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#define DOUT_ACLK_FSYS1_200 1
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#define DOUT_ACLK_FSYS0_200 2
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#define DOUT_SCLK_MMC2 3
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#define DOUT_SCLK_MMC1 4
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#define DOUT_SCLK_MMC0 5
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#define CLK_SCLK_MMC2 6
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#define CLK_SCLK_MMC1 7
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#define CLK_SCLK_MMC0 8
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#define CLK_ACLK_FSYS0_200 9
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#define CLK_ACLK_FSYS1_200 10
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#define CLK_SCLK_PHY_FSYS1 11
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#define CLK_SCLK_PHY_FSYS1_26M 12
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#define MOUT_SCLK_UFSUNIPRO20 13
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#define DOUT_SCLK_UFSUNIPRO20 14
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#define CLK_SCLK_UFSUNIPRO20 15
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#define DOUT_SCLK_PHY_FSYS1 16
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#define DOUT_SCLK_PHY_FSYS1_26M 17
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#define TOP1_NR_CLK 18
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/* CCORE */
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#define PCLK_RTC 1
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#define CCORE_NR_CLK 2
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/* PERIC0 */
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#define PCLK_UART0 1
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#define SCLK_UART0 2
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#define PCLK_HSI2C0 3
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#define PCLK_HSI2C1 4
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#define PCLK_HSI2C4 5
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#define PCLK_HSI2C5 6
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#define PCLK_HSI2C9 7
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#define PCLK_HSI2C10 8
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#define PCLK_HSI2C11 9
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#define PCLK_PWM 10
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#define SCLK_PWM 11
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#define PCLK_ADCIF 12
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#define PERIC0_NR_CLK 13
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/* PERIC1 */
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#define PCLK_UART1 1
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#define PCLK_UART2 2
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#define PCLK_UART3 3
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#define SCLK_UART1 4
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#define SCLK_UART2 5
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#define SCLK_UART3 6
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#define PCLK_HSI2C2 7
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#define PCLK_HSI2C3 8
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#define PCLK_HSI2C6 9
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#define PCLK_HSI2C7 10
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#define PCLK_HSI2C8 11
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#define PCLK_SPI0 12
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#define PCLK_SPI1 13
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#define PCLK_SPI2 14
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#define PCLK_SPI3 15
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#define PCLK_SPI4 16
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#define SCLK_SPI0 17
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#define SCLK_SPI1 18
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#define SCLK_SPI2 19
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#define SCLK_SPI3 20
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#define SCLK_SPI4 21
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#define PCLK_I2S1 22
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#define PCLK_PCM1 23
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#define PCLK_SPDIF 24
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#define SCLK_I2S1 25
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#define SCLK_PCM1 26
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#define SCLK_SPDIF 27
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#define PERIC1_NR_CLK 28
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/* PERIS */
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#define PCLK_CHIPID 1
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#define SCLK_CHIPID 2
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#define PCLK_WDT 3
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#define PCLK_TMU 4
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#define SCLK_TMU 5
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#define PERIS_NR_CLK 6
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/* FSYS0 */
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#define ACLK_MMC2 1
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#define ACLK_AXIUS_USBDRD30X_FSYS0X 2
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#define ACLK_USBDRD300 3
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#define SCLK_USBDRD300_SUSPENDCLK 4
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#define SCLK_USBDRD300_REFCLK 5
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#define PHYCLK_USBDRD300_UDRD30_PIPE_PCLK_USER 6
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#define PHYCLK_USBDRD300_UDRD30_PHYCLK_USER 7
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#define OSCCLK_PHY_CLKOUT_USB30_PHY 8
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#define ACLK_PDMA0 9
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#define ACLK_PDMA1 10
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#define FSYS0_NR_CLK 11
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/* FSYS1 */
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#define ACLK_MMC1 1
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#define ACLK_MMC0 2
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#define PHYCLK_UFS20_TX0_SYMBOL 3
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#define PHYCLK_UFS20_RX0_SYMBOL 4
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#define PHYCLK_UFS20_RX1_SYMBOL 5
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#define ACLK_UFS20_LINK 6
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#define SCLK_UFSUNIPRO20_USER 7
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#define PHYCLK_UFS20_RX1_SYMBOL_USER 8
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#define PHYCLK_UFS20_RX0_SYMBOL_USER 9
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#define PHYCLK_UFS20_TX0_SYMBOL_USER 10
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#define OSCCLK_PHY_CLKOUT_EMBEDDED_COMBO_PHY 11
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#define SCLK_COMBO_PHY_EMBEDDED_26M 12
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#define DOUT_PCLK_FSYS1 13
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#define PCLK_GPIO_FSYS1 14
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#define MOUT_FSYS1_PHYCLK_SEL1 15
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#define FSYS1_NR_CLK 16
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/* MSCL */
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#define USERMUX_ACLK_MSCL_532 1
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#define DOUT_PCLK_MSCL 2
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#define ACLK_MSCL_0 3
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#define ACLK_MSCL_1 4
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#define ACLK_JPEG 5
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#define ACLK_G2D 6
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#define ACLK_LH_ASYNC_SI_MSCL_0 7
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#define ACLK_LH_ASYNC_SI_MSCL_1 8
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#define ACLK_AXI2ACEL_BRIDGE 9
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#define ACLK_XIU_MSCLX_0 10
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#define ACLK_XIU_MSCLX_1 11
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#define ACLK_QE_MSCL_0 12
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#define ACLK_QE_MSCL_1 13
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#define ACLK_QE_JPEG 14
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#define ACLK_QE_G2D 15
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#define ACLK_PPMU_MSCL_0 16
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#define ACLK_PPMU_MSCL_1 17
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#define ACLK_MSCLNP_133 18
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#define ACLK_AHB2APB_MSCL0P 19
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#define ACLK_AHB2APB_MSCL1P 20
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#define PCLK_MSCL_0 21
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#define PCLK_MSCL_1 22
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#define PCLK_JPEG 23
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#define PCLK_G2D 24
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#define PCLK_QE_MSCL_0 25
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#define PCLK_QE_MSCL_1 26
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#define PCLK_QE_JPEG 27
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#define PCLK_QE_G2D 28
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#define PCLK_PPMU_MSCL_0 29
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#define PCLK_PPMU_MSCL_1 30
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#define PCLK_AXI2ACEL_BRIDGE 31
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#define PCLK_PMU_MSCL 32
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#define MSCL_NR_CLK 33
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/* AUD */
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#define SCLK_I2S 1
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#define SCLK_PCM 2
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#define PCLK_I2S 3
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#define PCLK_PCM 4
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#define ACLK_ADMA 5
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#define AUD_NR_CLK 6
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#endif /* _DT_BINDINGS_CLOCK_EXYNOS7_H */
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