521 lines
13 KiB
C
521 lines
13 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef __RADEONFB_H__
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#define __RADEONFB_H__
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#ifdef CONFIG_FB_RADEON_DEBUG
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#define DEBUG 1
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#endif
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/sched.h>
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#include <linux/delay.h>
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#include <linux/pci.h>
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#include <linux/fb.h>
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#ifdef CONFIG_FB_RADEON_I2C
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#include <linux/i2c.h>
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#include <linux/i2c-algo-bit.h>
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#endif
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#include <asm/io.h>
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#ifdef CONFIG_SPARC
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#include <asm/prom.h>
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#endif
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#include <video/radeon.h>
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/***************************************************************
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* Most of the definitions here are adapted right from XFree86 *
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***************************************************************/
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/*
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* Chip families. Must fit in the low 16 bits of a long word
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*/
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enum radeon_family {
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CHIP_FAMILY_UNKNOW,
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CHIP_FAMILY_LEGACY,
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CHIP_FAMILY_RADEON,
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CHIP_FAMILY_RV100,
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CHIP_FAMILY_RS100, /* U1 (IGP320M) or A3 (IGP320)*/
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CHIP_FAMILY_RV200,
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CHIP_FAMILY_RS200, /* U2 (IGP330M/340M/350M) or A4 (IGP330/340/345/350),
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RS250 (IGP 7000) */
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CHIP_FAMILY_R200,
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CHIP_FAMILY_RV250,
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CHIP_FAMILY_RS300, /* Radeon 9000 IGP */
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CHIP_FAMILY_RV280,
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CHIP_FAMILY_R300,
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CHIP_FAMILY_R350,
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CHIP_FAMILY_RV350,
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CHIP_FAMILY_RV380, /* RV370/RV380/M22/M24 */
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CHIP_FAMILY_R420, /* R420/R423/M18 */
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CHIP_FAMILY_RC410,
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CHIP_FAMILY_RS400,
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CHIP_FAMILY_RS480,
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CHIP_FAMILY_LAST,
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};
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#define IS_RV100_VARIANT(rinfo) (((rinfo)->family == CHIP_FAMILY_RV100) || \
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((rinfo)->family == CHIP_FAMILY_RV200) || \
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((rinfo)->family == CHIP_FAMILY_RS100) || \
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((rinfo)->family == CHIP_FAMILY_RS200) || \
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((rinfo)->family == CHIP_FAMILY_RV250) || \
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((rinfo)->family == CHIP_FAMILY_RV280) || \
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((rinfo)->family == CHIP_FAMILY_RS300))
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#define IS_R300_VARIANT(rinfo) (((rinfo)->family == CHIP_FAMILY_R300) || \
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((rinfo)->family == CHIP_FAMILY_RV350) || \
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((rinfo)->family == CHIP_FAMILY_R350) || \
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((rinfo)->family == CHIP_FAMILY_RV380) || \
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((rinfo)->family == CHIP_FAMILY_R420) || \
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((rinfo)->family == CHIP_FAMILY_RC410) || \
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((rinfo)->family == CHIP_FAMILY_RS480))
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/*
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* Chip flags
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*/
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enum radeon_chip_flags {
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CHIP_FAMILY_MASK = 0x0000ffffUL,
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CHIP_FLAGS_MASK = 0xffff0000UL,
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CHIP_IS_MOBILITY = 0x00010000UL,
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CHIP_IS_IGP = 0x00020000UL,
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CHIP_HAS_CRTC2 = 0x00040000UL,
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};
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/*
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* Errata workarounds
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*/
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enum radeon_errata {
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CHIP_ERRATA_R300_CG = 0x00000001,
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CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
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CHIP_ERRATA_PLL_DELAY = 0x00000004,
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};
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/*
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* Monitor types
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*/
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enum radeon_montype {
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MT_NONE = 0,
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MT_CRT, /* CRT */
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MT_LCD, /* LCD */
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MT_DFP, /* DVI */
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MT_CTV, /* composite TV */
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MT_STV /* S-Video out */
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};
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/*
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* DDC i2c ports
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*/
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enum ddc_type {
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ddc_none,
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ddc_monid,
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ddc_dvi,
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ddc_vga,
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ddc_crt2,
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};
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/*
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* Connector types
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*/
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enum conn_type {
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conn_none,
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conn_proprietary,
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conn_crt,
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conn_DVI_I,
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conn_DVI_D,
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};
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/*
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* PLL infos
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*/
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struct pll_info {
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int ppll_max;
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int ppll_min;
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int sclk, mclk;
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int ref_div;
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int ref_clk;
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};
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/*
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* This structure contains the various registers manipulated by this
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* driver for setting or restoring a mode. It's mostly copied from
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* XFree's RADEONSaveRec structure. A few chip settings might still be
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* tweaked without beeing reflected or saved in these registers though
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*/
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struct radeon_regs {
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/* Common registers */
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u32 ovr_clr;
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u32 ovr_wid_left_right;
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u32 ovr_wid_top_bottom;
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u32 ov0_scale_cntl;
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u32 mpp_tb_config;
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u32 mpp_gp_config;
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u32 subpic_cntl;
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u32 viph_control;
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u32 i2c_cntl_1;
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u32 gen_int_cntl;
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u32 cap0_trig_cntl;
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u32 cap1_trig_cntl;
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u32 bus_cntl;
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u32 surface_cntl;
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u32 bios_5_scratch;
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/* Other registers to save for VT switches or driver load/unload */
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u32 dp_datatype;
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u32 rbbm_soft_reset;
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u32 clock_cntl_index;
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u32 amcgpio_en_reg;
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u32 amcgpio_mask;
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/* Surface/tiling registers */
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u32 surf_lower_bound[8];
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u32 surf_upper_bound[8];
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u32 surf_info[8];
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/* CRTC registers */
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u32 crtc_gen_cntl;
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u32 crtc_ext_cntl;
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u32 dac_cntl;
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u32 crtc_h_total_disp;
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u32 crtc_h_sync_strt_wid;
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u32 crtc_v_total_disp;
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u32 crtc_v_sync_strt_wid;
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u32 crtc_offset;
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u32 crtc_offset_cntl;
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u32 crtc_pitch;
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u32 disp_merge_cntl;
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u32 grph_buffer_cntl;
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u32 crtc_more_cntl;
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/* CRTC2 registers */
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u32 crtc2_gen_cntl;
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u32 dac2_cntl;
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u32 disp_output_cntl;
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u32 disp_hw_debug;
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u32 disp2_merge_cntl;
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u32 grph2_buffer_cntl;
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u32 crtc2_h_total_disp;
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u32 crtc2_h_sync_strt_wid;
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u32 crtc2_v_total_disp;
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u32 crtc2_v_sync_strt_wid;
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u32 crtc2_offset;
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u32 crtc2_offset_cntl;
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u32 crtc2_pitch;
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/* Flat panel regs */
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u32 fp_crtc_h_total_disp;
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u32 fp_crtc_v_total_disp;
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u32 fp_gen_cntl;
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u32 fp2_gen_cntl;
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u32 fp_h_sync_strt_wid;
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u32 fp2_h_sync_strt_wid;
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u32 fp_horz_stretch;
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u32 fp_panel_cntl;
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u32 fp_v_sync_strt_wid;
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u32 fp2_v_sync_strt_wid;
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u32 fp_vert_stretch;
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u32 lvds_gen_cntl;
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u32 lvds_pll_cntl;
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u32 tmds_crc;
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u32 tmds_transmitter_cntl;
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/* Computed values for PLL */
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u32 dot_clock_freq;
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int feedback_div;
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int post_div;
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/* PLL registers */
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u32 ppll_div_3;
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u32 ppll_ref_div;
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u32 vclk_ecp_cntl;
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u32 clk_cntl_index;
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/* Computed values for PLL2 */
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u32 dot_clock_freq_2;
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int feedback_div_2;
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int post_div_2;
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/* PLL2 registers */
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u32 p2pll_ref_div;
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u32 p2pll_div_0;
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u32 htotal_cntl2;
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/* Palette */
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int palette_valid;
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};
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struct panel_info {
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int xres, yres;
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int valid;
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int clock;
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int hOver_plus, hSync_width, hblank;
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int vOver_plus, vSync_width, vblank;
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int hAct_high, vAct_high, interlaced;
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int pwr_delay;
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int use_bios_dividers;
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int ref_divider;
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int post_divider;
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int fbk_divider;
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};
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struct radeonfb_info;
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#ifdef CONFIG_FB_RADEON_I2C
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struct radeon_i2c_chan {
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struct radeonfb_info *rinfo;
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u32 ddc_reg;
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struct i2c_adapter adapter;
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struct i2c_algo_bit_data algo;
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};
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#endif
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enum radeon_pm_mode {
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radeon_pm_none = 0, /* Nothing supported */
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radeon_pm_d2 = 0x00000001, /* Can do D2 state */
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radeon_pm_off = 0x00000002, /* Can resume from D3 cold */
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};
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typedef void (*reinit_function_ptr)(struct radeonfb_info *rinfo);
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struct radeonfb_info {
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struct fb_info *info;
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struct radeon_regs state;
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struct radeon_regs init_state;
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char name[50];
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unsigned long mmio_base_phys;
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unsigned long fb_base_phys;
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void __iomem *mmio_base;
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void __iomem *fb_base;
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unsigned long fb_local_base;
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struct pci_dev *pdev;
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#if defined(CONFIG_PPC) || defined(CONFIG_SPARC)
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struct device_node *of_node;
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#endif
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void __iomem *bios_seg;
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int fp_bios_start;
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u32 pseudo_palette[16];
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struct { u8 red, green, blue, pad; }
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palette[256];
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int chipset;
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u8 family;
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u8 rev;
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unsigned int errata;
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unsigned long video_ram;
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unsigned long mapped_vram;
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int vram_width;
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int vram_ddr;
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int pitch, bpp, depth;
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int has_CRTC2;
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int is_mobility;
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int is_IGP;
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int reversed_DAC;
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int reversed_TMDS;
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struct panel_info panel_info;
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int mon1_type;
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u8 *mon1_EDID;
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struct fb_videomode *mon1_modedb;
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int mon1_dbsize;
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int mon2_type;
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u8 *mon2_EDID;
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u32 dp_gui_master_cntl;
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struct pll_info pll;
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int wc_cookie;
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u32 save_regs[100];
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int asleep;
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int lock_blank;
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int dynclk;
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int no_schedule;
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enum radeon_pm_mode pm_mode;
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reinit_function_ptr reinit_func;
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/* Lock on register access */
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spinlock_t reg_lock;
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/* Timer used for delayed LVDS operations */
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struct timer_list lvds_timer;
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u32 pending_lvds_gen_cntl;
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#ifdef CONFIG_FB_RADEON_I2C
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struct radeon_i2c_chan i2c[4];
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#endif
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};
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#define PRIMARY_MONITOR(rinfo) (rinfo->mon1_type)
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/*
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* IO macros
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*/
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void _radeon_msleep(struct radeonfb_info *rinfo, unsigned long ms);
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#define INREG8(addr) readb((rinfo->mmio_base)+addr)
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#define OUTREG8(addr,val) writeb(val, (rinfo->mmio_base)+addr)
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#define INREG16(addr) readw((rinfo->mmio_base)+addr)
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#define OUTREG16(addr,val) writew(val, (rinfo->mmio_base)+addr)
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#define INREG(addr) readl((rinfo->mmio_base)+addr)
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#define OUTREG(addr,val) writel(val, (rinfo->mmio_base)+addr)
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void _OUTREGP(struct radeonfb_info *rinfo, u32 addr, u32 val, u32 mask);
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#define OUTREGP(addr,val,mask) _OUTREGP(rinfo, addr, val,mask)
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/*
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* Note about PLL register accesses:
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*
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* I have removed the spinlock on them on purpose. The driver now
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* expects that it will only manipulate the PLL registers in normal
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* task environment, where radeon_msleep() will be called, protected
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* by a semaphore (currently the console semaphore) so that no conflict
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* will happen on the PLL register index.
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*
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* With the latest changes to the VT layer, this is guaranteed for all
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* calls except the actual drawing/blits which aren't supposed to use
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* the PLL registers anyway
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*
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* This is very important for the workarounds to work properly. The only
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* possible exception to this rule is the call to unblank(), which may
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* be done at irq time if an oops is in progress.
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*/
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void radeon_pll_errata_after_index_slow(struct radeonfb_info *rinfo);
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static inline void radeon_pll_errata_after_index(struct radeonfb_info *rinfo)
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{
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if (rinfo->errata & CHIP_ERRATA_PLL_DUMMYREADS)
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radeon_pll_errata_after_index_slow(rinfo);
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}
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void radeon_pll_errata_after_data_slow(struct radeonfb_info *rinfo);
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static inline void radeon_pll_errata_after_data(struct radeonfb_info *rinfo)
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{
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if (rinfo->errata & (CHIP_ERRATA_PLL_DELAY|CHIP_ERRATA_R300_CG))
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radeon_pll_errata_after_data_slow(rinfo);
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}
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u32 __INPLL(struct radeonfb_info *rinfo, u32 addr);
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void __OUTPLL(struct radeonfb_info *rinfo, unsigned int index, u32 val);
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void __OUTPLLP(struct radeonfb_info *rinfo, unsigned int index,
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u32 val, u32 mask);
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#define INPLL(addr) __INPLL(rinfo, addr)
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#define OUTPLL(index, val) __OUTPLL(rinfo, index, val)
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#define OUTPLLP(index, val, mask) __OUTPLLP(rinfo, index, val, mask)
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#define BIOS_IN8(v) (readb(rinfo->bios_seg + (v)))
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#define BIOS_IN16(v) (readb(rinfo->bios_seg + (v)) | \
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(readb(rinfo->bios_seg + (v) + 1) << 8))
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#define BIOS_IN32(v) (readb(rinfo->bios_seg + (v)) | \
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(readb(rinfo->bios_seg + (v) + 1) << 8) | \
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(readb(rinfo->bios_seg + (v) + 2) << 16) | \
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(readb(rinfo->bios_seg + (v) + 3) << 24))
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/*
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* Inline utilities
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*/
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static inline int round_div(int num, int den)
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{
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return (num + (den / 2)) / den;
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}
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static inline int var_to_depth(const struct fb_var_screeninfo *var)
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{
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if (var->bits_per_pixel != 16)
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return var->bits_per_pixel;
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return (var->green.length == 5) ? 15 : 16;
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}
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static inline u32 radeon_get_dstbpp(u16 depth)
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{
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switch (depth) {
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case 8:
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return DST_8BPP;
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case 15:
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return DST_15BPP;
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case 16:
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return DST_16BPP;
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case 32:
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return DST_32BPP;
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default:
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return 0;
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}
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}
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/*
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* 2D Engine helper routines
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*/
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void _radeon_fifo_wait(struct radeonfb_info *rinfo, int entries);
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void radeon_engine_flush(struct radeonfb_info *rinfo);
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void _radeon_engine_idle(struct radeonfb_info *rinfo);
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#define radeon_engine_idle() _radeon_engine_idle(rinfo)
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#define radeon_fifo_wait(entries) _radeon_fifo_wait(rinfo,entries)
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#define radeon_msleep(ms) _radeon_msleep(rinfo,ms)
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/* I2C Functions */
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extern void radeon_create_i2c_busses(struct radeonfb_info *rinfo);
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extern void radeon_delete_i2c_busses(struct radeonfb_info *rinfo);
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extern int radeon_probe_i2c_connector(struct radeonfb_info *rinfo, int conn, u8 **out_edid);
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/* PM Functions */
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extern const struct dev_pm_ops radeonfb_pci_pm_ops;
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extern void radeonfb_pm_init(struct radeonfb_info *rinfo, int dynclk, int ignore_devlist, int force_sleep);
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extern void radeonfb_pm_exit(struct radeonfb_info *rinfo);
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/* Monitor probe functions */
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extern void radeon_probe_screens(struct radeonfb_info *rinfo,
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const char *monitor_layout, int ignore_edid);
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extern void radeon_check_modes(struct radeonfb_info *rinfo, const char *mode_option);
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extern int radeon_match_mode(struct radeonfb_info *rinfo,
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struct fb_var_screeninfo *dest,
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const struct fb_var_screeninfo *src);
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/* Accel functions */
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extern void radeonfb_fillrect(struct fb_info *info, const struct fb_fillrect *region);
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extern void radeonfb_copyarea(struct fb_info *info, const struct fb_copyarea *area);
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extern void radeonfb_imageblit(struct fb_info *p, const struct fb_image *image);
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extern int radeonfb_sync(struct fb_info *info);
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extern void radeonfb_engine_init (struct radeonfb_info *rinfo);
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extern void radeonfb_engine_reset(struct radeonfb_info *rinfo);
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/* Other functions */
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extern int radeon_screen_blank(struct radeonfb_info *rinfo, int blank, int mode_switch);
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extern void radeon_write_mode (struct radeonfb_info *rinfo, struct radeon_regs *mode,
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int reg_only);
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/* Backlight functions */
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#ifdef CONFIG_FB_RADEON_BACKLIGHT
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extern void radeonfb_bl_init(struct radeonfb_info *rinfo);
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extern void radeonfb_bl_exit(struct radeonfb_info *rinfo);
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#else
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static inline void radeonfb_bl_init(struct radeonfb_info *rinfo) {}
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static inline void radeonfb_bl_exit(struct radeonfb_info *rinfo) {}
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#endif
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#endif /* __RADEONFB_H__ */
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