171 lines
4.1 KiB
C
171 lines
4.1 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2014 NVIDIA CORPORATION. All rights reserved.
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*/
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#define dev_fmt(fmt) "tegra-soc: " fmt
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#include <linux/clk.h>
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#include <linux/device.h>
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#include <linux/export.h>
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#include <linux/of.h>
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#include <linux/pm_opp.h>
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#include <linux/pm_runtime.h>
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#include <soc/tegra/common.h>
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#include <soc/tegra/fuse.h>
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static const struct of_device_id tegra_machine_match[] = {
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{ .compatible = "nvidia,tegra20", },
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{ .compatible = "nvidia,tegra30", },
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{ .compatible = "nvidia,tegra114", },
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{ .compatible = "nvidia,tegra124", },
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{ .compatible = "nvidia,tegra132", },
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{ .compatible = "nvidia,tegra210", },
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{ }
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};
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bool soc_is_tegra(void)
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{
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const struct of_device_id *match;
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struct device_node *root;
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root = of_find_node_by_path("/");
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if (!root)
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return false;
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match = of_match_node(tegra_machine_match, root);
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of_node_put(root);
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return match != NULL;
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}
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static int tegra_core_dev_init_opp_state(struct device *dev)
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{
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unsigned long rate;
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struct clk *clk;
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bool rpm_enabled;
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int err;
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clk = devm_clk_get(dev, NULL);
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if (IS_ERR(clk)) {
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dev_err(dev, "failed to get clk: %pe\n", clk);
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return PTR_ERR(clk);
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}
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rate = clk_get_rate(clk);
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if (!rate) {
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dev_err(dev, "failed to get clk rate\n");
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return -EINVAL;
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}
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/*
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* Runtime PM of the device must be enabled in order to set up
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* GENPD's performance properly because GENPD core checks whether
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* device is suspended and this check doesn't work while RPM is
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* disabled. This makes sure the OPP vote below gets cached in
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* GENPD for the device. Instead, the vote is done the next time
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* the device gets runtime resumed.
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*/
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rpm_enabled = pm_runtime_enabled(dev);
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if (!rpm_enabled)
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pm_runtime_enable(dev);
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/* should never happen in practice */
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if (!pm_runtime_enabled(dev)) {
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dev_WARN(dev, "failed to enable runtime PM\n");
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pm_runtime_disable(dev);
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return -EINVAL;
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}
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/* first dummy rate-setting initializes voltage vote */
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err = dev_pm_opp_set_rate(dev, rate);
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if (!rpm_enabled)
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pm_runtime_disable(dev);
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if (err) {
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dev_err(dev, "failed to initialize OPP clock: %d\n", err);
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return err;
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}
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return 0;
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}
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/**
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* devm_tegra_core_dev_init_opp_table() - initialize OPP table
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* @dev: device for which OPP table is initialized
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* @params: pointer to the OPP table configuration
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*
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* This function will initialize OPP table and sync OPP state of a Tegra SoC
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* core device.
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*
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* Return: 0 on success or errorno.
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*/
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int devm_tegra_core_dev_init_opp_table(struct device *dev,
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struct tegra_core_opp_params *params)
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{
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u32 hw_version;
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int err;
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/*
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* The clk's connection id to set is NULL and this is a NULL terminated
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* array, hence two NULL entries.
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*/
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const char *clk_names[] = { NULL, NULL };
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struct dev_pm_opp_config config = {
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/*
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* For some devices we don't have any OPP table in the DT, and
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* in order to use the same code path for all the devices, we
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* create a dummy OPP table for them via this. The dummy OPP
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* table is only capable of doing clk_set_rate() on invocation
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* of dev_pm_opp_set_rate() and doesn't provide any other
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* functionality.
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*/
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.clk_names = clk_names,
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};
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if (of_machine_is_compatible("nvidia,tegra20")) {
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hw_version = BIT(tegra_sku_info.soc_process_id);
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config.supported_hw = &hw_version;
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config.supported_hw_count = 1;
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} else if (of_machine_is_compatible("nvidia,tegra30")) {
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hw_version = BIT(tegra_sku_info.soc_speedo_id);
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config.supported_hw = &hw_version;
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config.supported_hw_count = 1;
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}
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err = devm_pm_opp_set_config(dev, &config);
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if (err) {
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dev_err(dev, "failed to set OPP config: %d\n", err);
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return err;
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}
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/*
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* Tegra114+ doesn't support OPP yet, return early for non tegra20/30
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* case.
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*/
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if (!config.supported_hw)
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return -ENODEV;
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/*
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* Older device-trees have an empty OPP table, we will get
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* -ENODEV from devm_pm_opp_of_add_table() in this case.
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*/
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err = devm_pm_opp_of_add_table(dev);
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if (err) {
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if (err != -ENODEV)
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dev_err(dev, "failed to add OPP table: %d\n", err);
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return err;
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}
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if (params->init_state) {
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err = tegra_core_dev_init_opp_state(dev);
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if (err)
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return err;
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}
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return 0;
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}
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EXPORT_SYMBOL_GPL(devm_tegra_core_dev_init_opp_table);
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