478 lines
8.5 KiB
C
478 lines
8.5 KiB
C
/* SPDX-License-Identifier: ISC */
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/* Copyright (C) 2020 MediaTek Inc. */
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#ifndef __MT7915_MCU_H
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#define __MT7915_MCU_H
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#include "../mt76_connac_mcu.h"
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enum {
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MCU_ATE_SET_TRX = 0x1,
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MCU_ATE_SET_FREQ_OFFSET = 0xa,
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MCU_ATE_SET_SLOT_TIME = 0x13,
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MCU_ATE_CLEAN_TXQUEUE = 0x1c,
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};
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struct mt7915_mcu_thermal_ctrl {
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u8 ctrl_id;
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u8 band_idx;
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union {
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struct {
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u8 protect_type; /* 1: duty admit, 2: radio off */
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u8 trigger_type; /* 0: low, 1: high */
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} __packed type;
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struct {
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u8 duty_level; /* level 0~3 */
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u8 duty_cycle;
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} __packed duty;
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};
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} __packed;
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struct mt7915_mcu_thermal_notify {
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struct mt76_connac2_mcu_rxd rxd;
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struct mt7915_mcu_thermal_ctrl ctrl;
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__le32 temperature;
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u8 rsv[8];
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} __packed;
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struct mt7915_mcu_csa_notify {
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struct mt76_connac2_mcu_rxd rxd;
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u8 omac_idx;
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u8 csa_count;
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u8 band_idx;
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u8 rsv;
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} __packed;
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struct mt7915_mcu_bcc_notify {
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struct mt76_connac2_mcu_rxd rxd;
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u8 band_idx;
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u8 omac_idx;
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u8 cca_count;
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u8 rsv;
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} __packed;
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struct mt7915_mcu_rdd_report {
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struct mt76_connac2_mcu_rxd rxd;
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u8 band_idx;
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u8 long_detected;
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u8 constant_prf_detected;
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u8 staggered_prf_detected;
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u8 radar_type_idx;
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u8 periodic_pulse_num;
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u8 long_pulse_num;
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u8 hw_pulse_num;
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u8 out_lpn;
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u8 out_spn;
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u8 out_crpn;
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u8 out_crpw;
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u8 out_crbn;
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u8 out_stgpn;
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u8 out_stgpw;
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u8 rsv;
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__le32 out_pri_const;
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__le32 out_pri_stg[3];
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struct {
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__le32 start;
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__le16 pulse_width;
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__le16 pulse_power;
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u8 mdrdy_flag;
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u8 rsv[3];
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} long_pulse[32];
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struct {
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__le32 start;
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__le16 pulse_width;
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__le16 pulse_power;
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u8 mdrdy_flag;
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u8 rsv[3];
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} periodic_pulse[32];
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struct {
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__le32 start;
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__le16 pulse_width;
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__le16 pulse_power;
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u8 sc_pass;
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u8 sw_reset;
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u8 mdrdy_flag;
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u8 tx_active;
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} hw_pulse[32];
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} __packed;
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struct mt7915_mcu_background_chain_ctrl {
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u8 chan; /* primary channel */
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u8 central_chan; /* central channel */
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u8 bw;
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u8 tx_stream;
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u8 rx_stream;
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u8 monitor_chan; /* monitor channel */
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u8 monitor_central_chan;/* monitor central channel */
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u8 monitor_bw;
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u8 monitor_tx_stream;
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u8 monitor_rx_stream;
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u8 scan_mode; /* 0: ScanStop
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* 1: ScanStart
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* 2: ScanRunning
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*/
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u8 band_idx; /* DBDC */
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u8 monitor_scan_type;
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u8 band; /* 0: 2.4GHz, 1: 5GHz */
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u8 rsv[2];
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} __packed;
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struct mt7915_mcu_eeprom {
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u8 buffer_mode;
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u8 format;
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__le16 len;
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} __packed;
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struct mt7915_mcu_eeprom_info {
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__le32 addr;
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__le32 valid;
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u8 data[16];
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} __packed;
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struct mt7915_mcu_phy_rx_info {
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u8 category;
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u8 rate;
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u8 mode;
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u8 nsts;
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u8 gi;
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u8 coding;
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u8 stbc;
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u8 bw;
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};
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struct mt7915_mcu_mib {
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__le32 band;
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__le32 offs;
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__le64 data;
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} __packed;
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enum mt7915_chan_mib_offs {
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/* mt7915 */
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MIB_BUSY_TIME = 14,
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MIB_TX_TIME = 81,
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MIB_RX_TIME,
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MIB_OBSS_AIRTIME = 86,
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/* mt7916 */
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MIB_BUSY_TIME_V2 = 0,
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MIB_TX_TIME_V2 = 6,
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MIB_RX_TIME_V2 = 8,
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MIB_OBSS_AIRTIME_V2 = 490
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};
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struct edca {
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u8 queue;
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u8 set;
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u8 aifs;
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u8 cw_min;
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__le16 cw_max;
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__le16 txop;
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};
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struct mt7915_mcu_tx {
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u8 total;
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u8 action;
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u8 valid;
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u8 mode;
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struct edca edca[IEEE80211_NUM_ACS];
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} __packed;
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struct mt7915_mcu_muru_stats {
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__le32 event_id;
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struct {
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__le32 cck_cnt;
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__le32 ofdm_cnt;
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__le32 htmix_cnt;
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__le32 htgf_cnt;
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__le32 vht_su_cnt;
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__le32 vht_2mu_cnt;
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__le32 vht_3mu_cnt;
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__le32 vht_4mu_cnt;
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__le32 he_su_cnt;
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__le32 he_ext_su_cnt;
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__le32 he_2ru_cnt;
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__le32 he_2mu_cnt;
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__le32 he_3ru_cnt;
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__le32 he_3mu_cnt;
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__le32 he_4ru_cnt;
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__le32 he_4mu_cnt;
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__le32 he_5to8ru_cnt;
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__le32 he_9to16ru_cnt;
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__le32 he_gtr16ru_cnt;
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} dl;
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struct {
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__le32 hetrig_su_cnt;
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__le32 hetrig_2ru_cnt;
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__le32 hetrig_3ru_cnt;
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__le32 hetrig_4ru_cnt;
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__le32 hetrig_5to8ru_cnt;
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__le32 hetrig_9to16ru_cnt;
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__le32 hetrig_gtr16ru_cnt;
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__le32 hetrig_2mu_cnt;
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__le32 hetrig_3mu_cnt;
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__le32 hetrig_4mu_cnt;
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} ul;
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};
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#define WMM_AIFS_SET BIT(0)
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#define WMM_CW_MIN_SET BIT(1)
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#define WMM_CW_MAX_SET BIT(2)
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#define WMM_TXOP_SET BIT(3)
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#define WMM_PARAM_SET GENMASK(3, 0)
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enum {
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MCU_FW_LOG_WM,
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MCU_FW_LOG_WA,
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MCU_FW_LOG_TO_HOST,
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};
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enum {
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MCU_TWT_AGRT_ADD,
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MCU_TWT_AGRT_MODIFY,
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MCU_TWT_AGRT_DELETE,
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MCU_TWT_AGRT_TEARDOWN,
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MCU_TWT_AGRT_GET_TSF,
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};
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enum {
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MCU_WA_PARAM_CMD_QUERY,
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MCU_WA_PARAM_CMD_SET,
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MCU_WA_PARAM_CMD_CAPABILITY,
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MCU_WA_PARAM_CMD_DEBUG,
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};
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enum {
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MCU_WA_PARAM_PDMA_RX = 0x04,
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MCU_WA_PARAM_CPU_UTIL = 0x0b,
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MCU_WA_PARAM_RED = 0x0e,
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};
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enum mcu_mmps_mode {
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MCU_MMPS_STATIC,
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MCU_MMPS_DYNAMIC,
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MCU_MMPS_RSV,
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MCU_MMPS_DISABLE,
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};
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struct bss_info_bmc_rate {
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__le16 tag;
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__le16 len;
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__le16 bc_trans;
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__le16 mc_trans;
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u8 short_preamble;
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u8 rsv[7];
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} __packed;
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struct bss_info_ra {
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__le16 tag;
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__le16 len;
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u8 op_mode;
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u8 adhoc_en;
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u8 short_preamble;
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u8 tx_streams;
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u8 rx_streams;
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u8 algo;
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u8 force_sgi;
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u8 force_gf;
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u8 ht_mode;
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u8 has_20_sta; /* Check if any sta support GF. */
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u8 bss_width_trigger_events;
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u8 vht_nss_cap;
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u8 vht_bw_signal; /* not use */
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u8 vht_force_sgi; /* not use */
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u8 se_off;
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u8 antenna_idx;
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u8 train_up_rule;
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u8 rsv[3];
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unsigned short train_up_high_thres;
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short train_up_rule_rssi;
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unsigned short low_traffic_thres;
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__le16 max_phyrate;
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__le32 phy_cap;
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__le32 interval;
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__le32 fast_interval;
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} __packed;
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struct bss_info_hw_amsdu {
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__le16 tag;
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__le16 len;
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__le32 cmp_bitmap_0;
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__le32 cmp_bitmap_1;
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__le16 trig_thres;
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u8 enable;
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u8 rsv;
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} __packed;
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struct bss_info_color {
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__le16 tag;
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__le16 len;
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u8 disable;
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u8 color;
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u8 rsv[2];
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} __packed;
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struct bss_info_he {
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__le16 tag;
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__le16 len;
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u8 he_pe_duration;
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u8 vht_op_info_present;
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__le16 he_rts_thres;
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__le16 max_nss_mcs[CMD_HE_MCS_BW_NUM];
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u8 rsv[6];
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} __packed;
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struct bss_info_bcn {
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__le16 tag;
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__le16 len;
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u8 ver;
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u8 enable;
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__le16 sub_ntlv;
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} __packed __aligned(4);
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struct bss_info_bcn_cntdwn {
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__le16 tag;
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__le16 len;
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u8 cnt;
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u8 rsv[3];
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} __packed __aligned(4);
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struct bss_info_bcn_mbss {
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#define MAX_BEACON_NUM 32
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__le16 tag;
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__le16 len;
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__le32 bitmap;
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__le16 offset[MAX_BEACON_NUM];
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u8 rsv[8];
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} __packed __aligned(4);
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struct bss_info_bcn_cont {
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__le16 tag;
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__le16 len;
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__le16 tim_ofs;
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__le16 csa_ofs;
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__le16 bcc_ofs;
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__le16 pkt_len;
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} __packed __aligned(4);
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struct bss_info_inband_discovery {
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__le16 tag;
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__le16 len;
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u8 tx_type;
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u8 tx_mode;
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u8 tx_interval;
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u8 enable;
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__le16 rsv;
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__le16 prob_rsp_len;
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} __packed __aligned(4);
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enum {
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BSS_INFO_BCN_CSA,
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BSS_INFO_BCN_BCC,
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BSS_INFO_BCN_MBSSID,
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BSS_INFO_BCN_CONTENT,
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BSS_INFO_BCN_DISCOV,
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BSS_INFO_BCN_MAX
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};
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enum {
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RATE_PARAM_FIXED = 3,
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RATE_PARAM_MMPS_UPDATE = 5,
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RATE_PARAM_FIXED_HE_LTF = 7,
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RATE_PARAM_FIXED_MCS,
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RATE_PARAM_FIXED_GI = 11,
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RATE_PARAM_AUTO = 20,
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};
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#define RATE_CFG_MCS GENMASK(3, 0)
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#define RATE_CFG_NSS GENMASK(7, 4)
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#define RATE_CFG_GI GENMASK(11, 8)
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#define RATE_CFG_BW GENMASK(15, 12)
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#define RATE_CFG_STBC GENMASK(19, 16)
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#define RATE_CFG_LDPC GENMASK(23, 20)
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#define RATE_CFG_PHY_TYPE GENMASK(27, 24)
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#define RATE_CFG_HE_LTF GENMASK(31, 28)
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enum {
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THERMAL_PROTECT_PARAMETER_CTRL,
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THERMAL_PROTECT_BASIC_INFO,
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THERMAL_PROTECT_ENABLE,
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THERMAL_PROTECT_DISABLE,
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THERMAL_PROTECT_DUTY_CONFIG,
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THERMAL_PROTECT_MECH_INFO,
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THERMAL_PROTECT_DUTY_INFO,
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THERMAL_PROTECT_STATE_ACT,
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};
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enum {
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MT_BF_SOUNDING_ON = 1,
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MT_BF_TYPE_UPDATE = 20,
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MT_BF_MODULE_UPDATE = 25
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};
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enum {
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MURU_SET_ARB_OP_MODE = 14,
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MURU_SET_PLATFORM_TYPE = 25,
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};
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enum {
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MURU_PLATFORM_TYPE_PERF_LEVEL_1 = 1,
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MURU_PLATFORM_TYPE_PERF_LEVEL_2,
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};
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/* tx cmd tx statistics */
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enum {
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MURU_SET_TXC_TX_STATS_EN = 150,
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MURU_GET_TXC_TX_STATS = 151,
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};
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enum {
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SER_QUERY,
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/* recovery */
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SER_SET_RECOVER_L1,
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SER_SET_RECOVER_L2,
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SER_SET_RECOVER_L3_RX_ABORT,
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SER_SET_RECOVER_L3_TX_ABORT,
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SER_SET_RECOVER_L3_TX_DISABLE,
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SER_SET_RECOVER_L3_BF,
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/* action */
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SER_ENABLE = 2,
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SER_RECOVER
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};
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#define MT7915_MAX_BEACON_SIZE 512
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#define MT7915_MAX_INBAND_FRAME_SIZE 256
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#define MT7915_MAX_BSS_OFFLOAD_SIZE (MT7915_MAX_BEACON_SIZE + \
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MT7915_MAX_INBAND_FRAME_SIZE + \
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MT7915_BEACON_UPDATE_SIZE)
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#define MT7915_BSS_UPDATE_MAX_SIZE (sizeof(struct sta_req_hdr) + \
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sizeof(struct bss_info_omac) + \
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sizeof(struct bss_info_basic) +\
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sizeof(struct bss_info_rf_ch) +\
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sizeof(struct bss_info_ra) + \
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sizeof(struct bss_info_hw_amsdu) +\
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sizeof(struct bss_info_he) + \
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sizeof(struct bss_info_bmc_rate) +\
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sizeof(struct bss_info_ext_bss))
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#define MT7915_BEACON_UPDATE_SIZE (sizeof(struct sta_req_hdr) + \
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sizeof(struct bss_info_bcn_cntdwn) + \
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sizeof(struct bss_info_bcn_mbss) + \
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sizeof(struct bss_info_bcn_cont) + \
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sizeof(struct bss_info_inband_discovery))
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#endif
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