488 lines
14 KiB
C
488 lines
14 KiB
C
// SPDX-License-Identifier: ISC
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/* Copyright (C) 2020 MediaTek Inc. */
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#include "mt7915.h"
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#include "../dma.h"
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#include "mac.h"
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static int
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mt7915_init_tx_queues(struct mt7915_phy *phy, int idx, int n_desc, int ring_base)
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{
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struct mt7915_dev *dev = phy->dev;
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if (mtk_wed_device_active(&phy->dev->mt76.mmio.wed)) {
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ring_base = MT_WED_TX_RING_BASE;
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idx -= MT_TXQ_ID(0);
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}
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return mt76_connac_init_tx_queues(phy->mt76, idx, n_desc, ring_base,
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MT_WED_Q_TX(idx));
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}
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static int mt7915_poll_tx(struct napi_struct *napi, int budget)
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{
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struct mt7915_dev *dev;
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dev = container_of(napi, struct mt7915_dev, mt76.tx_napi);
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mt76_connac_tx_cleanup(&dev->mt76);
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if (napi_complete_done(napi, 0))
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mt7915_irq_enable(dev, MT_INT_TX_DONE_MCU);
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return 0;
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}
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static void mt7915_dma_config(struct mt7915_dev *dev)
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{
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#define Q_CONFIG(q, wfdma, int, id) do { \
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if (wfdma) \
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dev->wfdma_mask |= (1 << (q)); \
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dev->q_int_mask[(q)] = int; \
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dev->q_id[(q)] = id; \
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} while (0)
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#define MCUQ_CONFIG(q, wfdma, int, id) Q_CONFIG(q, (wfdma), (int), (id))
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#define RXQ_CONFIG(q, wfdma, int, id) Q_CONFIG(__RXQ(q), (wfdma), (int), (id))
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#define TXQ_CONFIG(q, wfdma, int, id) Q_CONFIG(__TXQ(q), (wfdma), (int), (id))
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if (is_mt7915(&dev->mt76)) {
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RXQ_CONFIG(MT_RXQ_MAIN, WFDMA0, MT_INT_RX_DONE_BAND0, MT7915_RXQ_BAND0);
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RXQ_CONFIG(MT_RXQ_MCU, WFDMA1, MT_INT_RX_DONE_WM, MT7915_RXQ_MCU_WM);
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RXQ_CONFIG(MT_RXQ_MCU_WA, WFDMA1, MT_INT_RX_DONE_WA, MT7915_RXQ_MCU_WA);
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RXQ_CONFIG(MT_RXQ_BAND1, WFDMA0, MT_INT_RX_DONE_BAND1, MT7915_RXQ_BAND1);
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RXQ_CONFIG(MT_RXQ_BAND1_WA, WFDMA1, MT_INT_RX_DONE_WA_EXT, MT7915_RXQ_MCU_WA_EXT);
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RXQ_CONFIG(MT_RXQ_MAIN_WA, WFDMA1, MT_INT_RX_DONE_WA_MAIN, MT7915_RXQ_MCU_WA);
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TXQ_CONFIG(0, WFDMA1, MT_INT_TX_DONE_BAND0, MT7915_TXQ_BAND0);
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TXQ_CONFIG(1, WFDMA1, MT_INT_TX_DONE_BAND1, MT7915_TXQ_BAND1);
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MCUQ_CONFIG(MT_MCUQ_WM, WFDMA1, MT_INT_TX_DONE_MCU_WM, MT7915_TXQ_MCU_WM);
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MCUQ_CONFIG(MT_MCUQ_WA, WFDMA1, MT_INT_TX_DONE_MCU_WA, MT7915_TXQ_MCU_WA);
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MCUQ_CONFIG(MT_MCUQ_FWDL, WFDMA1, MT_INT_TX_DONE_FWDL, MT7915_TXQ_FWDL);
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} else {
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RXQ_CONFIG(MT_RXQ_MAIN, WFDMA0, MT_INT_RX_DONE_BAND0_MT7916, MT7916_RXQ_BAND0);
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RXQ_CONFIG(MT_RXQ_MCU, WFDMA0, MT_INT_RX_DONE_WM, MT7916_RXQ_MCU_WM);
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RXQ_CONFIG(MT_RXQ_MCU_WA, WFDMA0, MT_INT_RX_DONE_WA, MT7916_RXQ_MCU_WA);
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RXQ_CONFIG(MT_RXQ_BAND1, WFDMA0, MT_INT_RX_DONE_BAND1_MT7916, MT7916_RXQ_BAND1);
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RXQ_CONFIG(MT_RXQ_BAND1_WA, WFDMA0, MT_INT_RX_DONE_WA_EXT_MT7916, MT7916_RXQ_MCU_WA_EXT);
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RXQ_CONFIG(MT_RXQ_MAIN_WA, WFDMA0, MT_INT_RX_DONE_WA_MAIN_MT7916, MT7916_RXQ_MCU_WA_MAIN);
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TXQ_CONFIG(0, WFDMA0, MT_INT_TX_DONE_BAND0, MT7915_TXQ_BAND0);
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TXQ_CONFIG(1, WFDMA0, MT_INT_TX_DONE_BAND1, MT7915_TXQ_BAND1);
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MCUQ_CONFIG(MT_MCUQ_WM, WFDMA0, MT_INT_TX_DONE_MCU_WM, MT7915_TXQ_MCU_WM);
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MCUQ_CONFIG(MT_MCUQ_WA, WFDMA0, MT_INT_TX_DONE_MCU_WA_MT7916, MT7915_TXQ_MCU_WA);
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MCUQ_CONFIG(MT_MCUQ_FWDL, WFDMA0, MT_INT_TX_DONE_FWDL, MT7915_TXQ_FWDL);
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}
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}
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static void __mt7915_dma_prefetch(struct mt7915_dev *dev, u32 ofs)
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{
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#define PREFETCH(_base, _depth) ((_base) << 16 | (_depth))
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u32 base = 0;
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/* prefetch SRAM wrapping boundary for tx/rx ring. */
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mt76_wr(dev, MT_MCUQ_EXT_CTRL(MT_MCUQ_FWDL) + ofs, PREFETCH(0x0, 0x4));
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mt76_wr(dev, MT_MCUQ_EXT_CTRL(MT_MCUQ_WM) + ofs, PREFETCH(0x40, 0x4));
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mt76_wr(dev, MT_TXQ_EXT_CTRL(0) + ofs, PREFETCH(0x80, 0x4));
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mt76_wr(dev, MT_TXQ_EXT_CTRL(1) + ofs, PREFETCH(0xc0, 0x4));
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mt76_wr(dev, MT_MCUQ_EXT_CTRL(MT_MCUQ_WA) + ofs, PREFETCH(0x100, 0x4));
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mt76_wr(dev, MT_RXQ_BAND1_CTRL(MT_RXQ_MCU) + ofs,
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PREFETCH(0x140, 0x4));
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mt76_wr(dev, MT_RXQ_BAND1_CTRL(MT_RXQ_MCU_WA) + ofs,
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PREFETCH(0x180, 0x4));
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if (!is_mt7915(&dev->mt76)) {
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mt76_wr(dev, MT_RXQ_BAND1_CTRL(MT_RXQ_MAIN_WA) + ofs,
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PREFETCH(0x1c0, 0x4));
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base = 0x40;
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}
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mt76_wr(dev, MT_RXQ_BAND1_CTRL(MT_RXQ_BAND1_WA) + ofs,
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PREFETCH(0x1c0 + base, 0x4));
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mt76_wr(dev, MT_RXQ_BAND1_CTRL(MT_RXQ_MAIN) + ofs,
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PREFETCH(0x200 + base, 0x4));
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mt76_wr(dev, MT_RXQ_BAND1_CTRL(MT_RXQ_BAND1) + ofs,
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PREFETCH(0x240 + base, 0x4));
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/* for mt7915, the ring which is next the last
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* used ring must be initialized.
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*/
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if (is_mt7915(&dev->mt76)) {
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ofs += 0x4;
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mt76_wr(dev, MT_MCUQ_EXT_CTRL(MT_MCUQ_WA) + ofs,
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PREFETCH(0x140, 0x0));
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mt76_wr(dev, MT_RXQ_BAND1_CTRL(MT_RXQ_BAND1_WA) + ofs,
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PREFETCH(0x200 + base, 0x0));
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mt76_wr(dev, MT_RXQ_BAND1_CTRL(MT_RXQ_BAND1) + ofs,
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PREFETCH(0x280 + base, 0x0));
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}
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}
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void mt7915_dma_prefetch(struct mt7915_dev *dev)
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{
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__mt7915_dma_prefetch(dev, 0);
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if (dev->hif2)
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__mt7915_dma_prefetch(dev, MT_WFDMA0_PCIE1(0) - MT_WFDMA0(0));
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}
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static void mt7915_dma_disable(struct mt7915_dev *dev, bool rst)
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{
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struct mt76_dev *mdev = &dev->mt76;
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u32 hif1_ofs = 0;
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if (dev->hif2)
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hif1_ofs = MT_WFDMA0_PCIE1(0) - MT_WFDMA0(0);
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/* reset */
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if (rst) {
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mt76_clear(dev, MT_WFDMA0_RST,
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MT_WFDMA0_RST_DMASHDL_ALL_RST |
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MT_WFDMA0_RST_LOGIC_RST);
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mt76_set(dev, MT_WFDMA0_RST,
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MT_WFDMA0_RST_DMASHDL_ALL_RST |
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MT_WFDMA0_RST_LOGIC_RST);
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if (is_mt7915(mdev)) {
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mt76_clear(dev, MT_WFDMA1_RST,
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MT_WFDMA1_RST_DMASHDL_ALL_RST |
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MT_WFDMA1_RST_LOGIC_RST);
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mt76_set(dev, MT_WFDMA1_RST,
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MT_WFDMA1_RST_DMASHDL_ALL_RST |
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MT_WFDMA1_RST_LOGIC_RST);
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}
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if (dev->hif2) {
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mt76_clear(dev, MT_WFDMA0_RST + hif1_ofs,
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MT_WFDMA0_RST_DMASHDL_ALL_RST |
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MT_WFDMA0_RST_LOGIC_RST);
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mt76_set(dev, MT_WFDMA0_RST + hif1_ofs,
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MT_WFDMA0_RST_DMASHDL_ALL_RST |
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MT_WFDMA0_RST_LOGIC_RST);
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if (is_mt7915(mdev)) {
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mt76_clear(dev, MT_WFDMA1_RST + hif1_ofs,
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MT_WFDMA1_RST_DMASHDL_ALL_RST |
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MT_WFDMA1_RST_LOGIC_RST);
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mt76_set(dev, MT_WFDMA1_RST + hif1_ofs,
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MT_WFDMA1_RST_DMASHDL_ALL_RST |
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MT_WFDMA1_RST_LOGIC_RST);
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}
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}
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}
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/* disable */
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mt76_clear(dev, MT_WFDMA0_GLO_CFG,
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MT_WFDMA0_GLO_CFG_TX_DMA_EN |
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MT_WFDMA0_GLO_CFG_RX_DMA_EN |
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MT_WFDMA0_GLO_CFG_OMIT_TX_INFO |
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MT_WFDMA0_GLO_CFG_OMIT_RX_INFO |
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MT_WFDMA0_GLO_CFG_OMIT_RX_INFO_PFET2);
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if (is_mt7915(mdev))
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mt76_clear(dev, MT_WFDMA1_GLO_CFG,
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MT_WFDMA1_GLO_CFG_TX_DMA_EN |
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MT_WFDMA1_GLO_CFG_RX_DMA_EN |
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MT_WFDMA1_GLO_CFG_OMIT_TX_INFO |
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MT_WFDMA1_GLO_CFG_OMIT_RX_INFO |
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MT_WFDMA1_GLO_CFG_OMIT_RX_INFO_PFET2);
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if (dev->hif2) {
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mt76_clear(dev, MT_WFDMA0_GLO_CFG + hif1_ofs,
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MT_WFDMA0_GLO_CFG_TX_DMA_EN |
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MT_WFDMA0_GLO_CFG_RX_DMA_EN |
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MT_WFDMA0_GLO_CFG_OMIT_TX_INFO |
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MT_WFDMA0_GLO_CFG_OMIT_RX_INFO |
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MT_WFDMA0_GLO_CFG_OMIT_RX_INFO_PFET2);
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if (is_mt7915(mdev))
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mt76_clear(dev, MT_WFDMA1_GLO_CFG + hif1_ofs,
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MT_WFDMA1_GLO_CFG_TX_DMA_EN |
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MT_WFDMA1_GLO_CFG_RX_DMA_EN |
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MT_WFDMA1_GLO_CFG_OMIT_TX_INFO |
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MT_WFDMA1_GLO_CFG_OMIT_RX_INFO |
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MT_WFDMA1_GLO_CFG_OMIT_RX_INFO_PFET2);
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}
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}
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static int mt7915_dma_enable(struct mt7915_dev *dev)
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{
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struct mt76_dev *mdev = &dev->mt76;
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u32 hif1_ofs = 0;
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u32 irq_mask;
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if (dev->hif2)
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hif1_ofs = MT_WFDMA0_PCIE1(0) - MT_WFDMA0(0);
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/* reset dma idx */
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mt76_wr(dev, MT_WFDMA0_RST_DTX_PTR, ~0);
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if (is_mt7915(mdev))
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mt76_wr(dev, MT_WFDMA1_RST_DTX_PTR, ~0);
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if (dev->hif2) {
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mt76_wr(dev, MT_WFDMA0_RST_DTX_PTR + hif1_ofs, ~0);
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if (is_mt7915(mdev))
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mt76_wr(dev, MT_WFDMA1_RST_DTX_PTR + hif1_ofs, ~0);
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}
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/* configure delay interrupt off */
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mt76_wr(dev, MT_WFDMA0_PRI_DLY_INT_CFG0, 0);
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if (is_mt7915(mdev)) {
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mt76_wr(dev, MT_WFDMA1_PRI_DLY_INT_CFG0, 0);
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} else {
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mt76_wr(dev, MT_WFDMA0_PRI_DLY_INT_CFG1, 0);
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mt76_wr(dev, MT_WFDMA0_PRI_DLY_INT_CFG2, 0);
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}
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if (dev->hif2) {
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mt76_wr(dev, MT_WFDMA0_PRI_DLY_INT_CFG0 + hif1_ofs, 0);
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if (is_mt7915(mdev)) {
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mt76_wr(dev, MT_WFDMA1_PRI_DLY_INT_CFG0 +
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hif1_ofs, 0);
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} else {
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mt76_wr(dev, MT_WFDMA0_PRI_DLY_INT_CFG1 +
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hif1_ofs, 0);
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mt76_wr(dev, MT_WFDMA0_PRI_DLY_INT_CFG2 +
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hif1_ofs, 0);
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}
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}
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/* configure perfetch settings */
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mt7915_dma_prefetch(dev);
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/* hif wait WFDMA idle */
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mt76_set(dev, MT_WFDMA0_BUSY_ENA,
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MT_WFDMA0_BUSY_ENA_TX_FIFO0 |
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MT_WFDMA0_BUSY_ENA_TX_FIFO1 |
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MT_WFDMA0_BUSY_ENA_RX_FIFO);
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if (is_mt7915(mdev))
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mt76_set(dev, MT_WFDMA1_BUSY_ENA,
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MT_WFDMA1_BUSY_ENA_TX_FIFO0 |
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MT_WFDMA1_BUSY_ENA_TX_FIFO1 |
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MT_WFDMA1_BUSY_ENA_RX_FIFO);
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if (dev->hif2) {
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mt76_set(dev, MT_WFDMA0_BUSY_ENA + hif1_ofs,
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MT_WFDMA0_PCIE1_BUSY_ENA_TX_FIFO0 |
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MT_WFDMA0_PCIE1_BUSY_ENA_TX_FIFO1 |
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MT_WFDMA0_PCIE1_BUSY_ENA_RX_FIFO);
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if (is_mt7915(mdev))
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mt76_set(dev, MT_WFDMA1_BUSY_ENA + hif1_ofs,
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MT_WFDMA1_PCIE1_BUSY_ENA_TX_FIFO0 |
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MT_WFDMA1_PCIE1_BUSY_ENA_TX_FIFO1 |
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MT_WFDMA1_PCIE1_BUSY_ENA_RX_FIFO);
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}
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mt76_poll(dev, MT_WFDMA_EXT_CSR_HIF_MISC,
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MT_WFDMA_EXT_CSR_HIF_MISC_BUSY, 0, 1000);
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/* set WFDMA Tx/Rx */
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mt76_set(dev, MT_WFDMA0_GLO_CFG,
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MT_WFDMA0_GLO_CFG_TX_DMA_EN |
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MT_WFDMA0_GLO_CFG_RX_DMA_EN |
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MT_WFDMA0_GLO_CFG_OMIT_TX_INFO |
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MT_WFDMA0_GLO_CFG_OMIT_RX_INFO_PFET2);
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if (is_mt7915(mdev))
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mt76_set(dev, MT_WFDMA1_GLO_CFG,
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MT_WFDMA1_GLO_CFG_TX_DMA_EN |
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MT_WFDMA1_GLO_CFG_RX_DMA_EN |
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MT_WFDMA1_GLO_CFG_OMIT_TX_INFO |
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MT_WFDMA1_GLO_CFG_OMIT_RX_INFO);
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if (dev->hif2) {
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mt76_set(dev, MT_WFDMA0_GLO_CFG + hif1_ofs,
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MT_WFDMA0_GLO_CFG_TX_DMA_EN |
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MT_WFDMA0_GLO_CFG_RX_DMA_EN |
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MT_WFDMA0_GLO_CFG_OMIT_TX_INFO |
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MT_WFDMA0_GLO_CFG_OMIT_RX_INFO_PFET2);
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if (is_mt7915(mdev))
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mt76_set(dev, MT_WFDMA1_GLO_CFG + hif1_ofs,
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MT_WFDMA1_GLO_CFG_TX_DMA_EN |
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MT_WFDMA1_GLO_CFG_RX_DMA_EN |
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MT_WFDMA1_GLO_CFG_OMIT_TX_INFO |
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MT_WFDMA1_GLO_CFG_OMIT_RX_INFO);
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mt76_set(dev, MT_WFDMA_HOST_CONFIG,
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MT_WFDMA_HOST_CONFIG_PDMA_BAND);
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}
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/* enable interrupts for TX/RX rings */
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irq_mask = MT_INT_RX_DONE_MCU |
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MT_INT_TX_DONE_MCU |
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MT_INT_MCU_CMD;
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if (!dev->phy.band_idx)
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irq_mask |= MT_INT_BAND0_RX_DONE;
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if (dev->dbdc_support || dev->phy.band_idx)
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irq_mask |= MT_INT_BAND1_RX_DONE;
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if (mtk_wed_device_active(&dev->mt76.mmio.wed)) {
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u32 wed_irq_mask = irq_mask;
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wed_irq_mask |= MT_INT_TX_DONE_BAND0 | MT_INT_TX_DONE_BAND1;
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mt76_wr(dev, MT_INT_WED_MASK_CSR, wed_irq_mask);
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mtk_wed_device_start(&dev->mt76.mmio.wed, wed_irq_mask);
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}
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mt7915_irq_enable(dev, irq_mask);
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return 0;
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}
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int mt7915_dma_init(struct mt7915_dev *dev, struct mt7915_phy *phy2)
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{
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struct mt76_dev *mdev = &dev->mt76;
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u32 wa_rx_base, wa_rx_idx;
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u32 hif1_ofs = 0;
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int ret;
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mt7915_dma_config(dev);
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mt76_dma_attach(&dev->mt76);
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if (dev->hif2)
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hif1_ofs = MT_WFDMA0_PCIE1(0) - MT_WFDMA0(0);
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mt7915_dma_disable(dev, true);
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if (mtk_wed_device_active(&dev->mt76.mmio.wed)) {
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mt76_set(dev, MT_WFDMA_HOST_CONFIG, MT_WFDMA_HOST_CONFIG_WED);
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mt76_wr(dev, MT_WFDMA_WED_RING_CONTROL,
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FIELD_PREP(MT_WFDMA_WED_RING_CONTROL_TX0, 18) |
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FIELD_PREP(MT_WFDMA_WED_RING_CONTROL_TX1, 19) |
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FIELD_PREP(MT_WFDMA_WED_RING_CONTROL_RX1, 1));
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} else {
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mt76_clear(dev, MT_WFDMA_HOST_CONFIG, MT_WFDMA_HOST_CONFIG_WED);
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}
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/* init tx queue */
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ret = mt7915_init_tx_queues(&dev->phy,
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MT_TXQ_ID(dev->phy.band_idx),
|
|
MT7915_TX_RING_SIZE,
|
|
MT_TXQ_RING_BASE(0));
|
|
if (ret)
|
|
return ret;
|
|
|
|
if (phy2) {
|
|
ret = mt7915_init_tx_queues(phy2,
|
|
MT_TXQ_ID(phy2->band_idx),
|
|
MT7915_TX_RING_SIZE,
|
|
MT_TXQ_RING_BASE(1));
|
|
if (ret)
|
|
return ret;
|
|
}
|
|
|
|
/* command to WM */
|
|
ret = mt76_init_mcu_queue(&dev->mt76, MT_MCUQ_WM,
|
|
MT_MCUQ_ID(MT_MCUQ_WM),
|
|
MT7915_TX_MCU_RING_SIZE,
|
|
MT_MCUQ_RING_BASE(MT_MCUQ_WM));
|
|
if (ret)
|
|
return ret;
|
|
|
|
/* command to WA */
|
|
ret = mt76_init_mcu_queue(&dev->mt76, MT_MCUQ_WA,
|
|
MT_MCUQ_ID(MT_MCUQ_WA),
|
|
MT7915_TX_MCU_RING_SIZE,
|
|
MT_MCUQ_RING_BASE(MT_MCUQ_WA));
|
|
if (ret)
|
|
return ret;
|
|
|
|
/* firmware download */
|
|
ret = mt76_init_mcu_queue(&dev->mt76, MT_MCUQ_FWDL,
|
|
MT_MCUQ_ID(MT_MCUQ_FWDL),
|
|
MT7915_TX_FWDL_RING_SIZE,
|
|
MT_MCUQ_RING_BASE(MT_MCUQ_FWDL));
|
|
if (ret)
|
|
return ret;
|
|
|
|
/* event from WM */
|
|
ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_MCU],
|
|
MT_RXQ_ID(MT_RXQ_MCU),
|
|
MT7915_RX_MCU_RING_SIZE,
|
|
MT_RX_BUF_SIZE,
|
|
MT_RXQ_RING_BASE(MT_RXQ_MCU));
|
|
if (ret)
|
|
return ret;
|
|
|
|
/* event from WA */
|
|
if (mtk_wed_device_active(&dev->mt76.mmio.wed)) {
|
|
wa_rx_base = MT_WED_RX_RING_BASE;
|
|
wa_rx_idx = MT7915_RXQ_MCU_WA;
|
|
dev->mt76.q_rx[MT_RXQ_MCU_WA].flags = MT_WED_Q_TXFREE;
|
|
} else {
|
|
wa_rx_base = MT_RXQ_RING_BASE(MT_RXQ_MCU_WA);
|
|
wa_rx_idx = MT_RXQ_ID(MT_RXQ_MCU_WA);
|
|
}
|
|
ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_MCU_WA],
|
|
wa_rx_idx, MT7915_RX_MCU_RING_SIZE,
|
|
MT_RX_BUF_SIZE, wa_rx_base);
|
|
if (ret)
|
|
return ret;
|
|
|
|
/* rx data queue for band0 */
|
|
if (!dev->phy.band_idx) {
|
|
ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_MAIN],
|
|
MT_RXQ_ID(MT_RXQ_MAIN),
|
|
MT7915_RX_RING_SIZE,
|
|
MT_RX_BUF_SIZE,
|
|
MT_RXQ_RING_BASE(MT_RXQ_MAIN));
|
|
if (ret)
|
|
return ret;
|
|
}
|
|
|
|
/* tx free notify event from WA for band0 */
|
|
if (!is_mt7915(mdev)) {
|
|
ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_MAIN_WA],
|
|
MT_RXQ_ID(MT_RXQ_MAIN_WA),
|
|
MT7915_RX_MCU_RING_SIZE,
|
|
MT_RX_BUF_SIZE,
|
|
MT_RXQ_RING_BASE(MT_RXQ_MAIN_WA));
|
|
if (ret)
|
|
return ret;
|
|
}
|
|
|
|
if (dev->dbdc_support || dev->phy.band_idx) {
|
|
/* rx data queue for band1 */
|
|
ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_BAND1],
|
|
MT_RXQ_ID(MT_RXQ_BAND1),
|
|
MT7915_RX_RING_SIZE,
|
|
MT_RX_BUF_SIZE,
|
|
MT_RXQ_RING_BASE(MT_RXQ_BAND1) + hif1_ofs);
|
|
if (ret)
|
|
return ret;
|
|
|
|
/* tx free notify event from WA for band1 */
|
|
ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_BAND1_WA],
|
|
MT_RXQ_ID(MT_RXQ_BAND1_WA),
|
|
MT7915_RX_MCU_RING_SIZE,
|
|
MT_RX_BUF_SIZE,
|
|
MT_RXQ_RING_BASE(MT_RXQ_BAND1_WA) + hif1_ofs);
|
|
if (ret)
|
|
return ret;
|
|
}
|
|
|
|
ret = mt76_init_queues(dev, mt76_dma_rx_poll);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
netif_napi_add_tx(&dev->mt76.tx_napi_dev, &dev->mt76.tx_napi,
|
|
mt7915_poll_tx);
|
|
napi_enable(&dev->mt76.tx_napi);
|
|
|
|
mt7915_dma_enable(dev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
void mt7915_dma_cleanup(struct mt7915_dev *dev)
|
|
{
|
|
mt7915_dma_disable(dev, true);
|
|
|
|
mt76_dma_cleanup(&dev->mt76);
|
|
}
|