599 lines
17 KiB
C
599 lines
17 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/* Microchip Sparx5 Switch driver
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*
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* Copyright (c) 2021 Microchip Technology Inc. and its subsidiaries.
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*
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* The Sparx5 Chip Register Model can be browsed at this location:
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* https://github.com/microchip-ung/sparx-5_reginfo
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*/
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#include <linux/types.h>
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#include <linux/skbuff.h>
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#include <linux/netdevice.h>
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#include <linux/interrupt.h>
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#include <linux/ip.h>
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#include <linux/dma-mapping.h>
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#include "sparx5_main_regs.h"
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#include "sparx5_main.h"
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#include "sparx5_port.h"
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#define FDMA_XTR_CHANNEL 6
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#define FDMA_INJ_CHANNEL 0
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#define FDMA_DCB_INFO_DATAL(x) ((x) & GENMASK(15, 0))
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#define FDMA_DCB_INFO_TOKEN BIT(17)
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#define FDMA_DCB_INFO_INTR BIT(18)
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#define FDMA_DCB_INFO_SW(x) (((x) << 24) & GENMASK(31, 24))
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#define FDMA_DCB_STATUS_BLOCKL(x) ((x) & GENMASK(15, 0))
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#define FDMA_DCB_STATUS_SOF BIT(16)
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#define FDMA_DCB_STATUS_EOF BIT(17)
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#define FDMA_DCB_STATUS_INTR BIT(18)
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#define FDMA_DCB_STATUS_DONE BIT(19)
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#define FDMA_DCB_STATUS_BLOCKO(x) (((x) << 20) & GENMASK(31, 20))
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#define FDMA_DCB_INVALID_DATA 0x1
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#define FDMA_XTR_BUFFER_SIZE 2048
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#define FDMA_WEIGHT 4
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/* Frame DMA DCB format
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*
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* +---------------------------+
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* | Next Ptr |
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* +---------------------------+
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* | Reserved | Info |
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* +---------------------------+
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* | Data0 Ptr |
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* +---------------------------+
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* | Reserved | Status0 |
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* +---------------------------+
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* | Data1 Ptr |
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* +---------------------------+
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* | Reserved | Status1 |
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* +---------------------------+
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* | Data2 Ptr |
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* +---------------------------+
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* | Reserved | Status2 |
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* |-------------|-------------|
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* | |
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* | |
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* | |
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* | |
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* | |
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* |---------------------------|
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* | Data14 Ptr |
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* +-------------|-------------+
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* | Reserved | Status14 |
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* +-------------|-------------+
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*/
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/* For each hardware DB there is an entry in this list and when the HW DB
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* entry is used, this SW DB entry is moved to the back of the list
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*/
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struct sparx5_db {
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struct list_head list;
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void *cpu_addr;
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};
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static void sparx5_fdma_rx_add_dcb(struct sparx5_rx *rx,
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struct sparx5_rx_dcb_hw *dcb,
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u64 nextptr)
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{
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int idx = 0;
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/* Reset the status of the DB */
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for (idx = 0; idx < FDMA_RX_DCB_MAX_DBS; ++idx) {
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struct sparx5_db_hw *db = &dcb->db[idx];
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db->status = FDMA_DCB_STATUS_INTR;
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}
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dcb->nextptr = FDMA_DCB_INVALID_DATA;
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dcb->info = FDMA_DCB_INFO_DATAL(FDMA_XTR_BUFFER_SIZE);
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rx->last_entry->nextptr = nextptr;
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rx->last_entry = dcb;
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}
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static void sparx5_fdma_tx_add_dcb(struct sparx5_tx *tx,
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struct sparx5_tx_dcb_hw *dcb,
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u64 nextptr)
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{
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int idx = 0;
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/* Reset the status of the DB */
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for (idx = 0; idx < FDMA_TX_DCB_MAX_DBS; ++idx) {
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struct sparx5_db_hw *db = &dcb->db[idx];
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db->status = FDMA_DCB_STATUS_DONE;
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}
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dcb->nextptr = FDMA_DCB_INVALID_DATA;
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dcb->info = FDMA_DCB_INFO_DATAL(FDMA_XTR_BUFFER_SIZE);
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}
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static void sparx5_fdma_rx_activate(struct sparx5 *sparx5, struct sparx5_rx *rx)
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{
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/* Write the buffer address in the LLP and LLP1 regs */
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spx5_wr(((u64)rx->dma) & GENMASK(31, 0), sparx5,
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FDMA_DCB_LLP(rx->channel_id));
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spx5_wr(((u64)rx->dma) >> 32, sparx5, FDMA_DCB_LLP1(rx->channel_id));
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/* Set the number of RX DBs to be used, and DB end-of-frame interrupt */
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spx5_wr(FDMA_CH_CFG_CH_DCB_DB_CNT_SET(FDMA_RX_DCB_MAX_DBS) |
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FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY_SET(1) |
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FDMA_CH_CFG_CH_INJ_PORT_SET(XTR_QUEUE),
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sparx5, FDMA_CH_CFG(rx->channel_id));
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/* Set the RX Watermark to max */
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spx5_rmw(FDMA_XTR_CFG_XTR_FIFO_WM_SET(31), FDMA_XTR_CFG_XTR_FIFO_WM,
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sparx5,
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FDMA_XTR_CFG);
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/* Start RX fdma */
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spx5_rmw(FDMA_PORT_CTRL_XTR_STOP_SET(0), FDMA_PORT_CTRL_XTR_STOP,
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sparx5, FDMA_PORT_CTRL(0));
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/* Enable RX channel DB interrupt */
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spx5_rmw(BIT(rx->channel_id),
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BIT(rx->channel_id) & FDMA_INTR_DB_ENA_INTR_DB_ENA,
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sparx5, FDMA_INTR_DB_ENA);
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/* Activate the RX channel */
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spx5_wr(BIT(rx->channel_id), sparx5, FDMA_CH_ACTIVATE);
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}
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static void sparx5_fdma_rx_deactivate(struct sparx5 *sparx5, struct sparx5_rx *rx)
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{
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/* Dectivate the RX channel */
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spx5_rmw(0, BIT(rx->channel_id) & FDMA_CH_ACTIVATE_CH_ACTIVATE,
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sparx5, FDMA_CH_ACTIVATE);
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/* Disable RX channel DB interrupt */
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spx5_rmw(0, BIT(rx->channel_id) & FDMA_INTR_DB_ENA_INTR_DB_ENA,
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sparx5, FDMA_INTR_DB_ENA);
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/* Stop RX fdma */
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spx5_rmw(FDMA_PORT_CTRL_XTR_STOP_SET(1), FDMA_PORT_CTRL_XTR_STOP,
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sparx5, FDMA_PORT_CTRL(0));
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}
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static void sparx5_fdma_tx_activate(struct sparx5 *sparx5, struct sparx5_tx *tx)
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{
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/* Write the buffer address in the LLP and LLP1 regs */
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spx5_wr(((u64)tx->dma) & GENMASK(31, 0), sparx5,
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FDMA_DCB_LLP(tx->channel_id));
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spx5_wr(((u64)tx->dma) >> 32, sparx5, FDMA_DCB_LLP1(tx->channel_id));
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/* Set the number of TX DBs to be used, and DB end-of-frame interrupt */
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spx5_wr(FDMA_CH_CFG_CH_DCB_DB_CNT_SET(FDMA_TX_DCB_MAX_DBS) |
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FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY_SET(1) |
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FDMA_CH_CFG_CH_INJ_PORT_SET(INJ_QUEUE),
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sparx5, FDMA_CH_CFG(tx->channel_id));
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/* Start TX fdma */
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spx5_rmw(FDMA_PORT_CTRL_INJ_STOP_SET(0), FDMA_PORT_CTRL_INJ_STOP,
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sparx5, FDMA_PORT_CTRL(0));
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/* Activate the channel */
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spx5_wr(BIT(tx->channel_id), sparx5, FDMA_CH_ACTIVATE);
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}
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static void sparx5_fdma_tx_deactivate(struct sparx5 *sparx5, struct sparx5_tx *tx)
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{
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/* Disable the channel */
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spx5_rmw(0, BIT(tx->channel_id) & FDMA_CH_ACTIVATE_CH_ACTIVATE,
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sparx5, FDMA_CH_ACTIVATE);
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}
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static void sparx5_fdma_rx_reload(struct sparx5 *sparx5, struct sparx5_rx *rx)
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{
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/* Reload the RX channel */
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spx5_wr(BIT(rx->channel_id), sparx5, FDMA_CH_RELOAD);
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}
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static void sparx5_fdma_tx_reload(struct sparx5 *sparx5, struct sparx5_tx *tx)
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{
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/* Reload the TX channel */
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spx5_wr(BIT(tx->channel_id), sparx5, FDMA_CH_RELOAD);
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}
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static struct sk_buff *sparx5_fdma_rx_alloc_skb(struct sparx5_rx *rx)
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{
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return __netdev_alloc_skb(rx->ndev, FDMA_XTR_BUFFER_SIZE,
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GFP_ATOMIC);
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}
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static bool sparx5_fdma_rx_get_frame(struct sparx5 *sparx5, struct sparx5_rx *rx)
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{
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struct sparx5_db_hw *db_hw;
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unsigned int packet_size;
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struct sparx5_port *port;
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struct sk_buff *new_skb;
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struct frame_info fi;
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struct sk_buff *skb;
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dma_addr_t dma_addr;
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/* Check if the DCB is done */
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db_hw = &rx->dcb_entries[rx->dcb_index].db[rx->db_index];
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if (unlikely(!(db_hw->status & FDMA_DCB_STATUS_DONE)))
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return false;
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skb = rx->skb[rx->dcb_index][rx->db_index];
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/* Replace the DB entry with a new SKB */
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new_skb = sparx5_fdma_rx_alloc_skb(rx);
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if (unlikely(!new_skb))
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return false;
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/* Map the new skb data and set the new skb */
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dma_addr = virt_to_phys(new_skb->data);
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rx->skb[rx->dcb_index][rx->db_index] = new_skb;
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db_hw->dataptr = dma_addr;
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packet_size = FDMA_DCB_STATUS_BLOCKL(db_hw->status);
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skb_put(skb, packet_size);
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/* Now do the normal processing of the skb */
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sparx5_ifh_parse((u32 *)skb->data, &fi);
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/* Map to port netdev */
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port = fi.src_port < SPX5_PORTS ? sparx5->ports[fi.src_port] : NULL;
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if (!port || !port->ndev) {
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dev_err(sparx5->dev, "Data on inactive port %d\n", fi.src_port);
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sparx5_xtr_flush(sparx5, XTR_QUEUE);
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return false;
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}
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skb->dev = port->ndev;
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skb_pull(skb, IFH_LEN * sizeof(u32));
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if (likely(!(skb->dev->features & NETIF_F_RXFCS)))
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skb_trim(skb, skb->len - ETH_FCS_LEN);
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sparx5_ptp_rxtstamp(sparx5, skb, fi.timestamp);
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skb->protocol = eth_type_trans(skb, skb->dev);
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/* Everything we see on an interface that is in the HW bridge
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* has already been forwarded
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*/
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if (test_bit(port->portno, sparx5->bridge_mask))
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skb->offload_fwd_mark = 1;
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skb->dev->stats.rx_bytes += skb->len;
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skb->dev->stats.rx_packets++;
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rx->packets++;
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netif_receive_skb(skb);
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return true;
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}
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static int sparx5_fdma_napi_callback(struct napi_struct *napi, int weight)
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{
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struct sparx5_rx *rx = container_of(napi, struct sparx5_rx, napi);
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struct sparx5 *sparx5 = container_of(rx, struct sparx5, rx);
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int counter = 0;
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while (counter < weight && sparx5_fdma_rx_get_frame(sparx5, rx)) {
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struct sparx5_rx_dcb_hw *old_dcb;
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rx->db_index++;
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counter++;
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/* Check if the DCB can be reused */
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if (rx->db_index != FDMA_RX_DCB_MAX_DBS)
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continue;
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/* As the DCB can be reused, just advance the dcb_index
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* pointer and set the nextptr in the DCB
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*/
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rx->db_index = 0;
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old_dcb = &rx->dcb_entries[rx->dcb_index];
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rx->dcb_index++;
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rx->dcb_index &= FDMA_DCB_MAX - 1;
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sparx5_fdma_rx_add_dcb(rx, old_dcb,
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rx->dma +
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((unsigned long)old_dcb -
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(unsigned long)rx->dcb_entries));
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}
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if (counter < weight) {
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napi_complete_done(&rx->napi, counter);
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spx5_rmw(BIT(rx->channel_id),
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BIT(rx->channel_id) & FDMA_INTR_DB_ENA_INTR_DB_ENA,
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sparx5, FDMA_INTR_DB_ENA);
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}
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if (counter)
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sparx5_fdma_rx_reload(sparx5, rx);
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return counter;
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}
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static struct sparx5_tx_dcb_hw *sparx5_fdma_next_dcb(struct sparx5_tx *tx,
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struct sparx5_tx_dcb_hw *dcb)
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{
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struct sparx5_tx_dcb_hw *next_dcb;
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next_dcb = dcb;
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next_dcb++;
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/* Handle wrap-around */
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if ((unsigned long)next_dcb >=
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((unsigned long)tx->first_entry + FDMA_DCB_MAX * sizeof(*dcb)))
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next_dcb = tx->first_entry;
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return next_dcb;
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}
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int sparx5_fdma_xmit(struct sparx5 *sparx5, u32 *ifh, struct sk_buff *skb)
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{
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struct sparx5_tx_dcb_hw *next_dcb_hw;
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struct sparx5_tx *tx = &sparx5->tx;
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static bool first_time = true;
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struct sparx5_db_hw *db_hw;
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struct sparx5_db *db;
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next_dcb_hw = sparx5_fdma_next_dcb(tx, tx->curr_entry);
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db_hw = &next_dcb_hw->db[0];
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if (!(db_hw->status & FDMA_DCB_STATUS_DONE))
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return -EINVAL;
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db = list_first_entry(&tx->db_list, struct sparx5_db, list);
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list_move_tail(&db->list, &tx->db_list);
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next_dcb_hw->nextptr = FDMA_DCB_INVALID_DATA;
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tx->curr_entry->nextptr = tx->dma +
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((unsigned long)next_dcb_hw -
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(unsigned long)tx->first_entry);
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tx->curr_entry = next_dcb_hw;
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memset(db->cpu_addr, 0, FDMA_XTR_BUFFER_SIZE);
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memcpy(db->cpu_addr, ifh, IFH_LEN * 4);
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memcpy(db->cpu_addr + IFH_LEN * 4, skb->data, skb->len);
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db_hw->status = FDMA_DCB_STATUS_SOF |
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FDMA_DCB_STATUS_EOF |
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FDMA_DCB_STATUS_BLOCKO(0) |
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FDMA_DCB_STATUS_BLOCKL(skb->len + IFH_LEN * 4 + 4);
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if (first_time) {
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sparx5_fdma_tx_activate(sparx5, tx);
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first_time = false;
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} else {
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sparx5_fdma_tx_reload(sparx5, tx);
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}
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return NETDEV_TX_OK;
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}
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static int sparx5_fdma_rx_alloc(struct sparx5 *sparx5)
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{
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struct sparx5_rx *rx = &sparx5->rx;
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struct sparx5_rx_dcb_hw *dcb;
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int idx, jdx;
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int size;
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size = sizeof(struct sparx5_rx_dcb_hw) * FDMA_DCB_MAX;
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size = ALIGN(size, PAGE_SIZE);
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rx->dcb_entries = devm_kzalloc(sparx5->dev, size, GFP_KERNEL);
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if (!rx->dcb_entries)
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return -ENOMEM;
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rx->dma = virt_to_phys(rx->dcb_entries);
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rx->last_entry = rx->dcb_entries;
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rx->db_index = 0;
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rx->dcb_index = 0;
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/* Now for each dcb allocate the db */
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for (idx = 0; idx < FDMA_DCB_MAX; ++idx) {
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dcb = &rx->dcb_entries[idx];
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dcb->info = 0;
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/* For each db allocate an skb and map skb data pointer to the DB
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* dataptr. In this way when the frame is received the skb->data
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* will contain the frame, so no memcpy is needed
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*/
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for (jdx = 0; jdx < FDMA_RX_DCB_MAX_DBS; ++jdx) {
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struct sparx5_db_hw *db_hw = &dcb->db[jdx];
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dma_addr_t dma_addr;
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struct sk_buff *skb;
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skb = sparx5_fdma_rx_alloc_skb(rx);
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if (!skb)
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return -ENOMEM;
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dma_addr = virt_to_phys(skb->data);
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db_hw->dataptr = dma_addr;
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db_hw->status = 0;
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rx->skb[idx][jdx] = skb;
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}
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sparx5_fdma_rx_add_dcb(rx, dcb, rx->dma + sizeof(*dcb) * idx);
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}
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netif_napi_add_weight(rx->ndev, &rx->napi, sparx5_fdma_napi_callback,
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FDMA_WEIGHT);
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napi_enable(&rx->napi);
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sparx5_fdma_rx_activate(sparx5, rx);
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return 0;
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}
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static int sparx5_fdma_tx_alloc(struct sparx5 *sparx5)
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{
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struct sparx5_tx *tx = &sparx5->tx;
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struct sparx5_tx_dcb_hw *dcb;
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int idx, jdx;
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int size;
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size = sizeof(struct sparx5_tx_dcb_hw) * FDMA_DCB_MAX;
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size = ALIGN(size, PAGE_SIZE);
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tx->curr_entry = devm_kzalloc(sparx5->dev, size, GFP_KERNEL);
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if (!tx->curr_entry)
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return -ENOMEM;
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tx->dma = virt_to_phys(tx->curr_entry);
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tx->first_entry = tx->curr_entry;
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INIT_LIST_HEAD(&tx->db_list);
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/* Now for each dcb allocate the db */
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for (idx = 0; idx < FDMA_DCB_MAX; ++idx) {
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dcb = &tx->curr_entry[idx];
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dcb->info = 0;
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/* TX databuffers must be 16byte aligned */
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for (jdx = 0; jdx < FDMA_TX_DCB_MAX_DBS; ++jdx) {
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struct sparx5_db_hw *db_hw = &dcb->db[jdx];
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struct sparx5_db *db;
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dma_addr_t phys;
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void *cpu_addr;
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cpu_addr = devm_kzalloc(sparx5->dev,
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FDMA_XTR_BUFFER_SIZE,
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GFP_KERNEL);
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if (!cpu_addr)
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return -ENOMEM;
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phys = virt_to_phys(cpu_addr);
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db_hw->dataptr = phys;
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db_hw->status = 0;
|
|
db = devm_kzalloc(sparx5->dev, sizeof(*db), GFP_KERNEL);
|
|
if (!db)
|
|
return -ENOMEM;
|
|
db->cpu_addr = cpu_addr;
|
|
list_add_tail(&db->list, &tx->db_list);
|
|
}
|
|
sparx5_fdma_tx_add_dcb(tx, dcb, tx->dma + sizeof(*dcb) * idx);
|
|
/* Let the curr_entry to point to the last allocated entry */
|
|
if (idx == FDMA_DCB_MAX - 1)
|
|
tx->curr_entry = dcb;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
static void sparx5_fdma_rx_init(struct sparx5 *sparx5,
|
|
struct sparx5_rx *rx, int channel)
|
|
{
|
|
int idx;
|
|
|
|
rx->channel_id = channel;
|
|
/* Fetch a netdev for SKB and NAPI use, any will do */
|
|
for (idx = 0; idx < SPX5_PORTS; ++idx) {
|
|
struct sparx5_port *port = sparx5->ports[idx];
|
|
|
|
if (port && port->ndev) {
|
|
rx->ndev = port->ndev;
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
|
|
static void sparx5_fdma_tx_init(struct sparx5 *sparx5,
|
|
struct sparx5_tx *tx, int channel)
|
|
{
|
|
tx->channel_id = channel;
|
|
}
|
|
|
|
irqreturn_t sparx5_fdma_handler(int irq, void *args)
|
|
{
|
|
struct sparx5 *sparx5 = args;
|
|
u32 db = 0, err = 0;
|
|
|
|
db = spx5_rd(sparx5, FDMA_INTR_DB);
|
|
err = spx5_rd(sparx5, FDMA_INTR_ERR);
|
|
/* Clear interrupt */
|
|
if (db) {
|
|
spx5_wr(0, sparx5, FDMA_INTR_DB_ENA);
|
|
spx5_wr(db, sparx5, FDMA_INTR_DB);
|
|
napi_schedule(&sparx5->rx.napi);
|
|
}
|
|
if (err) {
|
|
u32 err_type = spx5_rd(sparx5, FDMA_ERRORS);
|
|
|
|
dev_err_ratelimited(sparx5->dev,
|
|
"ERR: int: %#x, type: %#x\n",
|
|
err, err_type);
|
|
spx5_wr(err, sparx5, FDMA_INTR_ERR);
|
|
spx5_wr(err_type, sparx5, FDMA_ERRORS);
|
|
}
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
static void sparx5_fdma_injection_mode(struct sparx5 *sparx5)
|
|
{
|
|
const int byte_swap = 1;
|
|
int portno;
|
|
int urgency;
|
|
|
|
/* Change mode to fdma extraction and injection */
|
|
spx5_wr(QS_XTR_GRP_CFG_MODE_SET(2) |
|
|
QS_XTR_GRP_CFG_STATUS_WORD_POS_SET(1) |
|
|
QS_XTR_GRP_CFG_BYTE_SWAP_SET(byte_swap),
|
|
sparx5, QS_XTR_GRP_CFG(XTR_QUEUE));
|
|
spx5_wr(QS_INJ_GRP_CFG_MODE_SET(2) |
|
|
QS_INJ_GRP_CFG_BYTE_SWAP_SET(byte_swap),
|
|
sparx5, QS_INJ_GRP_CFG(INJ_QUEUE));
|
|
|
|
/* CPU ports capture setup */
|
|
for (portno = SPX5_PORT_CPU_0; portno <= SPX5_PORT_CPU_1; portno++) {
|
|
/* ASM CPU port: No preamble, IFH, enable padding */
|
|
spx5_wr(ASM_PORT_CFG_PAD_ENA_SET(1) |
|
|
ASM_PORT_CFG_NO_PREAMBLE_ENA_SET(1) |
|
|
ASM_PORT_CFG_INJ_FORMAT_CFG_SET(1), /* 1 = IFH */
|
|
sparx5, ASM_PORT_CFG(portno));
|
|
|
|
/* Reset WM cnt to unclog queued frames */
|
|
spx5_rmw(DSM_DEV_TX_STOP_WM_CFG_DEV_TX_CNT_CLR_SET(1),
|
|
DSM_DEV_TX_STOP_WM_CFG_DEV_TX_CNT_CLR,
|
|
sparx5,
|
|
DSM_DEV_TX_STOP_WM_CFG(portno));
|
|
|
|
/* Set Disassembler Stop Watermark level */
|
|
spx5_rmw(DSM_DEV_TX_STOP_WM_CFG_DEV_TX_STOP_WM_SET(100),
|
|
DSM_DEV_TX_STOP_WM_CFG_DEV_TX_STOP_WM,
|
|
sparx5,
|
|
DSM_DEV_TX_STOP_WM_CFG(portno));
|
|
|
|
/* Enable port in queue system */
|
|
urgency = sparx5_port_fwd_urg(sparx5, SPEED_2500);
|
|
spx5_rmw(QFWD_SWITCH_PORT_MODE_PORT_ENA_SET(1) |
|
|
QFWD_SWITCH_PORT_MODE_FWD_URGENCY_SET(urgency),
|
|
QFWD_SWITCH_PORT_MODE_PORT_ENA |
|
|
QFWD_SWITCH_PORT_MODE_FWD_URGENCY,
|
|
sparx5,
|
|
QFWD_SWITCH_PORT_MODE(portno));
|
|
|
|
/* Disable Disassembler buffer underrun watchdog
|
|
* to avoid truncated packets in XTR
|
|
*/
|
|
spx5_rmw(DSM_BUF_CFG_UNDERFLOW_WATCHDOG_DIS_SET(1),
|
|
DSM_BUF_CFG_UNDERFLOW_WATCHDOG_DIS,
|
|
sparx5,
|
|
DSM_BUF_CFG(portno));
|
|
|
|
/* Disabling frame aging */
|
|
spx5_rmw(HSCH_PORT_MODE_AGE_DIS_SET(1),
|
|
HSCH_PORT_MODE_AGE_DIS,
|
|
sparx5,
|
|
HSCH_PORT_MODE(portno));
|
|
}
|
|
}
|
|
|
|
int sparx5_fdma_start(struct sparx5 *sparx5)
|
|
{
|
|
int err;
|
|
|
|
/* Reset FDMA state */
|
|
spx5_wr(FDMA_CTRL_NRESET_SET(0), sparx5, FDMA_CTRL);
|
|
spx5_wr(FDMA_CTRL_NRESET_SET(1), sparx5, FDMA_CTRL);
|
|
|
|
/* Force ACP caching but disable read/write allocation */
|
|
spx5_rmw(CPU_PROC_CTRL_ACP_CACHE_FORCE_ENA_SET(1) |
|
|
CPU_PROC_CTRL_ACP_AWCACHE_SET(0) |
|
|
CPU_PROC_CTRL_ACP_ARCACHE_SET(0),
|
|
CPU_PROC_CTRL_ACP_CACHE_FORCE_ENA |
|
|
CPU_PROC_CTRL_ACP_AWCACHE |
|
|
CPU_PROC_CTRL_ACP_ARCACHE,
|
|
sparx5, CPU_PROC_CTRL);
|
|
|
|
sparx5_fdma_injection_mode(sparx5);
|
|
sparx5_fdma_rx_init(sparx5, &sparx5->rx, FDMA_XTR_CHANNEL);
|
|
sparx5_fdma_tx_init(sparx5, &sparx5->tx, FDMA_INJ_CHANNEL);
|
|
err = sparx5_fdma_rx_alloc(sparx5);
|
|
if (err) {
|
|
dev_err(sparx5->dev, "Could not allocate RX buffers: %d\n", err);
|
|
return err;
|
|
}
|
|
err = sparx5_fdma_tx_alloc(sparx5);
|
|
if (err) {
|
|
dev_err(sparx5->dev, "Could not allocate TX buffers: %d\n", err);
|
|
return err;
|
|
}
|
|
return err;
|
|
}
|
|
|
|
static u32 sparx5_fdma_port_ctrl(struct sparx5 *sparx5)
|
|
{
|
|
return spx5_rd(sparx5, FDMA_PORT_CTRL(0));
|
|
}
|
|
|
|
int sparx5_fdma_stop(struct sparx5 *sparx5)
|
|
{
|
|
u32 val;
|
|
|
|
napi_disable(&sparx5->rx.napi);
|
|
/* Stop the fdma and channel interrupts */
|
|
sparx5_fdma_rx_deactivate(sparx5, &sparx5->rx);
|
|
sparx5_fdma_tx_deactivate(sparx5, &sparx5->tx);
|
|
/* Wait for the RX channel to stop */
|
|
read_poll_timeout(sparx5_fdma_port_ctrl, val,
|
|
FDMA_PORT_CTRL_XTR_BUF_IS_EMPTY_GET(val) == 0,
|
|
500, 10000, 0, sparx5);
|
|
return 0;
|
|
}
|