645 lines
17 KiB
C
645 lines
17 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
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* 2002-2006 Thomas Gleixner (tglx@linutronix.de)
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*
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* Credits:
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* David Woodhouse for adding multichip support
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*
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* Aleph One Ltd. and Toby Churchill Ltd. for supporting the
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* rework for 2K page size chips
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*
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* This file contains all legacy helpers/code that should be removed
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* at some point.
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*/
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/nmi.h>
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#include "internals.h"
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/**
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* nand_read_byte - [DEFAULT] read one byte from the chip
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* @chip: NAND chip object
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*
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* Default read function for 8bit buswidth
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*/
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static uint8_t nand_read_byte(struct nand_chip *chip)
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{
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return readb(chip->legacy.IO_ADDR_R);
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}
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/**
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* nand_read_byte16 - [DEFAULT] read one byte endianness aware from the chip
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* @chip: NAND chip object
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*
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* Default read function for 16bit buswidth with endianness conversion.
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*
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*/
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static uint8_t nand_read_byte16(struct nand_chip *chip)
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{
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return (uint8_t) cpu_to_le16(readw(chip->legacy.IO_ADDR_R));
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}
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/**
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* nand_select_chip - [DEFAULT] control CE line
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* @chip: NAND chip object
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* @chipnr: chipnumber to select, -1 for deselect
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*
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* Default select function for 1 chip devices.
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*/
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static void nand_select_chip(struct nand_chip *chip, int chipnr)
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{
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switch (chipnr) {
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case -1:
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chip->legacy.cmd_ctrl(chip, NAND_CMD_NONE,
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0 | NAND_CTRL_CHANGE);
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break;
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case 0:
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break;
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default:
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BUG();
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}
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}
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/**
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* nand_write_byte - [DEFAULT] write single byte to chip
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* @chip: NAND chip object
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* @byte: value to write
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*
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* Default function to write a byte to I/O[7:0]
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*/
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static void nand_write_byte(struct nand_chip *chip, uint8_t byte)
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{
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chip->legacy.write_buf(chip, &byte, 1);
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}
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/**
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* nand_write_byte16 - [DEFAULT] write single byte to a chip with width 16
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* @chip: NAND chip object
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* @byte: value to write
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*
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* Default function to write a byte to I/O[7:0] on a 16-bit wide chip.
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*/
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static void nand_write_byte16(struct nand_chip *chip, uint8_t byte)
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{
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uint16_t word = byte;
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/*
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* It's not entirely clear what should happen to I/O[15:8] when writing
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* a byte. The ONFi spec (Revision 3.1; 2012-09-19, Section 2.16) reads:
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*
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* When the host supports a 16-bit bus width, only data is
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* transferred at the 16-bit width. All address and command line
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* transfers shall use only the lower 8-bits of the data bus. During
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* command transfers, the host may place any value on the upper
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* 8-bits of the data bus. During address transfers, the host shall
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* set the upper 8-bits of the data bus to 00h.
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*
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* One user of the write_byte callback is nand_set_features. The
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* four parameters are specified to be written to I/O[7:0], but this is
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* neither an address nor a command transfer. Let's assume a 0 on the
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* upper I/O lines is OK.
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*/
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chip->legacy.write_buf(chip, (uint8_t *)&word, 2);
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}
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/**
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* nand_write_buf - [DEFAULT] write buffer to chip
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* @chip: NAND chip object
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* @buf: data buffer
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* @len: number of bytes to write
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*
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* Default write function for 8bit buswidth.
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*/
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static void nand_write_buf(struct nand_chip *chip, const uint8_t *buf, int len)
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{
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iowrite8_rep(chip->legacy.IO_ADDR_W, buf, len);
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}
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/**
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* nand_read_buf - [DEFAULT] read chip data into buffer
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* @chip: NAND chip object
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* @buf: buffer to store date
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* @len: number of bytes to read
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*
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* Default read function for 8bit buswidth.
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*/
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static void nand_read_buf(struct nand_chip *chip, uint8_t *buf, int len)
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{
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ioread8_rep(chip->legacy.IO_ADDR_R, buf, len);
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}
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/**
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* nand_write_buf16 - [DEFAULT] write buffer to chip
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* @chip: NAND chip object
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* @buf: data buffer
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* @len: number of bytes to write
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*
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* Default write function for 16bit buswidth.
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*/
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static void nand_write_buf16(struct nand_chip *chip, const uint8_t *buf,
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int len)
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{
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u16 *p = (u16 *) buf;
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iowrite16_rep(chip->legacy.IO_ADDR_W, p, len >> 1);
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}
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/**
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* nand_read_buf16 - [DEFAULT] read chip data into buffer
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* @chip: NAND chip object
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* @buf: buffer to store date
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* @len: number of bytes to read
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*
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* Default read function for 16bit buswidth.
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*/
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static void nand_read_buf16(struct nand_chip *chip, uint8_t *buf, int len)
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{
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u16 *p = (u16 *) buf;
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ioread16_rep(chip->legacy.IO_ADDR_R, p, len >> 1);
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}
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/**
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* panic_nand_wait_ready - [GENERIC] Wait for the ready pin after commands.
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* @chip: NAND chip object
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* @timeo: Timeout
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*
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* Helper function for nand_wait_ready used when needing to wait in interrupt
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* context.
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*/
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static void panic_nand_wait_ready(struct nand_chip *chip, unsigned long timeo)
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{
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int i;
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/* Wait for the device to get ready */
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for (i = 0; i < timeo; i++) {
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if (chip->legacy.dev_ready(chip))
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break;
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touch_softlockup_watchdog();
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mdelay(1);
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}
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}
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/**
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* nand_wait_ready - [GENERIC] Wait for the ready pin after commands.
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* @chip: NAND chip object
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*
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* Wait for the ready pin after a command, and warn if a timeout occurs.
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*/
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void nand_wait_ready(struct nand_chip *chip)
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{
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struct mtd_info *mtd = nand_to_mtd(chip);
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unsigned long timeo = 400;
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if (mtd->oops_panic_write)
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return panic_nand_wait_ready(chip, timeo);
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/* Wait until command is processed or timeout occurs */
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timeo = jiffies + msecs_to_jiffies(timeo);
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do {
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if (chip->legacy.dev_ready(chip))
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return;
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cond_resched();
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} while (time_before(jiffies, timeo));
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if (!chip->legacy.dev_ready(chip))
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pr_warn_ratelimited("timeout while waiting for chip to become ready\n");
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}
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EXPORT_SYMBOL_GPL(nand_wait_ready);
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/**
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* nand_wait_status_ready - [GENERIC] Wait for the ready status after commands.
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* @chip: NAND chip object
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* @timeo: Timeout in ms
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*
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* Wait for status ready (i.e. command done) or timeout.
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*/
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static void nand_wait_status_ready(struct nand_chip *chip, unsigned long timeo)
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{
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int ret;
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timeo = jiffies + msecs_to_jiffies(timeo);
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do {
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u8 status;
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ret = nand_read_data_op(chip, &status, sizeof(status), true,
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false);
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if (ret)
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return;
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if (status & NAND_STATUS_READY)
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break;
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touch_softlockup_watchdog();
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} while (time_before(jiffies, timeo));
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};
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/**
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* nand_command - [DEFAULT] Send command to NAND device
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* @chip: NAND chip object
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* @command: the command to be sent
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* @column: the column address for this command, -1 if none
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* @page_addr: the page address for this command, -1 if none
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*
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* Send command to NAND device. This function is used for small page devices
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* (512 Bytes per page).
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*/
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static void nand_command(struct nand_chip *chip, unsigned int command,
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int column, int page_addr)
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{
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struct mtd_info *mtd = nand_to_mtd(chip);
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int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE;
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/* Write out the command to the device */
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if (command == NAND_CMD_SEQIN) {
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int readcmd;
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if (column >= mtd->writesize) {
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/* OOB area */
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column -= mtd->writesize;
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readcmd = NAND_CMD_READOOB;
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} else if (column < 256) {
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/* First 256 bytes --> READ0 */
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readcmd = NAND_CMD_READ0;
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} else {
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column -= 256;
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readcmd = NAND_CMD_READ1;
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}
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chip->legacy.cmd_ctrl(chip, readcmd, ctrl);
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ctrl &= ~NAND_CTRL_CHANGE;
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}
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if (command != NAND_CMD_NONE)
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chip->legacy.cmd_ctrl(chip, command, ctrl);
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/* Address cycle, when necessary */
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ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE;
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/* Serially input address */
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if (column != -1) {
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/* Adjust columns for 16 bit buswidth */
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if (chip->options & NAND_BUSWIDTH_16 &&
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!nand_opcode_8bits(command))
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column >>= 1;
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chip->legacy.cmd_ctrl(chip, column, ctrl);
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ctrl &= ~NAND_CTRL_CHANGE;
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}
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if (page_addr != -1) {
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chip->legacy.cmd_ctrl(chip, page_addr, ctrl);
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ctrl &= ~NAND_CTRL_CHANGE;
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chip->legacy.cmd_ctrl(chip, page_addr >> 8, ctrl);
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if (chip->options & NAND_ROW_ADDR_3)
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chip->legacy.cmd_ctrl(chip, page_addr >> 16, ctrl);
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}
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chip->legacy.cmd_ctrl(chip, NAND_CMD_NONE,
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NAND_NCE | NAND_CTRL_CHANGE);
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/*
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* Program and erase have their own busy handlers status and sequential
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* in needs no delay
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*/
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switch (command) {
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case NAND_CMD_NONE:
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case NAND_CMD_PAGEPROG:
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case NAND_CMD_ERASE1:
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case NAND_CMD_ERASE2:
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case NAND_CMD_SEQIN:
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case NAND_CMD_STATUS:
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case NAND_CMD_READID:
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case NAND_CMD_SET_FEATURES:
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return;
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case NAND_CMD_RESET:
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if (chip->legacy.dev_ready)
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break;
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udelay(chip->legacy.chip_delay);
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chip->legacy.cmd_ctrl(chip, NAND_CMD_STATUS,
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NAND_CTRL_CLE | NAND_CTRL_CHANGE);
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chip->legacy.cmd_ctrl(chip, NAND_CMD_NONE,
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NAND_NCE | NAND_CTRL_CHANGE);
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/* EZ-NAND can take upto 250ms as per ONFi v4.0 */
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nand_wait_status_ready(chip, 250);
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return;
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/* This applies to read commands */
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case NAND_CMD_READ0:
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/*
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* READ0 is sometimes used to exit GET STATUS mode. When this
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* is the case no address cycles are requested, and we can use
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* this information to detect that we should not wait for the
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* device to be ready.
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*/
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if (column == -1 && page_addr == -1)
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return;
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fallthrough;
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default:
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/*
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* If we don't have access to the busy pin, we apply the given
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* command delay
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*/
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if (!chip->legacy.dev_ready) {
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udelay(chip->legacy.chip_delay);
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return;
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}
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}
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/*
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* Apply this short delay always to ensure that we do wait tWB in
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* any case on any machine.
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*/
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ndelay(100);
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nand_wait_ready(chip);
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}
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static void nand_ccs_delay(struct nand_chip *chip)
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{
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const struct nand_sdr_timings *sdr =
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nand_get_sdr_timings(nand_get_interface_config(chip));
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/*
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* The controller already takes care of waiting for tCCS when the RNDIN
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* or RNDOUT command is sent, return directly.
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*/
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if (!(chip->options & NAND_WAIT_TCCS))
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return;
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/*
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* Wait tCCS_min if it is correctly defined, otherwise wait 500ns
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* (which should be safe for all NANDs).
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*/
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if (!IS_ERR(sdr) && nand_controller_can_setup_interface(chip))
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ndelay(sdr->tCCS_min / 1000);
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else
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ndelay(500);
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}
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/**
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* nand_command_lp - [DEFAULT] Send command to NAND large page device
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* @chip: NAND chip object
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* @command: the command to be sent
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* @column: the column address for this command, -1 if none
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* @page_addr: the page address for this command, -1 if none
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*
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* Send command to NAND device. This is the version for the new large page
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* devices. We don't have the separate regions as we have in the small page
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* devices. We must emulate NAND_CMD_READOOB to keep the code compatible.
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*/
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static void nand_command_lp(struct nand_chip *chip, unsigned int command,
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int column, int page_addr)
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{
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struct mtd_info *mtd = nand_to_mtd(chip);
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/* Emulate NAND_CMD_READOOB */
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if (command == NAND_CMD_READOOB) {
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column += mtd->writesize;
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command = NAND_CMD_READ0;
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}
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/* Command latch cycle */
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if (command != NAND_CMD_NONE)
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chip->legacy.cmd_ctrl(chip, command,
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NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
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if (column != -1 || page_addr != -1) {
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int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE;
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/* Serially input address */
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if (column != -1) {
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/* Adjust columns for 16 bit buswidth */
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if (chip->options & NAND_BUSWIDTH_16 &&
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!nand_opcode_8bits(command))
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column >>= 1;
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chip->legacy.cmd_ctrl(chip, column, ctrl);
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ctrl &= ~NAND_CTRL_CHANGE;
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/* Only output a single addr cycle for 8bits opcodes. */
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if (!nand_opcode_8bits(command))
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chip->legacy.cmd_ctrl(chip, column >> 8, ctrl);
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}
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if (page_addr != -1) {
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chip->legacy.cmd_ctrl(chip, page_addr, ctrl);
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chip->legacy.cmd_ctrl(chip, page_addr >> 8,
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NAND_NCE | NAND_ALE);
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if (chip->options & NAND_ROW_ADDR_3)
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chip->legacy.cmd_ctrl(chip, page_addr >> 16,
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NAND_NCE | NAND_ALE);
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}
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}
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chip->legacy.cmd_ctrl(chip, NAND_CMD_NONE,
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NAND_NCE | NAND_CTRL_CHANGE);
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/*
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* Program and erase have their own busy handlers status, sequential
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* in and status need no delay.
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*/
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switch (command) {
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case NAND_CMD_NONE:
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case NAND_CMD_CACHEDPROG:
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case NAND_CMD_PAGEPROG:
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case NAND_CMD_ERASE1:
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case NAND_CMD_ERASE2:
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case NAND_CMD_SEQIN:
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case NAND_CMD_STATUS:
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case NAND_CMD_READID:
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case NAND_CMD_SET_FEATURES:
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return;
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case NAND_CMD_RNDIN:
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nand_ccs_delay(chip);
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return;
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case NAND_CMD_RESET:
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if (chip->legacy.dev_ready)
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break;
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udelay(chip->legacy.chip_delay);
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chip->legacy.cmd_ctrl(chip, NAND_CMD_STATUS,
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NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
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chip->legacy.cmd_ctrl(chip, NAND_CMD_NONE,
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NAND_NCE | NAND_CTRL_CHANGE);
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/* EZ-NAND can take upto 250ms as per ONFi v4.0 */
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nand_wait_status_ready(chip, 250);
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return;
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case NAND_CMD_RNDOUT:
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/* No ready / busy check necessary */
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chip->legacy.cmd_ctrl(chip, NAND_CMD_RNDOUTSTART,
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NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
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chip->legacy.cmd_ctrl(chip, NAND_CMD_NONE,
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NAND_NCE | NAND_CTRL_CHANGE);
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nand_ccs_delay(chip);
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return;
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case NAND_CMD_READ0:
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/*
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* READ0 is sometimes used to exit GET STATUS mode. When this
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* is the case no address cycles are requested, and we can use
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* this information to detect that READSTART should not be
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* issued.
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*/
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if (column == -1 && page_addr == -1)
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return;
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chip->legacy.cmd_ctrl(chip, NAND_CMD_READSTART,
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NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
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chip->legacy.cmd_ctrl(chip, NAND_CMD_NONE,
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NAND_NCE | NAND_CTRL_CHANGE);
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fallthrough; /* This applies to read commands */
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default:
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/*
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* If we don't have access to the busy pin, we apply the given
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* command delay.
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*/
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if (!chip->legacy.dev_ready) {
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udelay(chip->legacy.chip_delay);
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return;
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}
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}
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/*
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* Apply this short delay always to ensure that we do wait tWB in
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* any case on any machine.
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*/
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ndelay(100);
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nand_wait_ready(chip);
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}
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|
/**
|
|
* nand_get_set_features_notsupp - set/get features stub returning -ENOTSUPP
|
|
* @chip: nand chip info structure
|
|
* @addr: feature address.
|
|
* @subfeature_param: the subfeature parameters, a four bytes array.
|
|
*
|
|
* Should be used by NAND controller drivers that do not support the SET/GET
|
|
* FEATURES operations.
|
|
*/
|
|
int nand_get_set_features_notsupp(struct nand_chip *chip, int addr,
|
|
u8 *subfeature_param)
|
|
{
|
|
return -ENOTSUPP;
|
|
}
|
|
EXPORT_SYMBOL(nand_get_set_features_notsupp);
|
|
|
|
/**
|
|
* nand_wait - [DEFAULT] wait until the command is done
|
|
* @chip: NAND chip structure
|
|
*
|
|
* Wait for command done. This applies to erase and program only.
|
|
*/
|
|
static int nand_wait(struct nand_chip *chip)
|
|
{
|
|
struct mtd_info *mtd = nand_to_mtd(chip);
|
|
unsigned long timeo = 400;
|
|
u8 status;
|
|
int ret;
|
|
|
|
/*
|
|
* Apply this short delay always to ensure that we do wait tWB in any
|
|
* case on any machine.
|
|
*/
|
|
ndelay(100);
|
|
|
|
ret = nand_status_op(chip, NULL);
|
|
if (ret)
|
|
return ret;
|
|
|
|
if (mtd->oops_panic_write) {
|
|
panic_nand_wait(chip, timeo);
|
|
} else {
|
|
timeo = jiffies + msecs_to_jiffies(timeo);
|
|
do {
|
|
if (chip->legacy.dev_ready) {
|
|
if (chip->legacy.dev_ready(chip))
|
|
break;
|
|
} else {
|
|
ret = nand_read_data_op(chip, &status,
|
|
sizeof(status), true,
|
|
false);
|
|
if (ret)
|
|
return ret;
|
|
|
|
if (status & NAND_STATUS_READY)
|
|
break;
|
|
}
|
|
cond_resched();
|
|
} while (time_before(jiffies, timeo));
|
|
}
|
|
|
|
ret = nand_read_data_op(chip, &status, sizeof(status), true, false);
|
|
if (ret)
|
|
return ret;
|
|
|
|
/* This can happen if in case of timeout or buggy dev_ready */
|
|
WARN_ON(!(status & NAND_STATUS_READY));
|
|
return status;
|
|
}
|
|
|
|
void nand_legacy_set_defaults(struct nand_chip *chip)
|
|
{
|
|
unsigned int busw = chip->options & NAND_BUSWIDTH_16;
|
|
|
|
if (nand_has_exec_op(chip))
|
|
return;
|
|
|
|
/* check for proper chip_delay setup, set 20us if not */
|
|
if (!chip->legacy.chip_delay)
|
|
chip->legacy.chip_delay = 20;
|
|
|
|
/* check, if a user supplied command function given */
|
|
if (!chip->legacy.cmdfunc)
|
|
chip->legacy.cmdfunc = nand_command;
|
|
|
|
/* check, if a user supplied wait function given */
|
|
if (chip->legacy.waitfunc == NULL)
|
|
chip->legacy.waitfunc = nand_wait;
|
|
|
|
if (!chip->legacy.select_chip)
|
|
chip->legacy.select_chip = nand_select_chip;
|
|
|
|
/* If called twice, pointers that depend on busw may need to be reset */
|
|
if (!chip->legacy.read_byte || chip->legacy.read_byte == nand_read_byte)
|
|
chip->legacy.read_byte = busw ? nand_read_byte16 : nand_read_byte;
|
|
if (!chip->legacy.write_buf || chip->legacy.write_buf == nand_write_buf)
|
|
chip->legacy.write_buf = busw ? nand_write_buf16 : nand_write_buf;
|
|
if (!chip->legacy.write_byte || chip->legacy.write_byte == nand_write_byte)
|
|
chip->legacy.write_byte = busw ? nand_write_byte16 : nand_write_byte;
|
|
if (!chip->legacy.read_buf || chip->legacy.read_buf == nand_read_buf)
|
|
chip->legacy.read_buf = busw ? nand_read_buf16 : nand_read_buf;
|
|
}
|
|
|
|
void nand_legacy_adjust_cmdfunc(struct nand_chip *chip)
|
|
{
|
|
struct mtd_info *mtd = nand_to_mtd(chip);
|
|
|
|
/* Do not replace user supplied command function! */
|
|
if (mtd->writesize > 512 && chip->legacy.cmdfunc == nand_command)
|
|
chip->legacy.cmdfunc = nand_command_lp;
|
|
}
|
|
|
|
int nand_legacy_check_hooks(struct nand_chip *chip)
|
|
{
|
|
/*
|
|
* ->legacy.cmdfunc() is legacy and will only be used if ->exec_op() is
|
|
* not populated.
|
|
*/
|
|
if (nand_has_exec_op(chip))
|
|
return 0;
|
|
|
|
/*
|
|
* Default functions assigned for ->legacy.cmdfunc() and
|
|
* ->legacy.select_chip() both expect ->legacy.cmd_ctrl() to be
|
|
* populated.
|
|
*/
|
|
if ((!chip->legacy.cmdfunc || !chip->legacy.select_chip) &&
|
|
!chip->legacy.cmd_ctrl) {
|
|
pr_err("->legacy.cmd_ctrl() should be provided\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
return 0;
|
|
}
|