859 lines
21 KiB
C
859 lines
21 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Copyright 2004-2008 Freescale Semiconductor, Inc.
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* Copyright 2009 Semihalf.
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*
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* Approved as OSADL project by a majority of OSADL members and funded
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* by OSADL membership fees in 2009; for details see www.osadl.org.
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*
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* Based on original driver from Freescale Semiconductor
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* written by John Rigby <jrigby@freescale.com> on basis of mxc_nand.c.
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* Reworked and extended by Piotr Ziecik <kosmo@semihalf.com>.
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*/
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#include <linux/module.h>
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#include <linux/clk.h>
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#include <linux/gfp.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/rawnand.h>
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#include <linux/mtd/partitions.h>
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#include <linux/of_address.h>
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#include <linux/of_device.h>
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#include <linux/of_irq.h>
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#include <linux/of_platform.h>
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#include <asm/mpc5121.h>
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/* Addresses for NFC MAIN RAM BUFFER areas */
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#define NFC_MAIN_AREA(n) ((n) * 0x200)
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/* Addresses for NFC SPARE BUFFER areas */
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#define NFC_SPARE_BUFFERS 8
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#define NFC_SPARE_LEN 0x40
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#define NFC_SPARE_AREA(n) (0x1000 + ((n) * NFC_SPARE_LEN))
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/* MPC5121 NFC registers */
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#define NFC_BUF_ADDR 0x1E04
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#define NFC_FLASH_ADDR 0x1E06
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#define NFC_FLASH_CMD 0x1E08
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#define NFC_CONFIG 0x1E0A
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#define NFC_ECC_STATUS1 0x1E0C
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#define NFC_ECC_STATUS2 0x1E0E
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#define NFC_SPAS 0x1E10
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#define NFC_WRPROT 0x1E12
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#define NFC_NF_WRPRST 0x1E18
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#define NFC_CONFIG1 0x1E1A
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#define NFC_CONFIG2 0x1E1C
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#define NFC_UNLOCKSTART_BLK0 0x1E20
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#define NFC_UNLOCKEND_BLK0 0x1E22
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#define NFC_UNLOCKSTART_BLK1 0x1E24
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#define NFC_UNLOCKEND_BLK1 0x1E26
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#define NFC_UNLOCKSTART_BLK2 0x1E28
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#define NFC_UNLOCKEND_BLK2 0x1E2A
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#define NFC_UNLOCKSTART_BLK3 0x1E2C
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#define NFC_UNLOCKEND_BLK3 0x1E2E
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/* Bit Definitions: NFC_BUF_ADDR */
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#define NFC_RBA_MASK (7 << 0)
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#define NFC_ACTIVE_CS_SHIFT 5
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#define NFC_ACTIVE_CS_MASK (3 << NFC_ACTIVE_CS_SHIFT)
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/* Bit Definitions: NFC_CONFIG */
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#define NFC_BLS_UNLOCKED (1 << 1)
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/* Bit Definitions: NFC_CONFIG1 */
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#define NFC_ECC_4BIT (1 << 0)
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#define NFC_FULL_PAGE_DMA (1 << 1)
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#define NFC_SPARE_ONLY (1 << 2)
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#define NFC_ECC_ENABLE (1 << 3)
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#define NFC_INT_MASK (1 << 4)
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#define NFC_BIG_ENDIAN (1 << 5)
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#define NFC_RESET (1 << 6)
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#define NFC_CE (1 << 7)
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#define NFC_ONE_CYCLE (1 << 8)
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#define NFC_PPB_32 (0 << 9)
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#define NFC_PPB_64 (1 << 9)
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#define NFC_PPB_128 (2 << 9)
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#define NFC_PPB_256 (3 << 9)
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#define NFC_PPB_MASK (3 << 9)
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#define NFC_FULL_PAGE_INT (1 << 11)
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/* Bit Definitions: NFC_CONFIG2 */
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#define NFC_COMMAND (1 << 0)
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#define NFC_ADDRESS (1 << 1)
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#define NFC_INPUT (1 << 2)
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#define NFC_OUTPUT (1 << 3)
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#define NFC_ID (1 << 4)
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#define NFC_STATUS (1 << 5)
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#define NFC_CMD_FAIL (1 << 15)
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#define NFC_INT (1 << 15)
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/* Bit Definitions: NFC_WRPROT */
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#define NFC_WPC_LOCK_TIGHT (1 << 0)
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#define NFC_WPC_LOCK (1 << 1)
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#define NFC_WPC_UNLOCK (1 << 2)
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#define DRV_NAME "mpc5121_nfc"
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/* Timeouts */
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#define NFC_RESET_TIMEOUT 1000 /* 1 ms */
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#define NFC_TIMEOUT (HZ / 10) /* 1/10 s */
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struct mpc5121_nfc_prv {
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struct nand_controller controller;
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struct nand_chip chip;
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int irq;
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void __iomem *regs;
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struct clk *clk;
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wait_queue_head_t irq_waitq;
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uint column;
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int spareonly;
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void __iomem *csreg;
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struct device *dev;
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};
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static void mpc5121_nfc_done(struct mtd_info *mtd);
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/* Read NFC register */
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static inline u16 nfc_read(struct mtd_info *mtd, uint reg)
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{
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struct nand_chip *chip = mtd_to_nand(mtd);
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struct mpc5121_nfc_prv *prv = nand_get_controller_data(chip);
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return in_be16(prv->regs + reg);
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}
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/* Write NFC register */
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static inline void nfc_write(struct mtd_info *mtd, uint reg, u16 val)
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{
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struct nand_chip *chip = mtd_to_nand(mtd);
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struct mpc5121_nfc_prv *prv = nand_get_controller_data(chip);
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out_be16(prv->regs + reg, val);
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}
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/* Set bits in NFC register */
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static inline void nfc_set(struct mtd_info *mtd, uint reg, u16 bits)
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{
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nfc_write(mtd, reg, nfc_read(mtd, reg) | bits);
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}
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/* Clear bits in NFC register */
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static inline void nfc_clear(struct mtd_info *mtd, uint reg, u16 bits)
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{
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nfc_write(mtd, reg, nfc_read(mtd, reg) & ~bits);
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}
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/* Invoke address cycle */
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static inline void mpc5121_nfc_send_addr(struct mtd_info *mtd, u16 addr)
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{
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nfc_write(mtd, NFC_FLASH_ADDR, addr);
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nfc_write(mtd, NFC_CONFIG2, NFC_ADDRESS);
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mpc5121_nfc_done(mtd);
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}
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/* Invoke command cycle */
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static inline void mpc5121_nfc_send_cmd(struct mtd_info *mtd, u16 cmd)
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{
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nfc_write(mtd, NFC_FLASH_CMD, cmd);
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nfc_write(mtd, NFC_CONFIG2, NFC_COMMAND);
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mpc5121_nfc_done(mtd);
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}
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/* Send data from NFC buffers to NAND flash */
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static inline void mpc5121_nfc_send_prog_page(struct mtd_info *mtd)
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{
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nfc_clear(mtd, NFC_BUF_ADDR, NFC_RBA_MASK);
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nfc_write(mtd, NFC_CONFIG2, NFC_INPUT);
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mpc5121_nfc_done(mtd);
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}
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/* Receive data from NAND flash */
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static inline void mpc5121_nfc_send_read_page(struct mtd_info *mtd)
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{
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nfc_clear(mtd, NFC_BUF_ADDR, NFC_RBA_MASK);
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nfc_write(mtd, NFC_CONFIG2, NFC_OUTPUT);
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mpc5121_nfc_done(mtd);
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}
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/* Receive ID from NAND flash */
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static inline void mpc5121_nfc_send_read_id(struct mtd_info *mtd)
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{
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nfc_clear(mtd, NFC_BUF_ADDR, NFC_RBA_MASK);
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nfc_write(mtd, NFC_CONFIG2, NFC_ID);
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mpc5121_nfc_done(mtd);
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}
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/* Receive status from NAND flash */
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static inline void mpc5121_nfc_send_read_status(struct mtd_info *mtd)
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{
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nfc_clear(mtd, NFC_BUF_ADDR, NFC_RBA_MASK);
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nfc_write(mtd, NFC_CONFIG2, NFC_STATUS);
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mpc5121_nfc_done(mtd);
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}
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/* NFC interrupt handler */
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static irqreturn_t mpc5121_nfc_irq(int irq, void *data)
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{
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struct mtd_info *mtd = data;
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struct nand_chip *chip = mtd_to_nand(mtd);
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struct mpc5121_nfc_prv *prv = nand_get_controller_data(chip);
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nfc_set(mtd, NFC_CONFIG1, NFC_INT_MASK);
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wake_up(&prv->irq_waitq);
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return IRQ_HANDLED;
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}
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/* Wait for operation complete */
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static void mpc5121_nfc_done(struct mtd_info *mtd)
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{
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struct nand_chip *chip = mtd_to_nand(mtd);
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struct mpc5121_nfc_prv *prv = nand_get_controller_data(chip);
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int rv;
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if ((nfc_read(mtd, NFC_CONFIG2) & NFC_INT) == 0) {
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nfc_clear(mtd, NFC_CONFIG1, NFC_INT_MASK);
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rv = wait_event_timeout(prv->irq_waitq,
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(nfc_read(mtd, NFC_CONFIG2) & NFC_INT), NFC_TIMEOUT);
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if (!rv)
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dev_warn(prv->dev,
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"Timeout while waiting for interrupt.\n");
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}
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nfc_clear(mtd, NFC_CONFIG2, NFC_INT);
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}
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/* Do address cycle(s) */
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static void mpc5121_nfc_addr_cycle(struct mtd_info *mtd, int column, int page)
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{
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struct nand_chip *chip = mtd_to_nand(mtd);
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u32 pagemask = chip->pagemask;
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if (column != -1) {
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mpc5121_nfc_send_addr(mtd, column);
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if (mtd->writesize > 512)
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mpc5121_nfc_send_addr(mtd, column >> 8);
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}
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if (page != -1) {
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do {
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mpc5121_nfc_send_addr(mtd, page & 0xFF);
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page >>= 8;
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pagemask >>= 8;
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} while (pagemask);
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}
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}
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/* Control chip select signals */
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static void mpc5121_nfc_select_chip(struct nand_chip *nand, int chip)
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{
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struct mtd_info *mtd = nand_to_mtd(nand);
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if (chip < 0) {
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nfc_clear(mtd, NFC_CONFIG1, NFC_CE);
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return;
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}
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nfc_clear(mtd, NFC_BUF_ADDR, NFC_ACTIVE_CS_MASK);
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nfc_set(mtd, NFC_BUF_ADDR, (chip << NFC_ACTIVE_CS_SHIFT) &
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NFC_ACTIVE_CS_MASK);
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nfc_set(mtd, NFC_CONFIG1, NFC_CE);
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}
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/* Init external chip select logic on ADS5121 board */
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static int ads5121_chipselect_init(struct mtd_info *mtd)
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{
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struct nand_chip *chip = mtd_to_nand(mtd);
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struct mpc5121_nfc_prv *prv = nand_get_controller_data(chip);
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struct device_node *dn;
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dn = of_find_compatible_node(NULL, NULL, "fsl,mpc5121ads-cpld");
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if (dn) {
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prv->csreg = of_iomap(dn, 0);
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of_node_put(dn);
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if (!prv->csreg)
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return -ENOMEM;
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/* CPLD Register 9 controls NAND /CE Lines */
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prv->csreg += 9;
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return 0;
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}
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return -EINVAL;
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}
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/* Control chips select signal on ADS5121 board */
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static void ads5121_select_chip(struct nand_chip *nand, int chip)
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{
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struct mpc5121_nfc_prv *prv = nand_get_controller_data(nand);
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u8 v;
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v = in_8(prv->csreg);
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v |= 0x0F;
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if (chip >= 0) {
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mpc5121_nfc_select_chip(nand, 0);
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v &= ~(1 << chip);
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} else
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mpc5121_nfc_select_chip(nand, -1);
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out_8(prv->csreg, v);
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}
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/* Read NAND Ready/Busy signal */
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static int mpc5121_nfc_dev_ready(struct nand_chip *nand)
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{
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/*
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* NFC handles ready/busy signal internally. Therefore, this function
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* always returns status as ready.
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*/
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return 1;
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}
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/* Write command to NAND flash */
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static void mpc5121_nfc_command(struct nand_chip *chip, unsigned command,
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int column, int page)
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{
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struct mtd_info *mtd = nand_to_mtd(chip);
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struct mpc5121_nfc_prv *prv = nand_get_controller_data(chip);
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prv->column = (column >= 0) ? column : 0;
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prv->spareonly = 0;
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switch (command) {
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case NAND_CMD_PAGEPROG:
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mpc5121_nfc_send_prog_page(mtd);
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break;
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/*
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* NFC does not support sub-page reads and writes,
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* so emulate them using full page transfers.
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*/
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case NAND_CMD_READ0:
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column = 0;
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break;
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case NAND_CMD_READ1:
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prv->column += 256;
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command = NAND_CMD_READ0;
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column = 0;
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break;
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case NAND_CMD_READOOB:
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prv->spareonly = 1;
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command = NAND_CMD_READ0;
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column = 0;
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break;
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case NAND_CMD_SEQIN:
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mpc5121_nfc_command(chip, NAND_CMD_READ0, column, page);
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column = 0;
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break;
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case NAND_CMD_ERASE1:
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case NAND_CMD_ERASE2:
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case NAND_CMD_READID:
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case NAND_CMD_STATUS:
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break;
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default:
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return;
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}
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mpc5121_nfc_send_cmd(mtd, command);
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mpc5121_nfc_addr_cycle(mtd, column, page);
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switch (command) {
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case NAND_CMD_READ0:
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if (mtd->writesize > 512)
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mpc5121_nfc_send_cmd(mtd, NAND_CMD_READSTART);
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mpc5121_nfc_send_read_page(mtd);
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break;
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case NAND_CMD_READID:
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mpc5121_nfc_send_read_id(mtd);
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break;
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case NAND_CMD_STATUS:
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mpc5121_nfc_send_read_status(mtd);
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if (chip->options & NAND_BUSWIDTH_16)
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prv->column = 1;
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else
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prv->column = 0;
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break;
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}
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}
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/* Copy data from/to NFC spare buffers. */
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static void mpc5121_nfc_copy_spare(struct mtd_info *mtd, uint offset,
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u8 *buffer, uint size, int wr)
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{
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struct nand_chip *nand = mtd_to_nand(mtd);
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struct mpc5121_nfc_prv *prv = nand_get_controller_data(nand);
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uint o, s, sbsize, blksize;
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/*
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* NAND spare area is available through NFC spare buffers.
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* The NFC divides spare area into (page_size / 512) chunks.
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* Each chunk is placed into separate spare memory area, using
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* first (spare_size / num_of_chunks) bytes of the buffer.
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*
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* For NAND device in which the spare area is not divided fully
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* by the number of chunks, number of used bytes in each spare
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* buffer is rounded down to the nearest even number of bytes,
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* and all remaining bytes are added to the last used spare area.
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*
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* For more information read section 26.6.10 of MPC5121e
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* Microcontroller Reference Manual, Rev. 3.
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*/
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/* Calculate number of valid bytes in each spare buffer */
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sbsize = (mtd->oobsize / (mtd->writesize / 512)) & ~1;
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while (size) {
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/* Calculate spare buffer number */
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s = offset / sbsize;
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if (s > NFC_SPARE_BUFFERS - 1)
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s = NFC_SPARE_BUFFERS - 1;
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/*
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* Calculate offset to requested data block in selected spare
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* buffer and its size.
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*/
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o = offset - (s * sbsize);
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blksize = min(sbsize - o, size);
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if (wr)
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memcpy_toio(prv->regs + NFC_SPARE_AREA(s) + o,
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buffer, blksize);
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else
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memcpy_fromio(buffer,
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prv->regs + NFC_SPARE_AREA(s) + o, blksize);
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buffer += blksize;
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offset += blksize;
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size -= blksize;
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}
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}
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/* Copy data from/to NFC main and spare buffers */
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static void mpc5121_nfc_buf_copy(struct mtd_info *mtd, u_char *buf, int len,
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int wr)
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{
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struct nand_chip *chip = mtd_to_nand(mtd);
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struct mpc5121_nfc_prv *prv = nand_get_controller_data(chip);
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uint c = prv->column;
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uint l;
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/* Handle spare area access */
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if (prv->spareonly || c >= mtd->writesize) {
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/* Calculate offset from beginning of spare area */
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if (c >= mtd->writesize)
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c -= mtd->writesize;
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prv->column += len;
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mpc5121_nfc_copy_spare(mtd, c, buf, len, wr);
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return;
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}
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/*
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* Handle main area access - limit copy length to prevent
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* crossing main/spare boundary.
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*/
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l = min((uint)len, mtd->writesize - c);
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prv->column += l;
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if (wr)
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memcpy_toio(prv->regs + NFC_MAIN_AREA(0) + c, buf, l);
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else
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memcpy_fromio(buf, prv->regs + NFC_MAIN_AREA(0) + c, l);
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/* Handle crossing main/spare boundary */
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if (l != len) {
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buf += l;
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len -= l;
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mpc5121_nfc_buf_copy(mtd, buf, len, wr);
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}
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}
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/* Read data from NFC buffers */
|
|
static void mpc5121_nfc_read_buf(struct nand_chip *chip, u_char *buf, int len)
|
|
{
|
|
mpc5121_nfc_buf_copy(nand_to_mtd(chip), buf, len, 0);
|
|
}
|
|
|
|
/* Write data to NFC buffers */
|
|
static void mpc5121_nfc_write_buf(struct nand_chip *chip, const u_char *buf,
|
|
int len)
|
|
{
|
|
mpc5121_nfc_buf_copy(nand_to_mtd(chip), (u_char *)buf, len, 1);
|
|
}
|
|
|
|
/* Read byte from NFC buffers */
|
|
static u8 mpc5121_nfc_read_byte(struct nand_chip *chip)
|
|
{
|
|
u8 tmp;
|
|
|
|
mpc5121_nfc_read_buf(chip, &tmp, sizeof(tmp));
|
|
|
|
return tmp;
|
|
}
|
|
|
|
/*
|
|
* Read NFC configuration from Reset Config Word
|
|
*
|
|
* NFC is configured during reset in basis of information stored
|
|
* in Reset Config Word. There is no other way to set NAND block
|
|
* size, spare size and bus width.
|
|
*/
|
|
static int mpc5121_nfc_read_hw_config(struct mtd_info *mtd)
|
|
{
|
|
struct nand_chip *chip = mtd_to_nand(mtd);
|
|
struct mpc5121_nfc_prv *prv = nand_get_controller_data(chip);
|
|
struct mpc512x_reset_module *rm;
|
|
struct device_node *rmnode;
|
|
uint rcw_pagesize = 0;
|
|
uint rcw_sparesize = 0;
|
|
uint rcw_width;
|
|
uint rcwh;
|
|
uint romloc, ps;
|
|
int ret = 0;
|
|
|
|
rmnode = of_find_compatible_node(NULL, NULL, "fsl,mpc5121-reset");
|
|
if (!rmnode) {
|
|
dev_err(prv->dev, "Missing 'fsl,mpc5121-reset' "
|
|
"node in device tree!\n");
|
|
return -ENODEV;
|
|
}
|
|
|
|
rm = of_iomap(rmnode, 0);
|
|
if (!rm) {
|
|
dev_err(prv->dev, "Error mapping reset module node!\n");
|
|
ret = -EBUSY;
|
|
goto out;
|
|
}
|
|
|
|
rcwh = in_be32(&rm->rcwhr);
|
|
|
|
/* Bit 6: NFC bus width */
|
|
rcw_width = ((rcwh >> 6) & 0x1) ? 2 : 1;
|
|
|
|
/* Bit 7: NFC Page/Spare size */
|
|
ps = (rcwh >> 7) & 0x1;
|
|
|
|
/* Bits [22:21]: ROM Location */
|
|
romloc = (rcwh >> 21) & 0x3;
|
|
|
|
/* Decode RCW bits */
|
|
switch ((ps << 2) | romloc) {
|
|
case 0x00:
|
|
case 0x01:
|
|
rcw_pagesize = 512;
|
|
rcw_sparesize = 16;
|
|
break;
|
|
case 0x02:
|
|
case 0x03:
|
|
rcw_pagesize = 4096;
|
|
rcw_sparesize = 128;
|
|
break;
|
|
case 0x04:
|
|
case 0x05:
|
|
rcw_pagesize = 2048;
|
|
rcw_sparesize = 64;
|
|
break;
|
|
case 0x06:
|
|
case 0x07:
|
|
rcw_pagesize = 4096;
|
|
rcw_sparesize = 218;
|
|
break;
|
|
}
|
|
|
|
mtd->writesize = rcw_pagesize;
|
|
mtd->oobsize = rcw_sparesize;
|
|
if (rcw_width == 2)
|
|
chip->options |= NAND_BUSWIDTH_16;
|
|
|
|
dev_notice(prv->dev, "Configured for "
|
|
"%u-bit NAND, page size %u "
|
|
"with %u spare.\n",
|
|
rcw_width * 8, rcw_pagesize,
|
|
rcw_sparesize);
|
|
iounmap(rm);
|
|
out:
|
|
of_node_put(rmnode);
|
|
return ret;
|
|
}
|
|
|
|
/* Free driver resources */
|
|
static void mpc5121_nfc_free(struct device *dev, struct mtd_info *mtd)
|
|
{
|
|
struct nand_chip *chip = mtd_to_nand(mtd);
|
|
struct mpc5121_nfc_prv *prv = nand_get_controller_data(chip);
|
|
|
|
clk_disable_unprepare(prv->clk);
|
|
|
|
if (prv->csreg)
|
|
iounmap(prv->csreg);
|
|
}
|
|
|
|
static int mpc5121_nfc_attach_chip(struct nand_chip *chip)
|
|
{
|
|
if (chip->ecc.engine_type == NAND_ECC_ENGINE_TYPE_SOFT &&
|
|
chip->ecc.algo == NAND_ECC_ALGO_UNKNOWN)
|
|
chip->ecc.algo = NAND_ECC_ALGO_HAMMING;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct nand_controller_ops mpc5121_nfc_ops = {
|
|
.attach_chip = mpc5121_nfc_attach_chip,
|
|
};
|
|
|
|
static int mpc5121_nfc_probe(struct platform_device *op)
|
|
{
|
|
struct device_node *dn = op->dev.of_node;
|
|
struct clk *clk;
|
|
struct device *dev = &op->dev;
|
|
struct mpc5121_nfc_prv *prv;
|
|
struct resource res;
|
|
struct mtd_info *mtd;
|
|
struct nand_chip *chip;
|
|
unsigned long regs_paddr, regs_size;
|
|
const __be32 *chips_no;
|
|
int resettime = 0;
|
|
int retval = 0;
|
|
int rev, len;
|
|
|
|
/*
|
|
* Check SoC revision. This driver supports only NFC
|
|
* in MPC5121 revision 2 and MPC5123 revision 3.
|
|
*/
|
|
rev = (mfspr(SPRN_SVR) >> 4) & 0xF;
|
|
if ((rev != 2) && (rev != 3)) {
|
|
dev_err(dev, "SoC revision %u is not supported!\n", rev);
|
|
return -ENXIO;
|
|
}
|
|
|
|
prv = devm_kzalloc(dev, sizeof(*prv), GFP_KERNEL);
|
|
if (!prv)
|
|
return -ENOMEM;
|
|
|
|
chip = &prv->chip;
|
|
mtd = nand_to_mtd(chip);
|
|
|
|
nand_controller_init(&prv->controller);
|
|
prv->controller.ops = &mpc5121_nfc_ops;
|
|
chip->controller = &prv->controller;
|
|
|
|
mtd->dev.parent = dev;
|
|
nand_set_controller_data(chip, prv);
|
|
nand_set_flash_node(chip, dn);
|
|
prv->dev = dev;
|
|
|
|
/* Read NFC configuration from Reset Config Word */
|
|
retval = mpc5121_nfc_read_hw_config(mtd);
|
|
if (retval) {
|
|
dev_err(dev, "Unable to read NFC config!\n");
|
|
return retval;
|
|
}
|
|
|
|
prv->irq = irq_of_parse_and_map(dn, 0);
|
|
if (prv->irq == NO_IRQ) {
|
|
dev_err(dev, "Error mapping IRQ!\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
retval = of_address_to_resource(dn, 0, &res);
|
|
if (retval) {
|
|
dev_err(dev, "Error parsing memory region!\n");
|
|
return retval;
|
|
}
|
|
|
|
chips_no = of_get_property(dn, "chips", &len);
|
|
if (!chips_no || len != sizeof(*chips_no)) {
|
|
dev_err(dev, "Invalid/missing 'chips' property!\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
regs_paddr = res.start;
|
|
regs_size = resource_size(&res);
|
|
|
|
if (!devm_request_mem_region(dev, regs_paddr, regs_size, DRV_NAME)) {
|
|
dev_err(dev, "Error requesting memory region!\n");
|
|
return -EBUSY;
|
|
}
|
|
|
|
prv->regs = devm_ioremap(dev, regs_paddr, regs_size);
|
|
if (!prv->regs) {
|
|
dev_err(dev, "Error mapping memory region!\n");
|
|
return -ENOMEM;
|
|
}
|
|
|
|
mtd->name = "MPC5121 NAND";
|
|
chip->legacy.dev_ready = mpc5121_nfc_dev_ready;
|
|
chip->legacy.cmdfunc = mpc5121_nfc_command;
|
|
chip->legacy.read_byte = mpc5121_nfc_read_byte;
|
|
chip->legacy.read_buf = mpc5121_nfc_read_buf;
|
|
chip->legacy.write_buf = mpc5121_nfc_write_buf;
|
|
chip->legacy.select_chip = mpc5121_nfc_select_chip;
|
|
chip->legacy.set_features = nand_get_set_features_notsupp;
|
|
chip->legacy.get_features = nand_get_set_features_notsupp;
|
|
chip->bbt_options = NAND_BBT_USE_FLASH;
|
|
|
|
/* Support external chip-select logic on ADS5121 board */
|
|
if (of_machine_is_compatible("fsl,mpc5121ads")) {
|
|
retval = ads5121_chipselect_init(mtd);
|
|
if (retval) {
|
|
dev_err(dev, "Chipselect init error!\n");
|
|
return retval;
|
|
}
|
|
|
|
chip->legacy.select_chip = ads5121_select_chip;
|
|
}
|
|
|
|
/* Enable NFC clock */
|
|
clk = devm_clk_get(dev, "ipg");
|
|
if (IS_ERR(clk)) {
|
|
dev_err(dev, "Unable to acquire NFC clock!\n");
|
|
retval = PTR_ERR(clk);
|
|
goto error;
|
|
}
|
|
retval = clk_prepare_enable(clk);
|
|
if (retval) {
|
|
dev_err(dev, "Unable to enable NFC clock!\n");
|
|
goto error;
|
|
}
|
|
prv->clk = clk;
|
|
|
|
/* Reset NAND Flash controller */
|
|
nfc_set(mtd, NFC_CONFIG1, NFC_RESET);
|
|
while (nfc_read(mtd, NFC_CONFIG1) & NFC_RESET) {
|
|
if (resettime++ >= NFC_RESET_TIMEOUT) {
|
|
dev_err(dev, "Timeout while resetting NFC!\n");
|
|
retval = -EINVAL;
|
|
goto error;
|
|
}
|
|
|
|
udelay(1);
|
|
}
|
|
|
|
/* Enable write to NFC memory */
|
|
nfc_write(mtd, NFC_CONFIG, NFC_BLS_UNLOCKED);
|
|
|
|
/* Enable write to all NAND pages */
|
|
nfc_write(mtd, NFC_UNLOCKSTART_BLK0, 0x0000);
|
|
nfc_write(mtd, NFC_UNLOCKEND_BLK0, 0xFFFF);
|
|
nfc_write(mtd, NFC_WRPROT, NFC_WPC_UNLOCK);
|
|
|
|
/*
|
|
* Setup NFC:
|
|
* - Big Endian transfers,
|
|
* - Interrupt after full page read/write.
|
|
*/
|
|
nfc_write(mtd, NFC_CONFIG1, NFC_BIG_ENDIAN | NFC_INT_MASK |
|
|
NFC_FULL_PAGE_INT);
|
|
|
|
/* Set spare area size */
|
|
nfc_write(mtd, NFC_SPAS, mtd->oobsize >> 1);
|
|
|
|
init_waitqueue_head(&prv->irq_waitq);
|
|
retval = devm_request_irq(dev, prv->irq, &mpc5121_nfc_irq, 0, DRV_NAME,
|
|
mtd);
|
|
if (retval) {
|
|
dev_err(dev, "Error requesting IRQ!\n");
|
|
goto error;
|
|
}
|
|
|
|
/*
|
|
* This driver assumes that the default ECC engine should be TYPE_SOFT.
|
|
* Set ->engine_type before registering the NAND devices in order to
|
|
* provide a driver specific default value.
|
|
*/
|
|
chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_SOFT;
|
|
|
|
/* Detect NAND chips */
|
|
retval = nand_scan(chip, be32_to_cpup(chips_no));
|
|
if (retval) {
|
|
dev_err(dev, "NAND Flash not found !\n");
|
|
goto error;
|
|
}
|
|
|
|
/* Set erase block size */
|
|
switch (mtd->erasesize / mtd->writesize) {
|
|
case 32:
|
|
nfc_set(mtd, NFC_CONFIG1, NFC_PPB_32);
|
|
break;
|
|
|
|
case 64:
|
|
nfc_set(mtd, NFC_CONFIG1, NFC_PPB_64);
|
|
break;
|
|
|
|
case 128:
|
|
nfc_set(mtd, NFC_CONFIG1, NFC_PPB_128);
|
|
break;
|
|
|
|
case 256:
|
|
nfc_set(mtd, NFC_CONFIG1, NFC_PPB_256);
|
|
break;
|
|
|
|
default:
|
|
dev_err(dev, "Unsupported NAND flash!\n");
|
|
retval = -ENXIO;
|
|
goto error;
|
|
}
|
|
|
|
dev_set_drvdata(dev, mtd);
|
|
|
|
/* Register device in MTD */
|
|
retval = mtd_device_register(mtd, NULL, 0);
|
|
if (retval) {
|
|
dev_err(dev, "Error adding MTD device!\n");
|
|
goto error;
|
|
}
|
|
|
|
return 0;
|
|
error:
|
|
mpc5121_nfc_free(dev, mtd);
|
|
return retval;
|
|
}
|
|
|
|
static int mpc5121_nfc_remove(struct platform_device *op)
|
|
{
|
|
struct device *dev = &op->dev;
|
|
struct mtd_info *mtd = dev_get_drvdata(dev);
|
|
int ret;
|
|
|
|
ret = mtd_device_unregister(mtd);
|
|
WARN_ON(ret);
|
|
nand_cleanup(mtd_to_nand(mtd));
|
|
mpc5121_nfc_free(dev, mtd);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct of_device_id mpc5121_nfc_match[] = {
|
|
{ .compatible = "fsl,mpc5121-nfc", },
|
|
{},
|
|
};
|
|
MODULE_DEVICE_TABLE(of, mpc5121_nfc_match);
|
|
|
|
static struct platform_driver mpc5121_nfc_driver = {
|
|
.probe = mpc5121_nfc_probe,
|
|
.remove = mpc5121_nfc_remove,
|
|
.driver = {
|
|
.name = DRV_NAME,
|
|
.of_match_table = mpc5121_nfc_match,
|
|
},
|
|
};
|
|
|
|
module_platform_driver(mpc5121_nfc_driver);
|
|
|
|
MODULE_AUTHOR("Freescale Semiconductor, Inc.");
|
|
MODULE_DESCRIPTION("MPC5121 NAND MTD driver");
|
|
MODULE_LICENSE("GPL");
|