589 lines
18 KiB
C
589 lines
18 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* DMA support for Internal DMAC with SDHI SD/SDIO controller
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*
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* Copyright (C) 2016-19 Renesas Electronics Corporation
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* Copyright (C) 2016-17 Horms Solutions, Simon Horman
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* Copyright (C) 2018-19 Sang Engineering, Wolfram Sang
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*/
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#include <linux/bitops.h>
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#include <linux/device.h>
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#include <linux/dma-mapping.h>
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#include <linux/io-64-nonatomic-hi-lo.h>
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#include <linux/mfd/tmio.h>
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#include <linux/mmc/host.h>
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#include <linux/mod_devicetable.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/pagemap.h>
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#include <linux/scatterlist.h>
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#include <linux/sys_soc.h>
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#include "renesas_sdhi.h"
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#include "tmio_mmc.h"
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#define DM_CM_DTRAN_MODE 0x820
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#define DM_CM_DTRAN_CTRL 0x828
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#define DM_CM_RST 0x830
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#define DM_CM_INFO1 0x840
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#define DM_CM_INFO1_MASK 0x848
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#define DM_CM_INFO2 0x850
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#define DM_CM_INFO2_MASK 0x858
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#define DM_DTRAN_ADDR 0x880
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/* DM_CM_DTRAN_MODE */
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#define DTRAN_MODE_CH_NUM_CH0 0 /* "downstream" = for write commands */
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#define DTRAN_MODE_CH_NUM_CH1 BIT(16) /* "upstream" = for read commands */
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#define DTRAN_MODE_BUS_WIDTH (BIT(5) | BIT(4))
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#define DTRAN_MODE_ADDR_MODE BIT(0) /* 1 = Increment address, 0 = Fixed */
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/* DM_CM_DTRAN_CTRL */
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#define DTRAN_CTRL_DM_START BIT(0)
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/* DM_CM_RST */
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#define RST_DTRANRST1 BIT(9)
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#define RST_DTRANRST0 BIT(8)
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#define RST_RESERVED_BITS GENMASK_ULL(31, 0)
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/* DM_CM_INFO1 and DM_CM_INFO1_MASK */
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#define INFO1_CLEAR 0
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#define INFO1_MASK_CLEAR GENMASK_ULL(31, 0)
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#define INFO1_DTRANEND1 BIT(20)
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#define INFO1_DTRANEND1_OLD BIT(17)
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#define INFO1_DTRANEND0 BIT(16)
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/* DM_CM_INFO2 and DM_CM_INFO2_MASK */
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#define INFO2_MASK_CLEAR GENMASK_ULL(31, 0)
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#define INFO2_DTRANERR1 BIT(17)
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#define INFO2_DTRANERR0 BIT(16)
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enum renesas_sdhi_dma_cookie {
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COOKIE_UNMAPPED,
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COOKIE_PRE_MAPPED,
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COOKIE_MAPPED,
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};
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/*
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* Specification of this driver:
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* - host->chan_{rx,tx} will be used as a flag of enabling/disabling the dma
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* - Since this SDHI DMAC register set has 16 but 32-bit width, we
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* need a custom accessor.
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*/
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static unsigned long global_flags;
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/*
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* Workaround for avoiding to use RX DMAC by multiple channels.
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* On R-Car H3 ES1.* and M3-W ES1.0, when multiple SDHI channels use
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* RX DMAC simultaneously, sometimes hundreds of bytes data are not
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* stored into the system memory even if the DMAC interrupt happened.
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* So, this driver then uses one RX DMAC channel only.
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*/
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#define SDHI_INTERNAL_DMAC_RX_IN_USE 0
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/* Definitions for sampling clocks */
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static struct renesas_sdhi_scc rcar_gen3_scc_taps[] = {
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{
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.clk_rate = 0,
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.tap = 0x00000300,
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.tap_hs400_4tap = 0x00000100,
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},
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};
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static const struct renesas_sdhi_of_data of_data_rza2 = {
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.tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_CLK_ACTUAL |
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TMIO_MMC_HAVE_CBSY,
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.tmio_ocr_mask = MMC_VDD_32_33,
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.capabilities = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ |
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MMC_CAP_CMD23 | MMC_CAP_WAIT_WHILE_BUSY,
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.bus_shift = 2,
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.scc_offset = 0 - 0x1000,
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.taps = rcar_gen3_scc_taps,
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.taps_num = ARRAY_SIZE(rcar_gen3_scc_taps),
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/* DMAC can handle 32bit blk count but only 1 segment */
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.max_blk_count = UINT_MAX / TMIO_MAX_BLK_SIZE,
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.max_segs = 1,
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};
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static const struct renesas_sdhi_of_data of_data_rcar_gen3 = {
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.tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_CLK_ACTUAL |
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TMIO_MMC_HAVE_CBSY | TMIO_MMC_MIN_RCAR2,
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.capabilities = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ |
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MMC_CAP_CMD23 | MMC_CAP_WAIT_WHILE_BUSY,
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.capabilities2 = MMC_CAP2_NO_WRITE_PROTECT | MMC_CAP2_MERGE_CAPABLE,
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.bus_shift = 2,
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.scc_offset = 0x1000,
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.taps = rcar_gen3_scc_taps,
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.taps_num = ARRAY_SIZE(rcar_gen3_scc_taps),
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/* DMAC can handle 32bit blk count but only 1 segment */
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.max_blk_count = UINT_MAX / TMIO_MAX_BLK_SIZE,
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.max_segs = 1,
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.sdhi_flags = SDHI_FLAG_NEED_CLKH_FALLBACK,
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};
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static const struct renesas_sdhi_of_data of_data_rcar_gen3_no_sdh_fallback = {
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.tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_CLK_ACTUAL |
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TMIO_MMC_HAVE_CBSY | TMIO_MMC_MIN_RCAR2,
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.capabilities = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ |
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MMC_CAP_CMD23 | MMC_CAP_WAIT_WHILE_BUSY,
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.capabilities2 = MMC_CAP2_NO_WRITE_PROTECT | MMC_CAP2_MERGE_CAPABLE,
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.bus_shift = 2,
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.scc_offset = 0x1000,
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.taps = rcar_gen3_scc_taps,
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.taps_num = ARRAY_SIZE(rcar_gen3_scc_taps),
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/* DMAC can handle 32bit blk count but only 1 segment */
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.max_blk_count = UINT_MAX / TMIO_MAX_BLK_SIZE,
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.max_segs = 1,
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};
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static const u8 r8a7796_es13_calib_table[2][SDHI_CALIB_TABLE_MAX] = {
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{ 3, 3, 3, 3, 3, 3, 3, 4, 4, 5, 6, 7, 8, 9, 10, 15,
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16, 16, 16, 16, 16, 16, 17, 18, 18, 19, 20, 21, 22, 23, 24, 25 },
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{ 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 6, 7, 8, 11,
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12, 17, 18, 18, 18, 18, 18, 18, 18, 19, 20, 21, 22, 23, 25, 25 }
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};
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static const u8 r8a77965_calib_table[2][SDHI_CALIB_TABLE_MAX] = {
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{ 1, 2, 6, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 16,
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17, 18, 19, 20, 21, 22, 23, 24, 25, 25, 26, 27, 28, 29, 30, 31 },
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{ 2, 3, 4, 4, 5, 6, 7, 9, 10, 11, 12, 13, 14, 15, 16, 17,
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17, 17, 20, 21, 22, 23, 24, 25, 27, 28, 29, 30, 31, 31, 31, 31 }
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};
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static const u8 r8a77990_calib_table[2][SDHI_CALIB_TABLE_MAX] = {
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{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
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{ 0, 0, 0, 1, 2, 3, 3, 4, 4, 4, 5, 5, 6, 8, 9, 10,
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11, 12, 13, 15, 16, 17, 17, 18, 18, 19, 20, 22, 24, 25, 26, 26 }
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};
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static const struct renesas_sdhi_quirks sdhi_quirks_4tap_nohs400 = {
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.hs400_disabled = true,
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.hs400_4taps = true,
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};
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static const struct renesas_sdhi_quirks sdhi_quirks_4tap_nohs400_one_rx = {
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.hs400_disabled = true,
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.hs400_4taps = true,
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.dma_one_rx_only = true,
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.old_info1_layout = true,
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};
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static const struct renesas_sdhi_quirks sdhi_quirks_4tap = {
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.hs400_4taps = true,
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.hs400_bad_taps = BIT(2) | BIT(3) | BIT(6) | BIT(7),
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.manual_tap_correction = true,
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};
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static const struct renesas_sdhi_quirks sdhi_quirks_nohs400 = {
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.hs400_disabled = true,
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};
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static const struct renesas_sdhi_quirks sdhi_quirks_fixed_addr = {
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.fixed_addr_mode = true,
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};
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static const struct renesas_sdhi_quirks sdhi_quirks_bad_taps1357 = {
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.hs400_bad_taps = BIT(1) | BIT(3) | BIT(5) | BIT(7),
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.manual_tap_correction = true,
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};
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static const struct renesas_sdhi_quirks sdhi_quirks_bad_taps2367 = {
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.hs400_bad_taps = BIT(2) | BIT(3) | BIT(6) | BIT(7),
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.manual_tap_correction = true,
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};
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static const struct renesas_sdhi_quirks sdhi_quirks_r8a7796_es13 = {
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.hs400_4taps = true,
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.hs400_bad_taps = BIT(2) | BIT(3) | BIT(6) | BIT(7),
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.hs400_calib_table = r8a7796_es13_calib_table,
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.manual_tap_correction = true,
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};
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static const struct renesas_sdhi_quirks sdhi_quirks_r8a77965 = {
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.hs400_bad_taps = BIT(2) | BIT(3) | BIT(6) | BIT(7),
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.hs400_calib_table = r8a77965_calib_table,
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.manual_tap_correction = true,
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};
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static const struct renesas_sdhi_quirks sdhi_quirks_r8a77990 = {
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.hs400_calib_table = r8a77990_calib_table,
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.manual_tap_correction = true,
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};
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/*
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* Note for r8a7796 / r8a774a1: we can't distinguish ES1.1 and 1.2 as of now.
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* So, we want to treat them equally and only have a match for ES1.2 to enforce
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* this if there ever will be a way to distinguish ES1.2.
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*/
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static const struct soc_device_attribute sdhi_quirks_match[] = {
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{ .soc_id = "r8a774a1", .revision = "ES1.[012]", .data = &sdhi_quirks_4tap_nohs400 },
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{ .soc_id = "r8a7795", .revision = "ES1.*", .data = &sdhi_quirks_4tap_nohs400_one_rx },
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{ .soc_id = "r8a7795", .revision = "ES2.0", .data = &sdhi_quirks_4tap },
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{ .soc_id = "r8a7796", .revision = "ES1.0", .data = &sdhi_quirks_4tap_nohs400_one_rx },
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{ .soc_id = "r8a7796", .revision = "ES1.[12]", .data = &sdhi_quirks_4tap_nohs400 },
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{ .soc_id = "r8a7796", .revision = "ES1.*", .data = &sdhi_quirks_r8a7796_es13 },
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{ .soc_id = "r8a77980", .revision = "ES1.*", .data = &sdhi_quirks_nohs400 },
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{ /* Sentinel. */ }
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};
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static const struct renesas_sdhi_of_data_with_quirks of_r8a7795_compatible = {
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.of_data = &of_data_rcar_gen3,
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.quirks = &sdhi_quirks_bad_taps2367,
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};
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static const struct renesas_sdhi_of_data_with_quirks of_r8a77961_compatible = {
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.of_data = &of_data_rcar_gen3,
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.quirks = &sdhi_quirks_bad_taps1357,
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};
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static const struct renesas_sdhi_of_data_with_quirks of_r8a77965_compatible = {
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.of_data = &of_data_rcar_gen3,
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.quirks = &sdhi_quirks_r8a77965,
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};
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static const struct renesas_sdhi_of_data_with_quirks of_r8a77970_compatible = {
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.of_data = &of_data_rcar_gen3_no_sdh_fallback,
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.quirks = &sdhi_quirks_nohs400,
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};
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static const struct renesas_sdhi_of_data_with_quirks of_r8a77990_compatible = {
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.of_data = &of_data_rcar_gen3,
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.quirks = &sdhi_quirks_r8a77990,
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};
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static const struct renesas_sdhi_of_data_with_quirks of_rcar_gen3_compatible = {
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.of_data = &of_data_rcar_gen3,
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};
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static const struct renesas_sdhi_of_data_with_quirks of_rcar_gen3_nohs400_compatible = {
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.of_data = &of_data_rcar_gen3,
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.quirks = &sdhi_quirks_nohs400,
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};
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static const struct renesas_sdhi_of_data_with_quirks of_rza2_compatible = {
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.of_data = &of_data_rza2,
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.quirks = &sdhi_quirks_fixed_addr,
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};
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static const struct of_device_id renesas_sdhi_internal_dmac_of_match[] = {
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{ .compatible = "renesas,sdhi-r7s9210", .data = &of_rza2_compatible, },
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{ .compatible = "renesas,sdhi-mmc-r8a77470", .data = &of_rcar_gen3_compatible, },
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{ .compatible = "renesas,sdhi-r8a7795", .data = &of_r8a7795_compatible, },
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{ .compatible = "renesas,sdhi-r8a77961", .data = &of_r8a77961_compatible, },
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{ .compatible = "renesas,sdhi-r8a77965", .data = &of_r8a77965_compatible, },
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{ .compatible = "renesas,sdhi-r8a77970", .data = &of_r8a77970_compatible, },
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{ .compatible = "renesas,sdhi-r8a77990", .data = &of_r8a77990_compatible, },
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{ .compatible = "renesas,sdhi-r8a77995", .data = &of_rcar_gen3_nohs400_compatible, },
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{ .compatible = "renesas,rcar-gen3-sdhi", .data = &of_rcar_gen3_compatible, },
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{ .compatible = "renesas,rcar-gen4-sdhi", .data = &of_rcar_gen3_compatible, },
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{},
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};
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MODULE_DEVICE_TABLE(of, renesas_sdhi_internal_dmac_of_match);
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static void
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renesas_sdhi_internal_dmac_dm_write(struct tmio_mmc_host *host,
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int addr, u64 val)
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{
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writeq(val, host->ctl + addr);
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}
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static void
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renesas_sdhi_internal_dmac_enable_dma(struct tmio_mmc_host *host, bool enable)
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{
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struct renesas_sdhi *priv = host_to_priv(host);
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if (!host->chan_tx || !host->chan_rx)
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return;
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if (!enable)
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renesas_sdhi_internal_dmac_dm_write(host, DM_CM_INFO1,
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INFO1_CLEAR);
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if (priv->dma_priv.enable)
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priv->dma_priv.enable(host, enable);
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}
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static void
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renesas_sdhi_internal_dmac_abort_dma(struct tmio_mmc_host *host)
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{
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u64 val = RST_DTRANRST1 | RST_DTRANRST0;
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renesas_sdhi_internal_dmac_enable_dma(host, false);
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renesas_sdhi_internal_dmac_dm_write(host, DM_CM_RST,
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RST_RESERVED_BITS & ~val);
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renesas_sdhi_internal_dmac_dm_write(host, DM_CM_RST,
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RST_RESERVED_BITS | val);
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clear_bit(SDHI_INTERNAL_DMAC_RX_IN_USE, &global_flags);
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renesas_sdhi_internal_dmac_enable_dma(host, true);
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}
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static void
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renesas_sdhi_internal_dmac_dataend_dma(struct tmio_mmc_host *host)
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{
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struct renesas_sdhi *priv = host_to_priv(host);
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tasklet_schedule(&priv->dma_priv.dma_complete);
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}
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/*
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* renesas_sdhi_internal_dmac_map() will be called with two different
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* sg pointers in two mmc_data by .pre_req(), but tmio host can have a single
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* sg_ptr only. So, renesas_sdhi_internal_dmac_{un}map() should use a sg
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* pointer in a mmc_data instead of host->sg_ptr.
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*/
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static void
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renesas_sdhi_internal_dmac_unmap(struct tmio_mmc_host *host,
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struct mmc_data *data,
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enum renesas_sdhi_dma_cookie cookie)
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{
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bool unmap = cookie == COOKIE_UNMAPPED ? (data->host_cookie != cookie) :
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(data->host_cookie == cookie);
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if (unmap) {
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dma_unmap_sg(&host->pdev->dev, data->sg, data->sg_len,
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mmc_get_dma_dir(data));
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data->host_cookie = COOKIE_UNMAPPED;
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}
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}
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static bool
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renesas_sdhi_internal_dmac_map(struct tmio_mmc_host *host,
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struct mmc_data *data,
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enum renesas_sdhi_dma_cookie cookie)
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{
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if (data->host_cookie == COOKIE_PRE_MAPPED)
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return true;
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if (!dma_map_sg(&host->pdev->dev, data->sg, data->sg_len,
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mmc_get_dma_dir(data)))
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return false;
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data->host_cookie = cookie;
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/* This DMAC needs buffers to be 128-byte aligned */
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if (!IS_ALIGNED(sg_dma_address(data->sg), 128)) {
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renesas_sdhi_internal_dmac_unmap(host, data, cookie);
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return false;
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}
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return true;
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}
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static void
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renesas_sdhi_internal_dmac_start_dma(struct tmio_mmc_host *host,
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struct mmc_data *data)
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{
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struct renesas_sdhi *priv = host_to_priv(host);
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struct scatterlist *sg = host->sg_ptr;
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u32 dtran_mode = DTRAN_MODE_BUS_WIDTH;
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if (!(priv->quirks && priv->quirks->fixed_addr_mode))
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dtran_mode |= DTRAN_MODE_ADDR_MODE;
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if (!renesas_sdhi_internal_dmac_map(host, data, COOKIE_MAPPED))
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goto force_pio;
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if (data->flags & MMC_DATA_READ) {
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dtran_mode |= DTRAN_MODE_CH_NUM_CH1;
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if (priv->quirks && priv->quirks->dma_one_rx_only &&
|
|
test_and_set_bit(SDHI_INTERNAL_DMAC_RX_IN_USE, &global_flags))
|
|
goto force_pio_with_unmap;
|
|
} else {
|
|
dtran_mode |= DTRAN_MODE_CH_NUM_CH0;
|
|
}
|
|
|
|
renesas_sdhi_internal_dmac_enable_dma(host, true);
|
|
|
|
/* set dma parameters */
|
|
renesas_sdhi_internal_dmac_dm_write(host, DM_CM_DTRAN_MODE,
|
|
dtran_mode);
|
|
renesas_sdhi_internal_dmac_dm_write(host, DM_DTRAN_ADDR,
|
|
sg_dma_address(sg));
|
|
|
|
host->dma_on = true;
|
|
|
|
return;
|
|
|
|
force_pio_with_unmap:
|
|
renesas_sdhi_internal_dmac_unmap(host, data, COOKIE_UNMAPPED);
|
|
|
|
force_pio:
|
|
renesas_sdhi_internal_dmac_enable_dma(host, false);
|
|
}
|
|
|
|
static void renesas_sdhi_internal_dmac_issue_tasklet_fn(unsigned long arg)
|
|
{
|
|
struct tmio_mmc_host *host = (struct tmio_mmc_host *)arg;
|
|
|
|
tmio_mmc_enable_mmc_irqs(host, TMIO_STAT_DATAEND);
|
|
|
|
/* start the DMAC */
|
|
renesas_sdhi_internal_dmac_dm_write(host, DM_CM_DTRAN_CTRL,
|
|
DTRAN_CTRL_DM_START);
|
|
}
|
|
|
|
static bool renesas_sdhi_internal_dmac_complete(struct tmio_mmc_host *host)
|
|
{
|
|
enum dma_data_direction dir;
|
|
|
|
if (!host->dma_on)
|
|
return false;
|
|
|
|
if (!host->data)
|
|
return false;
|
|
|
|
if (host->data->flags & MMC_DATA_READ)
|
|
dir = DMA_FROM_DEVICE;
|
|
else
|
|
dir = DMA_TO_DEVICE;
|
|
|
|
renesas_sdhi_internal_dmac_enable_dma(host, false);
|
|
renesas_sdhi_internal_dmac_unmap(host, host->data, COOKIE_MAPPED);
|
|
|
|
if (dir == DMA_FROM_DEVICE)
|
|
clear_bit(SDHI_INTERNAL_DMAC_RX_IN_USE, &global_flags);
|
|
|
|
host->dma_on = false;
|
|
|
|
return true;
|
|
}
|
|
|
|
static void renesas_sdhi_internal_dmac_complete_tasklet_fn(unsigned long arg)
|
|
{
|
|
struct tmio_mmc_host *host = (struct tmio_mmc_host *)arg;
|
|
|
|
spin_lock_irq(&host->lock);
|
|
if (!renesas_sdhi_internal_dmac_complete(host))
|
|
goto out;
|
|
|
|
tmio_mmc_do_data_irq(host);
|
|
out:
|
|
spin_unlock_irq(&host->lock);
|
|
}
|
|
|
|
static void renesas_sdhi_internal_dmac_end_dma(struct tmio_mmc_host *host)
|
|
{
|
|
if (host->data)
|
|
renesas_sdhi_internal_dmac_complete(host);
|
|
}
|
|
|
|
static void renesas_sdhi_internal_dmac_post_req(struct mmc_host *mmc,
|
|
struct mmc_request *mrq,
|
|
int err)
|
|
{
|
|
struct tmio_mmc_host *host = mmc_priv(mmc);
|
|
struct mmc_data *data = mrq->data;
|
|
|
|
if (!data)
|
|
return;
|
|
|
|
renesas_sdhi_internal_dmac_unmap(host, data, COOKIE_UNMAPPED);
|
|
}
|
|
|
|
static void renesas_sdhi_internal_dmac_pre_req(struct mmc_host *mmc,
|
|
struct mmc_request *mrq)
|
|
{
|
|
struct tmio_mmc_host *host = mmc_priv(mmc);
|
|
struct mmc_data *data = mrq->data;
|
|
|
|
if (!data)
|
|
return;
|
|
|
|
data->host_cookie = COOKIE_UNMAPPED;
|
|
renesas_sdhi_internal_dmac_map(host, data, COOKIE_PRE_MAPPED);
|
|
}
|
|
|
|
static void
|
|
renesas_sdhi_internal_dmac_request_dma(struct tmio_mmc_host *host,
|
|
struct tmio_mmc_data *pdata)
|
|
{
|
|
struct renesas_sdhi *priv = host_to_priv(host);
|
|
|
|
/* Disable DMAC interrupts, we don't use them */
|
|
renesas_sdhi_internal_dmac_dm_write(host, DM_CM_INFO1_MASK,
|
|
INFO1_MASK_CLEAR);
|
|
renesas_sdhi_internal_dmac_dm_write(host, DM_CM_INFO2_MASK,
|
|
INFO2_MASK_CLEAR);
|
|
|
|
/* Each value is set to non-zero to assume "enabling" each DMA */
|
|
host->chan_rx = host->chan_tx = (void *)0xdeadbeaf;
|
|
|
|
tasklet_init(&priv->dma_priv.dma_complete,
|
|
renesas_sdhi_internal_dmac_complete_tasklet_fn,
|
|
(unsigned long)host);
|
|
tasklet_init(&host->dma_issue,
|
|
renesas_sdhi_internal_dmac_issue_tasklet_fn,
|
|
(unsigned long)host);
|
|
|
|
/* Add pre_req and post_req */
|
|
host->ops.pre_req = renesas_sdhi_internal_dmac_pre_req;
|
|
host->ops.post_req = renesas_sdhi_internal_dmac_post_req;
|
|
}
|
|
|
|
static void
|
|
renesas_sdhi_internal_dmac_release_dma(struct tmio_mmc_host *host)
|
|
{
|
|
/* Each value is set to zero to assume "disabling" each DMA */
|
|
host->chan_rx = host->chan_tx = NULL;
|
|
}
|
|
|
|
static const struct tmio_mmc_dma_ops renesas_sdhi_internal_dmac_dma_ops = {
|
|
.start = renesas_sdhi_internal_dmac_start_dma,
|
|
.enable = renesas_sdhi_internal_dmac_enable_dma,
|
|
.request = renesas_sdhi_internal_dmac_request_dma,
|
|
.release = renesas_sdhi_internal_dmac_release_dma,
|
|
.abort = renesas_sdhi_internal_dmac_abort_dma,
|
|
.dataend = renesas_sdhi_internal_dmac_dataend_dma,
|
|
.end = renesas_sdhi_internal_dmac_end_dma,
|
|
};
|
|
|
|
static int renesas_sdhi_internal_dmac_probe(struct platform_device *pdev)
|
|
{
|
|
const struct soc_device_attribute *attr;
|
|
const struct renesas_sdhi_of_data_with_quirks *of_data_quirks;
|
|
const struct renesas_sdhi_quirks *quirks;
|
|
struct device *dev = &pdev->dev;
|
|
|
|
of_data_quirks = of_device_get_match_data(&pdev->dev);
|
|
quirks = of_data_quirks->quirks;
|
|
|
|
attr = soc_device_match(sdhi_quirks_match);
|
|
if (attr)
|
|
quirks = attr->data;
|
|
|
|
/* value is max of SD_SECCNT. Confirmed by HW engineers */
|
|
dma_set_max_seg_size(dev, 0xffffffff);
|
|
|
|
return renesas_sdhi_probe(pdev, &renesas_sdhi_internal_dmac_dma_ops,
|
|
of_data_quirks->of_data, quirks);
|
|
}
|
|
|
|
static const struct dev_pm_ops renesas_sdhi_internal_dmac_dev_pm_ops = {
|
|
SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
|
|
pm_runtime_force_resume)
|
|
SET_RUNTIME_PM_OPS(tmio_mmc_host_runtime_suspend,
|
|
tmio_mmc_host_runtime_resume,
|
|
NULL)
|
|
};
|
|
|
|
static struct platform_driver renesas_internal_dmac_sdhi_driver = {
|
|
.driver = {
|
|
.name = "renesas_sdhi_internal_dmac",
|
|
.probe_type = PROBE_PREFER_ASYNCHRONOUS,
|
|
.pm = &renesas_sdhi_internal_dmac_dev_pm_ops,
|
|
.of_match_table = renesas_sdhi_internal_dmac_of_match,
|
|
},
|
|
.probe = renesas_sdhi_internal_dmac_probe,
|
|
.remove = renesas_sdhi_remove,
|
|
};
|
|
|
|
module_platform_driver(renesas_internal_dmac_sdhi_driver);
|
|
|
|
MODULE_DESCRIPTION("Renesas SDHI driver for internal DMAC");
|
|
MODULE_AUTHOR("Yoshihiro Shimoda");
|
|
MODULE_LICENSE("GPL v2");
|