251 lines
6.3 KiB
C
251 lines
6.3 KiB
C
/*
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* Copyright (C) 2007-2013 Michal Simek <monstr@monstr.eu>
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* Copyright (C) 2012-2013 Xilinx, Inc.
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* Copyright (C) 2007-2009 PetaLogix
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* Copyright (C) 2006 Atmark Techno, Inc.
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/irqdomain.h>
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#include <linux/irq.h>
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#include <linux/irqchip.h>
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#include <linux/irqchip/chained_irq.h>
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#include <linux/of_address.h>
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#include <linux/io.h>
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#include <linux/jump_label.h>
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#include <linux/bug.h>
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#include <linux/of_irq.h>
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/* No one else should require these constants, so define them locally here. */
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#define ISR 0x00 /* Interrupt Status Register */
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#define IPR 0x04 /* Interrupt Pending Register */
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#define IER 0x08 /* Interrupt Enable Register */
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#define IAR 0x0c /* Interrupt Acknowledge Register */
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#define SIE 0x10 /* Set Interrupt Enable bits */
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#define CIE 0x14 /* Clear Interrupt Enable bits */
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#define IVR 0x18 /* Interrupt Vector Register */
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#define MER 0x1c /* Master Enable Register */
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#define MER_ME (1<<0)
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#define MER_HIE (1<<1)
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#define SPURIOUS_IRQ (-1U)
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static DEFINE_STATIC_KEY_FALSE(xintc_is_be);
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struct xintc_irq_chip {
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void __iomem *base;
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struct irq_domain *root_domain;
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u32 intr_mask;
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u32 nr_irq;
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};
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static struct xintc_irq_chip *primary_intc;
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static void xintc_write(struct xintc_irq_chip *irqc, int reg, u32 data)
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{
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if (static_branch_unlikely(&xintc_is_be))
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iowrite32be(data, irqc->base + reg);
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else
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iowrite32(data, irqc->base + reg);
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}
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static u32 xintc_read(struct xintc_irq_chip *irqc, int reg)
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{
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if (static_branch_unlikely(&xintc_is_be))
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return ioread32be(irqc->base + reg);
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else
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return ioread32(irqc->base + reg);
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}
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static void intc_enable_or_unmask(struct irq_data *d)
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{
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struct xintc_irq_chip *irqc = irq_data_get_irq_chip_data(d);
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unsigned long mask = BIT(d->hwirq);
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pr_debug("irq-xilinx: enable_or_unmask: %ld\n", d->hwirq);
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/* ack level irqs because they can't be acked during
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* ack function since the handle_level_irq function
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* acks the irq before calling the interrupt handler
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*/
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if (irqd_is_level_type(d))
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xintc_write(irqc, IAR, mask);
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xintc_write(irqc, SIE, mask);
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}
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static void intc_disable_or_mask(struct irq_data *d)
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{
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struct xintc_irq_chip *irqc = irq_data_get_irq_chip_data(d);
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pr_debug("irq-xilinx: disable: %ld\n", d->hwirq);
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xintc_write(irqc, CIE, BIT(d->hwirq));
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}
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static void intc_ack(struct irq_data *d)
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{
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struct xintc_irq_chip *irqc = irq_data_get_irq_chip_data(d);
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pr_debug("irq-xilinx: ack: %ld\n", d->hwirq);
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xintc_write(irqc, IAR, BIT(d->hwirq));
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}
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static void intc_mask_ack(struct irq_data *d)
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{
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struct xintc_irq_chip *irqc = irq_data_get_irq_chip_data(d);
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unsigned long mask = BIT(d->hwirq);
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pr_debug("irq-xilinx: disable_and_ack: %ld\n", d->hwirq);
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xintc_write(irqc, CIE, mask);
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xintc_write(irqc, IAR, mask);
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}
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static struct irq_chip intc_dev = {
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.name = "Xilinx INTC",
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.irq_unmask = intc_enable_or_unmask,
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.irq_mask = intc_disable_or_mask,
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.irq_ack = intc_ack,
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.irq_mask_ack = intc_mask_ack,
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};
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static int xintc_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
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{
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struct xintc_irq_chip *irqc = d->host_data;
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if (irqc->intr_mask & BIT(hw)) {
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irq_set_chip_and_handler_name(irq, &intc_dev,
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handle_edge_irq, "edge");
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irq_clear_status_flags(irq, IRQ_LEVEL);
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} else {
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irq_set_chip_and_handler_name(irq, &intc_dev,
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handle_level_irq, "level");
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irq_set_status_flags(irq, IRQ_LEVEL);
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}
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irq_set_chip_data(irq, irqc);
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return 0;
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}
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static const struct irq_domain_ops xintc_irq_domain_ops = {
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.xlate = irq_domain_xlate_onetwocell,
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.map = xintc_map,
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};
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static void xil_intc_irq_handler(struct irq_desc *desc)
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{
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struct irq_chip *chip = irq_desc_get_chip(desc);
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struct xintc_irq_chip *irqc;
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irqc = irq_data_get_irq_handler_data(&desc->irq_data);
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chained_irq_enter(chip, desc);
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do {
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u32 hwirq = xintc_read(irqc, IVR);
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if (hwirq == -1U)
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break;
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generic_handle_domain_irq(irqc->root_domain, hwirq);
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} while (true);
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chained_irq_exit(chip, desc);
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}
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static void xil_intc_handle_irq(struct pt_regs *regs)
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{
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u32 hwirq;
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do {
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hwirq = xintc_read(primary_intc, IVR);
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if (unlikely(hwirq == SPURIOUS_IRQ))
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break;
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generic_handle_domain_irq(primary_intc->root_domain, hwirq);
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} while (true);
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}
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static int __init xilinx_intc_of_init(struct device_node *intc,
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struct device_node *parent)
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{
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struct xintc_irq_chip *irqc;
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int ret, irq;
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irqc = kzalloc(sizeof(*irqc), GFP_KERNEL);
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if (!irqc)
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return -ENOMEM;
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irqc->base = of_iomap(intc, 0);
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BUG_ON(!irqc->base);
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ret = of_property_read_u32(intc, "xlnx,num-intr-inputs", &irqc->nr_irq);
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if (ret < 0) {
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pr_err("irq-xilinx: unable to read xlnx,num-intr-inputs\n");
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goto error;
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}
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ret = of_property_read_u32(intc, "xlnx,kind-of-intr", &irqc->intr_mask);
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if (ret < 0) {
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pr_warn("irq-xilinx: unable to read xlnx,kind-of-intr\n");
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irqc->intr_mask = 0;
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}
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if (irqc->intr_mask >> irqc->nr_irq)
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pr_warn("irq-xilinx: mismatch in kind-of-intr param\n");
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pr_info("irq-xilinx: %pOF: num_irq=%d, edge=0x%x\n",
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intc, irqc->nr_irq, irqc->intr_mask);
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/*
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* Disable all external interrupts until they are
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* explicitly requested.
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*/
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xintc_write(irqc, IER, 0);
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/* Acknowledge any pending interrupts just in case. */
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xintc_write(irqc, IAR, 0xffffffff);
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/* Turn on the Master Enable. */
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xintc_write(irqc, MER, MER_HIE | MER_ME);
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if (xintc_read(irqc, MER) != (MER_HIE | MER_ME)) {
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static_branch_enable(&xintc_is_be);
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xintc_write(irqc, MER, MER_HIE | MER_ME);
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}
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irqc->root_domain = irq_domain_add_linear(intc, irqc->nr_irq,
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&xintc_irq_domain_ops, irqc);
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if (!irqc->root_domain) {
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pr_err("irq-xilinx: Unable to create IRQ domain\n");
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ret = -EINVAL;
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goto error;
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}
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if (parent) {
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irq = irq_of_parse_and_map(intc, 0);
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if (irq) {
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irq_set_chained_handler_and_data(irq,
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xil_intc_irq_handler,
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irqc);
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} else {
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pr_err("irq-xilinx: interrupts property not in DT\n");
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ret = -EINVAL;
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goto error;
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}
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} else {
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primary_intc = irqc;
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irq_set_default_host(primary_intc->root_domain);
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set_handle_irq(xil_intc_handle_irq);
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}
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return 0;
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error:
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iounmap(irqc->base);
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kfree(irqc);
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return ret;
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}
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IRQCHIP_DECLARE(xilinx_intc_xps, "xlnx,xps-intc-1.00.a", xilinx_intc_of_init);
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IRQCHIP_DECLARE(xilinx_intc_opb, "xlnx,opb-intc-1.00.c", xilinx_intc_of_init);
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