573 lines
13 KiB
C
573 lines
13 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2014 Texas Instruments Incorporated - https://www.ti.com/
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*/
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#define DSS_SUBSYS_NAME "PLL"
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#include <linux/delay.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/regulator/consumer.h>
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#include <linux/sched.h>
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#include "omapdss.h"
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#include "dss.h"
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#define PLL_CONTROL 0x0000
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#define PLL_STATUS 0x0004
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#define PLL_GO 0x0008
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#define PLL_CONFIGURATION1 0x000C
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#define PLL_CONFIGURATION2 0x0010
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#define PLL_CONFIGURATION3 0x0014
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#define PLL_SSC_CONFIGURATION1 0x0018
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#define PLL_SSC_CONFIGURATION2 0x001C
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#define PLL_CONFIGURATION4 0x0020
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int dss_pll_register(struct dss_device *dss, struct dss_pll *pll)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(dss->plls); ++i) {
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if (!dss->plls[i]) {
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dss->plls[i] = pll;
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pll->dss = dss;
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return 0;
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}
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}
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return -EBUSY;
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}
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void dss_pll_unregister(struct dss_pll *pll)
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{
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struct dss_device *dss = pll->dss;
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int i;
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for (i = 0; i < ARRAY_SIZE(dss->plls); ++i) {
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if (dss->plls[i] == pll) {
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dss->plls[i] = NULL;
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pll->dss = NULL;
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return;
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}
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}
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}
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struct dss_pll *dss_pll_find(struct dss_device *dss, const char *name)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(dss->plls); ++i) {
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if (dss->plls[i] && strcmp(dss->plls[i]->name, name) == 0)
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return dss->plls[i];
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}
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return NULL;
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}
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struct dss_pll *dss_pll_find_by_src(struct dss_device *dss,
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enum dss_clk_source src)
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{
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struct dss_pll *pll;
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switch (src) {
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default:
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case DSS_CLK_SRC_FCK:
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return NULL;
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case DSS_CLK_SRC_HDMI_PLL:
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return dss_pll_find(dss, "hdmi");
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case DSS_CLK_SRC_PLL1_1:
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case DSS_CLK_SRC_PLL1_2:
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case DSS_CLK_SRC_PLL1_3:
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pll = dss_pll_find(dss, "dsi0");
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if (!pll)
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pll = dss_pll_find(dss, "video0");
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return pll;
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case DSS_CLK_SRC_PLL2_1:
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case DSS_CLK_SRC_PLL2_2:
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case DSS_CLK_SRC_PLL2_3:
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pll = dss_pll_find(dss, "dsi1");
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if (!pll)
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pll = dss_pll_find(dss, "video1");
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return pll;
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}
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}
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unsigned int dss_pll_get_clkout_idx_for_src(enum dss_clk_source src)
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{
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switch (src) {
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case DSS_CLK_SRC_HDMI_PLL:
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return 0;
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case DSS_CLK_SRC_PLL1_1:
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case DSS_CLK_SRC_PLL2_1:
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return 0;
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case DSS_CLK_SRC_PLL1_2:
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case DSS_CLK_SRC_PLL2_2:
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return 1;
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case DSS_CLK_SRC_PLL1_3:
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case DSS_CLK_SRC_PLL2_3:
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return 2;
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default:
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return 0;
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}
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}
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int dss_pll_enable(struct dss_pll *pll)
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{
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int r;
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r = clk_prepare_enable(pll->clkin);
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if (r)
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return r;
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if (pll->regulator) {
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r = regulator_enable(pll->regulator);
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if (r)
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goto err_reg;
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}
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r = pll->ops->enable(pll);
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if (r)
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goto err_enable;
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return 0;
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err_enable:
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if (pll->regulator)
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regulator_disable(pll->regulator);
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err_reg:
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clk_disable_unprepare(pll->clkin);
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return r;
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}
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void dss_pll_disable(struct dss_pll *pll)
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{
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pll->ops->disable(pll);
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if (pll->regulator)
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regulator_disable(pll->regulator);
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clk_disable_unprepare(pll->clkin);
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memset(&pll->cinfo, 0, sizeof(pll->cinfo));
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}
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int dss_pll_set_config(struct dss_pll *pll, const struct dss_pll_clock_info *cinfo)
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{
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int r;
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r = pll->ops->set_config(pll, cinfo);
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if (r)
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return r;
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pll->cinfo = *cinfo;
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return 0;
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}
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bool dss_pll_hsdiv_calc_a(const struct dss_pll *pll, unsigned long clkdco,
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unsigned long out_min, unsigned long out_max,
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dss_hsdiv_calc_func func, void *data)
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{
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const struct dss_pll_hw *hw = pll->hw;
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int m, m_start, m_stop;
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unsigned long out;
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out_min = out_min ? out_min : 1;
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out_max = out_max ? out_max : ULONG_MAX;
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m_start = max(DIV_ROUND_UP(clkdco, out_max), 1ul);
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m_stop = min((unsigned)(clkdco / out_min), hw->mX_max);
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for (m = m_start; m <= m_stop; ++m) {
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out = clkdco / m;
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if (func(m, out, data))
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return true;
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}
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return false;
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}
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/*
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* clkdco = clkin / n * m * 2
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* clkoutX = clkdco / mX
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*/
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bool dss_pll_calc_a(const struct dss_pll *pll, unsigned long clkin,
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unsigned long pll_min, unsigned long pll_max,
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dss_pll_calc_func func, void *data)
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{
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const struct dss_pll_hw *hw = pll->hw;
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int n, n_start, n_stop, n_inc;
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int m, m_start, m_stop, m_inc;
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unsigned long fint, clkdco;
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unsigned long pll_hw_max;
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unsigned long fint_hw_min, fint_hw_max;
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pll_hw_max = hw->clkdco_max;
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fint_hw_min = hw->fint_min;
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fint_hw_max = hw->fint_max;
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n_start = max(DIV_ROUND_UP(clkin, fint_hw_max), 1ul);
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n_stop = min((unsigned)(clkin / fint_hw_min), hw->n_max);
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n_inc = 1;
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if (n_start > n_stop)
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return false;
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if (hw->errata_i886) {
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swap(n_start, n_stop);
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n_inc = -1;
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}
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pll_max = pll_max ? pll_max : ULONG_MAX;
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for (n = n_start; n != n_stop; n += n_inc) {
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fint = clkin / n;
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m_start = max(DIV_ROUND_UP(DIV_ROUND_UP(pll_min, fint), 2),
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1ul);
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m_stop = min3((unsigned)(pll_max / fint / 2),
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(unsigned)(pll_hw_max / fint / 2),
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hw->m_max);
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m_inc = 1;
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if (m_start > m_stop)
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continue;
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if (hw->errata_i886) {
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swap(m_start, m_stop);
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m_inc = -1;
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}
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for (m = m_start; m != m_stop; m += m_inc) {
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clkdco = 2 * m * fint;
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if (func(n, m, fint, clkdco, data))
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return true;
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}
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}
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return false;
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}
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/*
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* This calculates a PLL config that will provide the target_clkout rate
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* for clkout. Additionally clkdco rate will be the same as clkout rate
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* when clkout rate is >= min_clkdco.
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*
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* clkdco = clkin / n * m + clkin / n * mf / 262144
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* clkout = clkdco / m2
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*/
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bool dss_pll_calc_b(const struct dss_pll *pll, unsigned long clkin,
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unsigned long target_clkout, struct dss_pll_clock_info *cinfo)
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{
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unsigned long fint, clkdco, clkout;
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unsigned long target_clkdco;
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unsigned long min_dco;
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unsigned int n, m, mf, m2, sd;
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const struct dss_pll_hw *hw = pll->hw;
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DSSDBG("clkin %lu, target clkout %lu\n", clkin, target_clkout);
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/* Fint */
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n = DIV_ROUND_UP(clkin, hw->fint_max);
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fint = clkin / n;
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/* adjust m2 so that the clkdco will be high enough */
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min_dco = roundup(hw->clkdco_min, fint);
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m2 = DIV_ROUND_UP(min_dco, target_clkout);
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if (m2 == 0)
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m2 = 1;
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target_clkdco = target_clkout * m2;
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m = target_clkdco / fint;
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clkdco = fint * m;
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/* adjust clkdco with fractional mf */
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if (WARN_ON(target_clkdco - clkdco > fint))
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mf = 0;
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else
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mf = (u32)div_u64(262144ull * (target_clkdco - clkdco), fint);
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if (mf > 0)
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clkdco += (u32)div_u64((u64)mf * fint, 262144);
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clkout = clkdco / m2;
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/* sigma-delta */
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sd = DIV_ROUND_UP(fint * m, 250000000);
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DSSDBG("N = %u, M = %u, M.f = %u, M2 = %u, SD = %u\n",
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n, m, mf, m2, sd);
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DSSDBG("Fint %lu, clkdco %lu, clkout %lu\n", fint, clkdco, clkout);
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cinfo->n = n;
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cinfo->m = m;
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cinfo->mf = mf;
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cinfo->mX[0] = m2;
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cinfo->sd = sd;
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cinfo->fint = fint;
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cinfo->clkdco = clkdco;
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cinfo->clkout[0] = clkout;
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return true;
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}
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static int wait_for_bit_change(void __iomem *reg, int bitnum, int value)
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{
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unsigned long timeout;
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ktime_t wait;
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int t;
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/* first busyloop to see if the bit changes right away */
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t = 100;
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while (t-- > 0) {
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if (FLD_GET(readl_relaxed(reg), bitnum, bitnum) == value)
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return value;
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}
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/* then loop for 500ms, sleeping for 1ms in between */
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timeout = jiffies + msecs_to_jiffies(500);
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while (time_before(jiffies, timeout)) {
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if (FLD_GET(readl_relaxed(reg), bitnum, bitnum) == value)
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return value;
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wait = ns_to_ktime(1000 * 1000);
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set_current_state(TASK_UNINTERRUPTIBLE);
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schedule_hrtimeout(&wait, HRTIMER_MODE_REL);
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}
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return !value;
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}
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int dss_pll_wait_reset_done(struct dss_pll *pll)
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{
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void __iomem *base = pll->base;
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if (wait_for_bit_change(base + PLL_STATUS, 0, 1) != 1)
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return -ETIMEDOUT;
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else
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return 0;
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}
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static int dss_wait_hsdiv_ack(struct dss_pll *pll, u32 hsdiv_ack_mask)
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{
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int t = 100;
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while (t-- > 0) {
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u32 v = readl_relaxed(pll->base + PLL_STATUS);
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v &= hsdiv_ack_mask;
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if (v == hsdiv_ack_mask)
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return 0;
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}
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return -ETIMEDOUT;
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}
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static bool pll_is_locked(u32 stat)
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{
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/*
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* Required value for each bitfield listed below
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*
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* PLL_STATUS[6] = 0 PLL_BYPASS
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* PLL_STATUS[5] = 0 PLL_HIGHJITTER
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*
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* PLL_STATUS[3] = 0 PLL_LOSSREF
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* PLL_STATUS[2] = 0 PLL_RECAL
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* PLL_STATUS[1] = 1 PLL_LOCK
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* PLL_STATUS[0] = 1 PLL_CTRL_RESET_DONE
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*/
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return ((stat & 0x6f) == 0x3);
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}
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int dss_pll_write_config_type_a(struct dss_pll *pll,
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const struct dss_pll_clock_info *cinfo)
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{
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const struct dss_pll_hw *hw = pll->hw;
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void __iomem *base = pll->base;
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int r = 0;
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u32 l;
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l = 0;
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if (hw->has_stopmode)
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l = FLD_MOD(l, 1, 0, 0); /* PLL_STOPMODE */
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l = FLD_MOD(l, cinfo->n - 1, hw->n_msb, hw->n_lsb); /* PLL_REGN */
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l = FLD_MOD(l, cinfo->m, hw->m_msb, hw->m_lsb); /* PLL_REGM */
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/* M4 */
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l = FLD_MOD(l, cinfo->mX[0] ? cinfo->mX[0] - 1 : 0,
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hw->mX_msb[0], hw->mX_lsb[0]);
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/* M5 */
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l = FLD_MOD(l, cinfo->mX[1] ? cinfo->mX[1] - 1 : 0,
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hw->mX_msb[1], hw->mX_lsb[1]);
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writel_relaxed(l, base + PLL_CONFIGURATION1);
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l = 0;
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/* M6 */
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l = FLD_MOD(l, cinfo->mX[2] ? cinfo->mX[2] - 1 : 0,
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hw->mX_msb[2], hw->mX_lsb[2]);
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/* M7 */
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l = FLD_MOD(l, cinfo->mX[3] ? cinfo->mX[3] - 1 : 0,
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hw->mX_msb[3], hw->mX_lsb[3]);
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writel_relaxed(l, base + PLL_CONFIGURATION3);
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l = readl_relaxed(base + PLL_CONFIGURATION2);
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if (hw->has_freqsel) {
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u32 f = cinfo->fint < 1000000 ? 0x3 :
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cinfo->fint < 1250000 ? 0x4 :
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cinfo->fint < 1500000 ? 0x5 :
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cinfo->fint < 1750000 ? 0x6 :
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0x7;
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l = FLD_MOD(l, f, 4, 1); /* PLL_FREQSEL */
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} else if (hw->has_selfreqdco) {
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u32 f = cinfo->clkdco < hw->clkdco_low ? 0x2 : 0x4;
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l = FLD_MOD(l, f, 3, 1); /* PLL_SELFREQDCO */
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}
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l = FLD_MOD(l, 1, 13, 13); /* PLL_REFEN */
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l = FLD_MOD(l, 0, 14, 14); /* PHY_CLKINEN */
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l = FLD_MOD(l, 0, 16, 16); /* M4_CLOCK_EN */
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l = FLD_MOD(l, 0, 18, 18); /* M5_CLOCK_EN */
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l = FLD_MOD(l, 1, 20, 20); /* HSDIVBYPASS */
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if (hw->has_refsel)
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l = FLD_MOD(l, 3, 22, 21); /* REFSEL = sysclk */
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l = FLD_MOD(l, 0, 23, 23); /* M6_CLOCK_EN */
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l = FLD_MOD(l, 0, 25, 25); /* M7_CLOCK_EN */
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writel_relaxed(l, base + PLL_CONFIGURATION2);
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if (hw->errata_i932) {
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int cnt = 0;
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u32 sleep_time;
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const u32 max_lock_retries = 20;
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/*
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* Calculate wait time for PLL LOCK
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* 1000 REFCLK cycles in us.
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*/
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sleep_time = DIV_ROUND_UP(1000*1000*1000, cinfo->fint);
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for (cnt = 0; cnt < max_lock_retries; cnt++) {
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writel_relaxed(1, base + PLL_GO); /* PLL_GO */
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/**
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* read the register back to ensure the write is
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* flushed
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*/
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readl_relaxed(base + PLL_GO);
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usleep_range(sleep_time, sleep_time + 5);
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l = readl_relaxed(base + PLL_STATUS);
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if (pll_is_locked(l) &&
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!(readl_relaxed(base + PLL_GO) & 0x1))
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break;
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}
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if (cnt == max_lock_retries) {
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DSSERR("cannot lock PLL\n");
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r = -EIO;
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goto err;
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}
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} else {
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writel_relaxed(1, base + PLL_GO); /* PLL_GO */
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if (wait_for_bit_change(base + PLL_GO, 0, 0) != 0) {
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DSSERR("DSS DPLL GO bit not going down.\n");
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r = -EIO;
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goto err;
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}
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if (wait_for_bit_change(base + PLL_STATUS, 1, 1) != 1) {
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DSSERR("cannot lock DSS DPLL\n");
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r = -EIO;
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goto err;
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}
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}
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l = readl_relaxed(base + PLL_CONFIGURATION2);
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l = FLD_MOD(l, 1, 14, 14); /* PHY_CLKINEN */
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l = FLD_MOD(l, cinfo->mX[0] ? 1 : 0, 16, 16); /* M4_CLOCK_EN */
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l = FLD_MOD(l, cinfo->mX[1] ? 1 : 0, 18, 18); /* M5_CLOCK_EN */
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l = FLD_MOD(l, 0, 20, 20); /* HSDIVBYPASS */
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l = FLD_MOD(l, cinfo->mX[2] ? 1 : 0, 23, 23); /* M6_CLOCK_EN */
|
|
l = FLD_MOD(l, cinfo->mX[3] ? 1 : 0, 25, 25); /* M7_CLOCK_EN */
|
|
writel_relaxed(l, base + PLL_CONFIGURATION2);
|
|
|
|
r = dss_wait_hsdiv_ack(pll,
|
|
(cinfo->mX[0] ? BIT(7) : 0) |
|
|
(cinfo->mX[1] ? BIT(8) : 0) |
|
|
(cinfo->mX[2] ? BIT(10) : 0) |
|
|
(cinfo->mX[3] ? BIT(11) : 0));
|
|
if (r) {
|
|
DSSERR("failed to enable HSDIV clocks\n");
|
|
goto err;
|
|
}
|
|
|
|
err:
|
|
return r;
|
|
}
|
|
|
|
int dss_pll_write_config_type_b(struct dss_pll *pll,
|
|
const struct dss_pll_clock_info *cinfo)
|
|
{
|
|
const struct dss_pll_hw *hw = pll->hw;
|
|
void __iomem *base = pll->base;
|
|
u32 l;
|
|
|
|
l = 0;
|
|
l = FLD_MOD(l, cinfo->m, 20, 9); /* PLL_REGM */
|
|
l = FLD_MOD(l, cinfo->n - 1, 8, 1); /* PLL_REGN */
|
|
writel_relaxed(l, base + PLL_CONFIGURATION1);
|
|
|
|
l = readl_relaxed(base + PLL_CONFIGURATION2);
|
|
l = FLD_MOD(l, 0x0, 12, 12); /* PLL_HIGHFREQ divide by 2 */
|
|
l = FLD_MOD(l, 0x1, 13, 13); /* PLL_REFEN */
|
|
l = FLD_MOD(l, 0x0, 14, 14); /* PHY_CLKINEN */
|
|
if (hw->has_refsel)
|
|
l = FLD_MOD(l, 0x3, 22, 21); /* REFSEL = SYSCLK */
|
|
|
|
/* PLL_SELFREQDCO */
|
|
if (cinfo->clkdco > hw->clkdco_low)
|
|
l = FLD_MOD(l, 0x4, 3, 1);
|
|
else
|
|
l = FLD_MOD(l, 0x2, 3, 1);
|
|
writel_relaxed(l, base + PLL_CONFIGURATION2);
|
|
|
|
l = readl_relaxed(base + PLL_CONFIGURATION3);
|
|
l = FLD_MOD(l, cinfo->sd, 17, 10); /* PLL_REGSD */
|
|
writel_relaxed(l, base + PLL_CONFIGURATION3);
|
|
|
|
l = readl_relaxed(base + PLL_CONFIGURATION4);
|
|
l = FLD_MOD(l, cinfo->mX[0], 24, 18); /* PLL_REGM2 */
|
|
l = FLD_MOD(l, cinfo->mf, 17, 0); /* PLL_REGM_F */
|
|
writel_relaxed(l, base + PLL_CONFIGURATION4);
|
|
|
|
writel_relaxed(1, base + PLL_GO); /* PLL_GO */
|
|
|
|
if (wait_for_bit_change(base + PLL_GO, 0, 0) != 0) {
|
|
DSSERR("DSS DPLL GO bit not going down.\n");
|
|
return -EIO;
|
|
}
|
|
|
|
if (wait_for_bit_change(base + PLL_STATUS, 1, 1) != 1) {
|
|
DSSERR("cannot lock DSS DPLL\n");
|
|
return -ETIMEDOUT;
|
|
}
|
|
|
|
return 0;
|
|
}
|