121 lines
3.3 KiB
C
121 lines
3.3 KiB
C
/*
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* Copyright 2013 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Ben Skeggs <bskeggs@redhat.com>
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* Roy Spliet <rspliet@eclipso.eu>
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*/
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#include "priv.h"
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#include "ram.h"
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struct ramxlat {
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int id;
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u8 enc;
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};
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static inline int
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ramxlat(const struct ramxlat *xlat, int id)
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{
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while (xlat->id >= 0) {
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if (xlat->id == id)
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return xlat->enc;
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xlat++;
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}
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return -EINVAL;
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}
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static const struct ramxlat
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ramddr3_cl[] = {
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{ 5, 2 }, { 6, 4 }, { 7, 6 }, { 8, 8 }, { 9, 10 }, { 10, 12 },
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{ 11, 14 },
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/* the below are mentioned in some, but not all, ddr3 docs */
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{ 12, 1 }, { 13, 3 }, { 14, 5 },
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{ -1 }
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};
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static const struct ramxlat
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ramddr3_wr[] = {
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{ 5, 1 }, { 6, 2 }, { 7, 3 }, { 8, 4 }, { 10, 5 }, { 12, 6 },
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/* the below are mentioned in some, but not all, ddr3 docs */
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{ 14, 7 }, { 15, 7 }, { 16, 0 },
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{ -1 }
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};
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static const struct ramxlat
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ramddr3_cwl[] = {
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{ 5, 0 }, { 6, 1 }, { 7, 2 }, { 8, 3 },
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/* the below are mentioned in some, but not all, ddr3 docs */
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{ 9, 4 }, { 10, 5 },
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{ -1 }
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};
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int
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nvkm_sddr3_calc(struct nvkm_ram *ram)
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{
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int CWL, CL, WR, DLL = 0, ODT = 0;
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DLL = !ram->next->bios.ramcfg_DLLoff;
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switch (ram->next->bios.timing_ver) {
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case 0x10:
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if (ram->next->bios.timing_hdr < 0x17) {
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/* XXX: NV50: Get CWL from the timing register */
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return -ENOSYS;
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}
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CWL = ram->next->bios.timing_10_CWL;
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CL = ram->next->bios.timing_10_CL;
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WR = ram->next->bios.timing_10_WR;
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ODT = ram->next->bios.timing_10_ODT;
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break;
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case 0x20:
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CWL = (ram->next->bios.timing[1] & 0x00000f80) >> 7;
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CL = (ram->next->bios.timing[1] & 0x0000001f) >> 0;
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WR = (ram->next->bios.timing[2] & 0x007f0000) >> 16;
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/* XXX: Get these values from the VBIOS instead */
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ODT = (ram->mr[1] & 0x004) >> 2 |
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(ram->mr[1] & 0x040) >> 5 |
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(ram->mr[1] & 0x200) >> 7;
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break;
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default:
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return -ENOSYS;
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}
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CWL = ramxlat(ramddr3_cwl, CWL);
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CL = ramxlat(ramddr3_cl, CL);
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WR = ramxlat(ramddr3_wr, WR);
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if (CL < 0 || CWL < 0 || WR < 0)
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return -EINVAL;
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ram->mr[0] &= ~0xf74;
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ram->mr[0] |= (WR & 0x07) << 9;
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ram->mr[0] |= (CL & 0x0e) << 3;
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ram->mr[0] |= (CL & 0x01) << 2;
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ram->mr[1] &= ~0x245;
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ram->mr[1] |= (ODT & 0x1) << 2;
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ram->mr[1] |= (ODT & 0x2) << 5;
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ram->mr[1] |= (ODT & 0x4) << 7;
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ram->mr[1] |= !DLL;
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ram->mr[2] &= ~0x038;
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ram->mr[2] |= (CWL & 0x07) << 3;
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return 0;
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}
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