311 lines
9.0 KiB
C
311 lines
9.0 KiB
C
/*
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* Copyright 2013 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Ben Skeggs <bskeggs@redhat.com>
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*/
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#include "ctxgf100.h"
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#include <subdev/fb.h>
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#include <subdev/mc.h>
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/*******************************************************************************
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* PGRAPH context register lists
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******************************************************************************/
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static const struct gf100_gr_init
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gf117_grctx_init_ds_0[] = {
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{ 0x405800, 1, 0x04, 0x0f8000bf },
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{ 0x405830, 1, 0x04, 0x02180324 },
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{ 0x405834, 1, 0x04, 0x08000000 },
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{ 0x405838, 1, 0x04, 0x00000000 },
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{ 0x405854, 1, 0x04, 0x00000000 },
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{ 0x405870, 4, 0x04, 0x00000001 },
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{ 0x405a00, 2, 0x04, 0x00000000 },
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{ 0x405a18, 1, 0x04, 0x00000000 },
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{}
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};
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static const struct gf100_gr_init
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gf117_grctx_init_pd_0[] = {
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{ 0x406020, 1, 0x04, 0x000103c1 },
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{ 0x406028, 4, 0x04, 0x00000001 },
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{ 0x4064a8, 1, 0x04, 0x00000000 },
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{ 0x4064ac, 1, 0x04, 0x00003fff },
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{ 0x4064b4, 3, 0x04, 0x00000000 },
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{ 0x4064c0, 1, 0x04, 0x801a0078 },
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{ 0x4064c4, 1, 0x04, 0x00c9ffff },
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{ 0x4064d0, 8, 0x04, 0x00000000 },
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{}
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};
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static const struct gf100_gr_pack
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gf117_grctx_pack_hub[] = {
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{ gf100_grctx_init_main_0 },
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{ gf119_grctx_init_fe_0 },
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{ gf100_grctx_init_pri_0 },
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{ gf100_grctx_init_memfmt_0 },
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{ gf117_grctx_init_ds_0 },
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{ gf117_grctx_init_pd_0 },
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{ gf100_grctx_init_rstr2d_0 },
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{ gf100_grctx_init_scc_0 },
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{ gf119_grctx_init_be_0 },
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{}
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};
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static const struct gf100_gr_init
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gf117_grctx_init_setup_0[] = {
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{ 0x418800, 1, 0x04, 0x7006860a },
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{ 0x418808, 3, 0x04, 0x00000000 },
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{ 0x418828, 1, 0x04, 0x00008442 },
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{ 0x418830, 1, 0x04, 0x10000001 },
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{ 0x4188d8, 1, 0x04, 0x00000008 },
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{ 0x4188e0, 1, 0x04, 0x01000000 },
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{ 0x4188e8, 5, 0x04, 0x00000000 },
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{ 0x4188fc, 1, 0x04, 0x20100018 },
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{}
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};
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static const struct gf100_gr_pack
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gf117_grctx_pack_gpc_0[] = {
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{ gf100_grctx_init_gpc_unk_0 },
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{ gf119_grctx_init_prop_0 },
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{ gf119_grctx_init_gpc_unk_1 },
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{ gf117_grctx_init_setup_0 },
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{ gf100_grctx_init_zcull_0 },
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{}
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};
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const struct gf100_gr_pack
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gf117_grctx_pack_gpc_1[] = {
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{ gf119_grctx_init_crstr_0 },
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{ gf108_grctx_init_gpm_0 },
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{ gf100_grctx_init_gcc_0 },
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{}
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};
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const struct gf100_gr_init
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gf117_grctx_init_pe_0[] = {
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{ 0x419848, 1, 0x04, 0x00000000 },
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{ 0x419864, 1, 0x04, 0x00000129 },
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{ 0x419888, 1, 0x04, 0x00000000 },
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{}
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};
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static const struct gf100_gr_init
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gf117_grctx_init_tex_0[] = {
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{ 0x419a00, 1, 0x04, 0x000001f0 },
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{ 0x419a04, 1, 0x04, 0x00000001 },
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{ 0x419a08, 1, 0x04, 0x00000023 },
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{ 0x419a0c, 1, 0x04, 0x00020000 },
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{ 0x419a10, 1, 0x04, 0x00000000 },
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{ 0x419a14, 1, 0x04, 0x00000200 },
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{ 0x419a1c, 1, 0x04, 0x00008000 },
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{ 0x419a20, 1, 0x04, 0x00000800 },
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{ 0x419ac4, 1, 0x04, 0x0017f440 },
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{}
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};
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static const struct gf100_gr_init
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gf117_grctx_init_mpc_0[] = {
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{ 0x419c00, 1, 0x04, 0x0000000a },
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{ 0x419c04, 1, 0x04, 0x00000006 },
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{ 0x419c08, 1, 0x04, 0x00000002 },
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{ 0x419c20, 1, 0x04, 0x00000000 },
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{ 0x419c24, 1, 0x04, 0x00084210 },
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{ 0x419c28, 1, 0x04, 0x3efbefbe },
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{}
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};
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static const struct gf100_gr_pack
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gf117_grctx_pack_tpc[] = {
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{ gf117_grctx_init_pe_0 },
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{ gf117_grctx_init_tex_0 },
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{ gf117_grctx_init_mpc_0 },
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{ gf104_grctx_init_l1c_0 },
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{ gf119_grctx_init_sm_0 },
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{}
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};
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static const struct gf100_gr_init
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gf117_grctx_init_pes_0[] = {
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{ 0x41be24, 1, 0x04, 0x00000002 },
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{}
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};
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static const struct gf100_gr_init
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gf117_grctx_init_cbm_0[] = {
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{ 0x41bec0, 1, 0x04, 0x12180000 },
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{ 0x41bec4, 1, 0x04, 0x00003fff },
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{ 0x41bee4, 1, 0x04, 0x03240218 },
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{}
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};
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const struct gf100_gr_init
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gf117_grctx_init_wwdx_0[] = {
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{ 0x41bf00, 1, 0x04, 0x0a418820 },
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{ 0x41bf04, 1, 0x04, 0x062080e6 },
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{ 0x41bf08, 1, 0x04, 0x020398a4 },
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{ 0x41bf0c, 1, 0x04, 0x0e629062 },
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{ 0x41bf10, 1, 0x04, 0x0a418820 },
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{ 0x41bf14, 1, 0x04, 0x000000e6 },
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{ 0x41bfd0, 1, 0x04, 0x00900103 },
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{ 0x41bfe0, 1, 0x04, 0x00400001 },
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{ 0x41bfe4, 1, 0x04, 0x00000000 },
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{}
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};
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static const struct gf100_gr_pack
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gf117_grctx_pack_ppc[] = {
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{ gf117_grctx_init_pes_0 },
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{ gf117_grctx_init_cbm_0 },
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{ gf117_grctx_init_wwdx_0 },
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{}
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};
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/*******************************************************************************
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* PGRAPH context implementation
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******************************************************************************/
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void
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gf117_grctx_generate_dist_skip_table(struct gf100_gr *gr)
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{
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struct nvkm_device *device = gr->base.engine.subdev.device;
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int i;
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for (i = 0; i < 8; i++)
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nvkm_wr32(device, 0x4064d0 + (i * 0x04), 0x00000000);
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}
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void
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gf117_grctx_generate_rop_mapping(struct gf100_gr *gr)
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{
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struct nvkm_device *device = gr->base.engine.subdev.device;
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u32 data[6] = {}, data2[2] = {};
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u8 shift, ntpcv;
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int i;
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/* Pack tile map into register format. */
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for (i = 0; i < 32; i++)
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data[i / 6] |= (gr->tile[i] & 0x07) << ((i % 6) * 5);
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/* Magic. */
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shift = 0;
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ntpcv = gr->tpc_total;
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while (!(ntpcv & (1 << 4))) {
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ntpcv <<= 1;
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shift++;
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}
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data2[0] = (ntpcv << 16);
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data2[0] |= (shift << 21);
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data2[0] |= (((1 << (0 + 5)) % ntpcv) << 24);
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for (i = 1; i < 7; i++)
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data2[1] |= ((1 << (i + 5)) % ntpcv) << ((i - 1) * 5);
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/* GPC_BROADCAST */
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nvkm_wr32(device, 0x418bb8, (gr->tpc_total << 8) |
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gr->screen_tile_row_offset);
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for (i = 0; i < 6; i++)
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nvkm_wr32(device, 0x418b08 + (i * 4), data[i]);
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/* GPC_BROADCAST.TP_BROADCAST */
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nvkm_wr32(device, 0x41bfd0, (gr->tpc_total << 8) |
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gr->screen_tile_row_offset | data2[0]);
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nvkm_wr32(device, 0x41bfe4, data2[1]);
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for (i = 0; i < 6; i++)
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nvkm_wr32(device, 0x41bf00 + (i * 4), data[i]);
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/* UNK78xx */
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nvkm_wr32(device, 0x4078bc, (gr->tpc_total << 8) |
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gr->screen_tile_row_offset);
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for (i = 0; i < 6; i++)
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nvkm_wr32(device, 0x40780c + (i * 4), data[i]);
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}
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void
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gf117_grctx_generate_attrib(struct gf100_grctx *info)
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{
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struct gf100_gr *gr = info->gr;
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const struct gf100_grctx_func *grctx = gr->func->grctx;
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const u32 alpha = grctx->alpha_nr;
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const u32 beta = grctx->attrib_nr;
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const u32 size = 0x20 * (grctx->attrib_nr_max + grctx->alpha_nr_max);
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const int s = 12;
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const int b = mmio_vram(info, size * gr->tpc_total, (1 << s), false);
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const int timeslice_mode = 1;
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const int max_batches = 0xffff;
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u32 bo = 0;
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u32 ao = bo + grctx->attrib_nr_max * gr->tpc_total;
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int gpc, ppc;
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mmio_refn(info, 0x418810, 0x80000000, s, b);
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mmio_refn(info, 0x419848, 0x10000000, s, b);
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mmio_wr32(info, 0x405830, (beta << 16) | alpha);
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mmio_wr32(info, 0x4064c4, ((alpha / 4) << 16) | max_batches);
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for (gpc = 0; gpc < gr->gpc_nr; gpc++) {
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for (ppc = 0; ppc < gr->ppc_nr[gpc]; ppc++) {
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const u32 a = alpha * gr->ppc_tpc_nr[gpc][ppc];
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const u32 b = beta * gr->ppc_tpc_nr[gpc][ppc];
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const u32 t = timeslice_mode;
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const u32 o = PPC_UNIT(gpc, ppc, 0);
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if (!(gr->ppc_mask[gpc] & (1 << ppc)))
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continue;
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mmio_skip(info, o + 0xc0, (t << 28) | (b << 16) | ++bo);
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mmio_wr32(info, o + 0xc0, (t << 28) | (b << 16) | --bo);
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bo += grctx->attrib_nr_max * gr->ppc_tpc_nr[gpc][ppc];
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mmio_wr32(info, o + 0xe4, (a << 16) | ao);
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ao += grctx->alpha_nr_max * gr->ppc_tpc_nr[gpc][ppc];
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}
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}
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}
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const struct gf100_grctx_func
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gf117_grctx = {
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.main = gf100_grctx_generate_main,
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.unkn = gk104_grctx_generate_unkn,
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.hub = gf117_grctx_pack_hub,
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.gpc_0 = gf117_grctx_pack_gpc_0,
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.gpc_1 = gf117_grctx_pack_gpc_1,
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.zcull = gf100_grctx_pack_zcull,
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.tpc = gf117_grctx_pack_tpc,
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.ppc = gf117_grctx_pack_ppc,
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.icmd = gf119_grctx_pack_icmd,
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.mthd = gf119_grctx_pack_mthd,
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.bundle = gf100_grctx_generate_bundle,
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.bundle_size = 0x1800,
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.pagepool = gf100_grctx_generate_pagepool,
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.pagepool_size = 0x8000,
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.attrib = gf117_grctx_generate_attrib,
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.attrib_nr_max = 0x324,
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.attrib_nr = 0x218,
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.alpha_nr_max = 0x7ff,
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.alpha_nr = 0x324,
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.sm_id = gf100_grctx_generate_sm_id,
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.tpc_nr = gf100_grctx_generate_tpc_nr,
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.r4060a8 = gf100_grctx_generate_r4060a8,
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.rop_mapping = gf117_grctx_generate_rop_mapping,
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.alpha_beta_tables = gf100_grctx_generate_alpha_beta_tables,
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.max_ways_evict = gf100_grctx_generate_max_ways_evict,
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.dist_skip_table = gf117_grctx_generate_dist_skip_table,
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.r419cb8 = gf100_grctx_generate_r419cb8,
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};
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