135 lines
3.7 KiB
C
135 lines
3.7 KiB
C
/*
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* Copyright 2012 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Ben Skeggs
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*/
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#define nv04_dmaobj(p) container_of((p), struct nv04_dmaobj, base)
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#include "user.h"
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#include <core/gpuobj.h>
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#include <subdev/fb.h>
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#include <subdev/mmu/vmm.h>
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#include <nvif/class.h>
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struct nv04_dmaobj {
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struct nvkm_dmaobj base;
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bool clone;
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u32 flags0;
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u32 flags2;
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};
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static int
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nv04_dmaobj_bind(struct nvkm_dmaobj *base, struct nvkm_gpuobj *parent,
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int align, struct nvkm_gpuobj **pgpuobj)
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{
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struct nv04_dmaobj *dmaobj = nv04_dmaobj(base);
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struct nvkm_device *device = dmaobj->base.dma->engine.subdev.device;
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u64 offset = dmaobj->base.start & 0xfffff000;
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u64 adjust = dmaobj->base.start & 0x00000fff;
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u32 length = dmaobj->base.limit - dmaobj->base.start;
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int ret;
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if (dmaobj->clone) {
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struct nvkm_memory *pgt =
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device->mmu->vmm->pd->pt[0]->memory;
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if (!dmaobj->base.start)
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return nvkm_gpuobj_wrap(pgt, pgpuobj);
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nvkm_kmap(pgt);
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offset = nvkm_ro32(pgt, 8 + (offset >> 10));
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offset &= 0xfffff000;
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nvkm_done(pgt);
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}
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ret = nvkm_gpuobj_new(device, 16, align, false, parent, pgpuobj);
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if (ret == 0) {
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nvkm_kmap(*pgpuobj);
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nvkm_wo32(*pgpuobj, 0x00, dmaobj->flags0 | (adjust << 20));
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nvkm_wo32(*pgpuobj, 0x04, length);
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nvkm_wo32(*pgpuobj, 0x08, dmaobj->flags2 | offset);
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nvkm_wo32(*pgpuobj, 0x0c, dmaobj->flags2 | offset);
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nvkm_done(*pgpuobj);
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}
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return ret;
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}
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static const struct nvkm_dmaobj_func
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nv04_dmaobj_func = {
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.bind = nv04_dmaobj_bind,
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};
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int
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nv04_dmaobj_new(struct nvkm_dma *dma, const struct nvkm_oclass *oclass,
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void *data, u32 size, struct nvkm_dmaobj **pdmaobj)
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{
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struct nvkm_device *device = dma->engine.subdev.device;
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struct nv04_dmaobj *dmaobj;
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int ret;
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if (!(dmaobj = kzalloc(sizeof(*dmaobj), GFP_KERNEL)))
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return -ENOMEM;
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*pdmaobj = &dmaobj->base;
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ret = nvkm_dmaobj_ctor(&nv04_dmaobj_func, dma, oclass,
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&data, &size, &dmaobj->base);
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if (ret)
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return ret;
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if (dmaobj->base.target == NV_MEM_TARGET_VM) {
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if (device->mmu->func == &nv04_mmu)
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dmaobj->clone = true;
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dmaobj->base.target = NV_MEM_TARGET_PCI;
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dmaobj->base.access = NV_MEM_ACCESS_RW;
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}
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dmaobj->flags0 = oclass->base.oclass;
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switch (dmaobj->base.target) {
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case NV_MEM_TARGET_VRAM:
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dmaobj->flags0 |= 0x00003000;
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break;
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case NV_MEM_TARGET_PCI:
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dmaobj->flags0 |= 0x00023000;
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break;
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case NV_MEM_TARGET_PCI_NOSNOOP:
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dmaobj->flags0 |= 0x00033000;
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break;
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default:
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return -EINVAL;
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}
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switch (dmaobj->base.access) {
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case NV_MEM_ACCESS_RO:
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dmaobj->flags0 |= 0x00004000;
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break;
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case NV_MEM_ACCESS_WO:
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dmaobj->flags0 |= 0x00008000;
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fallthrough;
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case NV_MEM_ACCESS_RW:
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dmaobj->flags2 |= 0x00000002;
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break;
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default:
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return -EINVAL;
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}
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return 0;
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}
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