288 lines
7.0 KiB
C
288 lines
7.0 KiB
C
// SPDX-License-Identifier: MIT
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/*
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* Copyright © 2019 Intel Corporation
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*/
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#include "i915_drv.h"
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#include "i915_pci.h"
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#include "i915_reg.h"
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#include "intel_memory_region.h"
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#include "intel_pci_config.h"
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#include "intel_region_lmem.h"
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#include "intel_region_ttm.h"
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#include "gem/i915_gem_lmem.h"
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#include "gem/i915_gem_region.h"
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#include "gem/i915_gem_ttm.h"
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#include "gt/intel_gt.h"
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#include "gt/intel_gt_mcr.h"
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#include "gt/intel_gt_regs.h"
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#ifdef CONFIG_64BIT
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static void _release_bars(struct pci_dev *pdev)
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{
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int resno;
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for (resno = PCI_STD_RESOURCES; resno < PCI_STD_RESOURCE_END; resno++) {
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if (pci_resource_len(pdev, resno))
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pci_release_resource(pdev, resno);
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}
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}
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static void
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_resize_bar(struct drm_i915_private *i915, int resno, resource_size_t size)
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{
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struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
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int bar_size = pci_rebar_bytes_to_size(size);
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int ret;
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_release_bars(pdev);
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ret = pci_resize_resource(pdev, resno, bar_size);
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if (ret) {
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drm_info(&i915->drm, "Failed to resize BAR%d to %dM (%pe)\n",
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resno, 1 << bar_size, ERR_PTR(ret));
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return;
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}
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drm_info(&i915->drm, "BAR%d resized to %dM\n", resno, 1 << bar_size);
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}
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static void i915_resize_lmem_bar(struct drm_i915_private *i915, resource_size_t lmem_size)
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{
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struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
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struct pci_bus *root = pdev->bus;
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struct resource *root_res;
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resource_size_t rebar_size;
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resource_size_t current_size;
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u32 pci_cmd;
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int i;
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current_size = roundup_pow_of_two(pci_resource_len(pdev, GEN12_LMEM_BAR));
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if (i915->params.lmem_bar_size) {
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u32 bar_sizes;
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rebar_size = i915->params.lmem_bar_size *
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(resource_size_t)SZ_1M;
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bar_sizes = pci_rebar_get_possible_sizes(pdev, GEN12_LMEM_BAR);
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if (rebar_size == current_size)
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return;
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if (!(bar_sizes & BIT(pci_rebar_bytes_to_size(rebar_size))) ||
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rebar_size >= roundup_pow_of_two(lmem_size)) {
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rebar_size = lmem_size;
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drm_info(&i915->drm,
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"Given bar size is not within supported size, setting it to default: %llu\n",
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(u64)lmem_size >> 20);
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}
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} else {
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rebar_size = current_size;
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if (rebar_size != roundup_pow_of_two(lmem_size))
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rebar_size = lmem_size;
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else
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return;
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}
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/* Find out if root bus contains 64bit memory addressing */
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while (root->parent)
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root = root->parent;
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pci_bus_for_each_resource(root, root_res, i) {
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if (root_res && root_res->flags & (IORESOURCE_MEM | IORESOURCE_MEM_64) &&
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root_res->start > 0x100000000ull)
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break;
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}
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/* pci_resize_resource will fail anyways */
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if (!root_res) {
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drm_info(&i915->drm, "Can't resize LMEM BAR - platform support is missing\n");
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return;
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}
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/* First disable PCI memory decoding references */
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pci_read_config_dword(pdev, PCI_COMMAND, &pci_cmd);
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pci_write_config_dword(pdev, PCI_COMMAND,
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pci_cmd & ~PCI_COMMAND_MEMORY);
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_resize_bar(i915, GEN12_LMEM_BAR, rebar_size);
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pci_assign_unassigned_bus_resources(pdev->bus);
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pci_write_config_dword(pdev, PCI_COMMAND, pci_cmd);
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}
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#else
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static void i915_resize_lmem_bar(struct drm_i915_private *i915, resource_size_t lmem_size) {}
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#endif
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static int
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region_lmem_release(struct intel_memory_region *mem)
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{
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int ret;
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ret = intel_region_ttm_fini(mem);
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io_mapping_fini(&mem->iomap);
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return ret;
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}
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static int
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region_lmem_init(struct intel_memory_region *mem)
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{
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int ret;
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if (!io_mapping_init_wc(&mem->iomap,
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mem->io_start,
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mem->io_size))
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return -EIO;
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ret = intel_region_ttm_init(mem);
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if (ret)
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goto out_no_buddy;
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return 0;
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out_no_buddy:
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io_mapping_fini(&mem->iomap);
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return ret;
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}
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static const struct intel_memory_region_ops intel_region_lmem_ops = {
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.init = region_lmem_init,
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.release = region_lmem_release,
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.init_object = __i915_gem_ttm_object_init,
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};
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static bool get_legacy_lowmem_region(struct intel_uncore *uncore,
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u64 *start, u32 *size)
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{
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if (!IS_DG1_GRAPHICS_STEP(uncore->i915, STEP_A0, STEP_C0))
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return false;
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*start = 0;
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*size = SZ_1M;
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drm_dbg(&uncore->i915->drm, "LMEM: reserved legacy low-memory [0x%llx-0x%llx]\n",
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*start, *start + *size);
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return true;
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}
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static int reserve_lowmem_region(struct intel_uncore *uncore,
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struct intel_memory_region *mem)
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{
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u64 reserve_start;
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u32 reserve_size;
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int ret;
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if (!get_legacy_lowmem_region(uncore, &reserve_start, &reserve_size))
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return 0;
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ret = intel_memory_region_reserve(mem, reserve_start, reserve_size);
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if (ret)
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drm_err(&uncore->i915->drm, "LMEM: reserving low memory region failed\n");
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return ret;
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}
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static struct intel_memory_region *setup_lmem(struct intel_gt *gt)
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{
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struct drm_i915_private *i915 = gt->i915;
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struct intel_uncore *uncore = gt->uncore;
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struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
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struct intel_memory_region *mem;
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resource_size_t min_page_size;
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resource_size_t io_start;
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resource_size_t io_size;
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resource_size_t lmem_size;
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int err;
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if (!IS_DGFX(i915))
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return ERR_PTR(-ENODEV);
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if (!i915_pci_resource_valid(pdev, GEN12_LMEM_BAR))
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return ERR_PTR(-ENXIO);
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if (HAS_FLAT_CCS(i915)) {
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resource_size_t lmem_range;
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u64 tile_stolen, flat_ccs_base;
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lmem_range = intel_gt_mcr_read_any(&i915->gt0, XEHP_TILE0_ADDR_RANGE) & 0xFFFF;
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lmem_size = lmem_range >> XEHP_TILE_LMEM_RANGE_SHIFT;
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lmem_size *= SZ_1G;
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flat_ccs_base = intel_gt_mcr_read_any(gt, XEHP_FLAT_CCS_BASE_ADDR);
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flat_ccs_base = (flat_ccs_base >> XEHP_CCS_BASE_SHIFT) * SZ_64K;
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if (GEM_WARN_ON(lmem_size < flat_ccs_base))
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return ERR_PTR(-EIO);
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tile_stolen = lmem_size - flat_ccs_base;
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/* If the FLAT_CCS_BASE_ADDR register is not populated, flag an error */
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if (tile_stolen == lmem_size)
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drm_err(&i915->drm,
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"CCS_BASE_ADDR register did not have expected value\n");
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lmem_size -= tile_stolen;
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} else {
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/* Stolen starts from GSMBASE without CCS */
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lmem_size = intel_uncore_read64(&i915->uncore, GEN12_GSMBASE);
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}
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i915_resize_lmem_bar(i915, lmem_size);
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if (i915->params.lmem_size > 0) {
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lmem_size = min_t(resource_size_t, lmem_size,
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mul_u32_u32(i915->params.lmem_size, SZ_1M));
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}
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io_start = pci_resource_start(pdev, GEN12_LMEM_BAR);
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io_size = min(pci_resource_len(pdev, GEN12_LMEM_BAR), lmem_size);
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if (!io_size)
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return ERR_PTR(-EIO);
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min_page_size = HAS_64K_PAGES(i915) ? I915_GTT_PAGE_SIZE_64K :
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I915_GTT_PAGE_SIZE_4K;
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mem = intel_memory_region_create(i915,
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0,
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lmem_size,
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min_page_size,
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io_start,
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io_size,
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INTEL_MEMORY_LOCAL,
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0,
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&intel_region_lmem_ops);
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if (IS_ERR(mem))
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return mem;
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err = reserve_lowmem_region(uncore, mem);
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if (err)
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goto err_region_put;
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drm_dbg(&i915->drm, "Local memory: %pR\n", &mem->region);
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drm_dbg(&i915->drm, "Local memory IO start: %pa\n",
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&mem->io_start);
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drm_info(&i915->drm, "Local memory IO size: %pa\n",
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&mem->io_size);
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drm_info(&i915->drm, "Local memory available: %pa\n",
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&lmem_size);
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if (io_size < lmem_size)
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drm_info(&i915->drm, "Using a reduced BAR size of %lluMiB. Consider enabling 'Resizable BAR' or similar, if available in the BIOS.\n",
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(u64)io_size >> 20);
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return mem;
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err_region_put:
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intel_memory_region_destroy(mem);
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return ERR_PTR(err);
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}
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struct intel_memory_region *intel_gt_setup_lmem(struct intel_gt *gt)
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{
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return setup_lmem(gt);
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}
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