299 lines
8.1 KiB
C
299 lines
8.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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#ifndef __ASPEED_HACE_H__
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#define __ASPEED_HACE_H__
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#include <linux/interrupt.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/fips.h>
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#include <linux/dma-mapping.h>
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#include <crypto/aes.h>
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#include <crypto/des.h>
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#include <crypto/scatterwalk.h>
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#include <crypto/internal/aead.h>
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#include <crypto/internal/akcipher.h>
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#include <crypto/internal/des.h>
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#include <crypto/internal/hash.h>
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#include <crypto/internal/kpp.h>
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#include <crypto/internal/skcipher.h>
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#include <crypto/algapi.h>
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#include <crypto/engine.h>
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#include <crypto/hmac.h>
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#include <crypto/sha1.h>
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#include <crypto/sha2.h>
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/*****************************
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* *
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* HACE register definitions *
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* *
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* ***************************/
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#define ASPEED_HACE_SRC 0x00 /* Crypto Data Source Base Address Register */
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#define ASPEED_HACE_DEST 0x04 /* Crypto Data Destination Base Address Register */
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#define ASPEED_HACE_CONTEXT 0x08 /* Crypto Context Buffer Base Address Register */
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#define ASPEED_HACE_DATA_LEN 0x0C /* Crypto Data Length Register */
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#define ASPEED_HACE_CMD 0x10 /* Crypto Engine Command Register */
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/* G5 */
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#define ASPEED_HACE_TAG 0x18 /* HACE Tag Register */
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/* G6 */
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#define ASPEED_HACE_GCM_ADD_LEN 0x14 /* Crypto AES-GCM Additional Data Length Register */
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#define ASPEED_HACE_GCM_TAG_BASE_ADDR 0x18 /* Crypto AES-GCM Tag Write Buff Base Address Reg */
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#define ASPEED_HACE_STS 0x1C /* HACE Status Register */
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#define ASPEED_HACE_HASH_SRC 0x20 /* Hash Data Source Base Address Register */
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#define ASPEED_HACE_HASH_DIGEST_BUFF 0x24 /* Hash Digest Write Buffer Base Address Register */
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#define ASPEED_HACE_HASH_KEY_BUFF 0x28 /* Hash HMAC Key Buffer Base Address Register */
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#define ASPEED_HACE_HASH_DATA_LEN 0x2C /* Hash Data Length Register */
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#define ASPEED_HACE_HASH_CMD 0x30 /* Hash Engine Command Register */
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/* crypto cmd */
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#define HACE_CMD_SINGLE_DES 0
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#define HACE_CMD_TRIPLE_DES BIT(17)
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#define HACE_CMD_AES_SELECT 0
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#define HACE_CMD_DES_SELECT BIT(16)
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#define HACE_CMD_ISR_EN BIT(12)
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#define HACE_CMD_CONTEXT_SAVE_ENABLE (0)
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#define HACE_CMD_CONTEXT_SAVE_DISABLE BIT(9)
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#define HACE_CMD_AES (0)
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#define HACE_CMD_DES (0)
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#define HACE_CMD_RC4 BIT(8)
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#define HACE_CMD_DECRYPT (0)
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#define HACE_CMD_ENCRYPT BIT(7)
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#define HACE_CMD_ECB (0x0 << 4)
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#define HACE_CMD_CBC (0x1 << 4)
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#define HACE_CMD_CFB (0x2 << 4)
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#define HACE_CMD_OFB (0x3 << 4)
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#define HACE_CMD_CTR (0x4 << 4)
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#define HACE_CMD_OP_MODE_MASK (0x7 << 4)
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#define HACE_CMD_AES128 (0x0 << 2)
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#define HACE_CMD_AES192 (0x1 << 2)
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#define HACE_CMD_AES256 (0x2 << 2)
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#define HACE_CMD_OP_CASCADE (0x3)
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#define HACE_CMD_OP_INDEPENDENT (0x1)
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/* G5 */
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#define HACE_CMD_RI_WO_DATA_ENABLE (0)
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#define HACE_CMD_RI_WO_DATA_DISABLE BIT(11)
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#define HACE_CMD_CONTEXT_LOAD_ENABLE (0)
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#define HACE_CMD_CONTEXT_LOAD_DISABLE BIT(10)
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/* G6 */
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#define HACE_CMD_AES_KEY_FROM_OTP BIT(24)
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#define HACE_CMD_GHASH_TAG_XOR_EN BIT(23)
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#define HACE_CMD_GHASH_PAD_LEN_INV BIT(22)
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#define HACE_CMD_GCM_TAG_ADDR_SEL BIT(21)
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#define HACE_CMD_MBUS_REQ_SYNC_EN BIT(20)
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#define HACE_CMD_DES_SG_CTRL BIT(19)
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#define HACE_CMD_SRC_SG_CTRL BIT(18)
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#define HACE_CMD_CTR_IV_AES_96 (0x1 << 14)
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#define HACE_CMD_CTR_IV_DES_32 (0x1 << 14)
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#define HACE_CMD_CTR_IV_AES_64 (0x2 << 14)
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#define HACE_CMD_CTR_IV_AES_32 (0x3 << 14)
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#define HACE_CMD_AES_KEY_HW_EXP BIT(13)
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#define HACE_CMD_GCM (0x5 << 4)
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/* interrupt status reg */
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#define HACE_CRYPTO_ISR BIT(12)
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#define HACE_HASH_ISR BIT(9)
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#define HACE_HASH_BUSY BIT(0)
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/* hash cmd reg */
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#define HASH_CMD_MBUS_REQ_SYNC_EN BIT(20)
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#define HASH_CMD_HASH_SRC_SG_CTRL BIT(18)
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#define HASH_CMD_SHA512_224 (0x3 << 10)
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#define HASH_CMD_SHA512_256 (0x2 << 10)
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#define HASH_CMD_SHA384 (0x1 << 10)
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#define HASH_CMD_SHA512 (0)
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#define HASH_CMD_INT_ENABLE BIT(9)
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#define HASH_CMD_HMAC (0x1 << 7)
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#define HASH_CMD_ACC_MODE (0x2 << 7)
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#define HASH_CMD_HMAC_KEY (0x3 << 7)
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#define HASH_CMD_SHA1 (0x2 << 4)
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#define HASH_CMD_SHA224 (0x4 << 4)
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#define HASH_CMD_SHA256 (0x5 << 4)
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#define HASH_CMD_SHA512_SER (0x6 << 4)
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#define HASH_CMD_SHA_SWAP (0x2 << 2)
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#define HASH_SG_LAST_LIST BIT(31)
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#define CRYPTO_FLAGS_BUSY BIT(1)
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#define SHA_OP_UPDATE 1
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#define SHA_OP_FINAL 2
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#define SHA_FLAGS_SHA1 BIT(0)
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#define SHA_FLAGS_SHA224 BIT(1)
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#define SHA_FLAGS_SHA256 BIT(2)
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#define SHA_FLAGS_SHA384 BIT(3)
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#define SHA_FLAGS_SHA512 BIT(4)
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#define SHA_FLAGS_SHA512_224 BIT(5)
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#define SHA_FLAGS_SHA512_256 BIT(6)
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#define SHA_FLAGS_HMAC BIT(8)
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#define SHA_FLAGS_FINUP BIT(9)
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#define SHA_FLAGS_MASK (0xff)
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#define ASPEED_CRYPTO_SRC_DMA_BUF_LEN 0xa000
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#define ASPEED_CRYPTO_DST_DMA_BUF_LEN 0xa000
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#define ASPEED_CRYPTO_GCM_TAG_OFFSET 0x9ff0
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#define ASPEED_HASH_SRC_DMA_BUF_LEN 0xa000
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#define ASPEED_HASH_QUEUE_LENGTH 50
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#define HACE_CMD_IV_REQUIRE (HACE_CMD_CBC | HACE_CMD_CFB | \
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HACE_CMD_OFB | HACE_CMD_CTR)
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struct aspeed_hace_dev;
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typedef int (*aspeed_hace_fn_t)(struct aspeed_hace_dev *);
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struct aspeed_sg_list {
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__le32 len;
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__le32 phy_addr;
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};
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struct aspeed_engine_hash {
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struct tasklet_struct done_task;
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unsigned long flags;
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struct ahash_request *req;
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/* input buffer */
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void *ahash_src_addr;
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dma_addr_t ahash_src_dma_addr;
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dma_addr_t src_dma;
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dma_addr_t digest_dma;
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size_t src_length;
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/* callback func */
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aspeed_hace_fn_t resume;
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aspeed_hace_fn_t dma_prepare;
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};
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struct aspeed_sha_hmac_ctx {
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struct crypto_shash *shash;
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u8 ipad[SHA512_BLOCK_SIZE];
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u8 opad[SHA512_BLOCK_SIZE];
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};
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struct aspeed_sham_ctx {
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struct crypto_engine_ctx enginectx;
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struct aspeed_hace_dev *hace_dev;
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unsigned long flags; /* hmac flag */
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struct aspeed_sha_hmac_ctx base[0];
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};
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struct aspeed_sham_reqctx {
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unsigned long flags; /* final update flag should no use*/
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unsigned long op; /* final or update */
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u32 cmd; /* trigger cmd */
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/* walk state */
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struct scatterlist *src_sg;
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int src_nents;
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unsigned int offset; /* offset in current sg */
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unsigned int total; /* per update length */
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size_t digsize;
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size_t block_size;
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size_t ivsize;
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const __be32 *sha_iv;
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/* remain data buffer */
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u8 buffer[SHA512_BLOCK_SIZE * 2];
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dma_addr_t buffer_dma_addr;
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size_t bufcnt; /* buffer counter */
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/* output buffer */
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u8 digest[SHA512_DIGEST_SIZE] __aligned(64);
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dma_addr_t digest_dma_addr;
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u64 digcnt[2];
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};
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struct aspeed_engine_crypto {
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struct tasklet_struct done_task;
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unsigned long flags;
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struct skcipher_request *req;
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/* context buffer */
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void *cipher_ctx;
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dma_addr_t cipher_ctx_dma;
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/* input buffer, could be single/scatter-gather lists */
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void *cipher_addr;
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dma_addr_t cipher_dma_addr;
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/* output buffer, only used in scatter-gather lists */
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void *dst_sg_addr;
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dma_addr_t dst_sg_dma_addr;
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/* callback func */
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aspeed_hace_fn_t resume;
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};
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struct aspeed_cipher_ctx {
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struct crypto_engine_ctx enginectx;
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struct aspeed_hace_dev *hace_dev;
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int key_len;
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u8 key[AES_MAX_KEYLENGTH];
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/* callback func */
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aspeed_hace_fn_t start;
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struct crypto_skcipher *fallback_tfm;
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};
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struct aspeed_cipher_reqctx {
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int enc_cmd;
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int src_nents;
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int dst_nents;
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struct skcipher_request fallback_req; /* keep at the end */
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};
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struct aspeed_hace_dev {
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void __iomem *regs;
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struct device *dev;
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int irq;
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struct clk *clk;
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unsigned long version;
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struct crypto_engine *crypt_engine_hash;
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struct crypto_engine *crypt_engine_crypto;
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struct aspeed_engine_hash hash_engine;
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struct aspeed_engine_crypto crypto_engine;
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};
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struct aspeed_hace_alg {
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struct aspeed_hace_dev *hace_dev;
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const char *alg_base;
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union {
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struct skcipher_alg skcipher;
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struct ahash_alg ahash;
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} alg;
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};
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enum aspeed_version {
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AST2500_VERSION = 5,
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AST2600_VERSION
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};
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#define ast_hace_write(hace, val, offset) \
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writel((val), (hace)->regs + (offset))
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#define ast_hace_read(hace, offset) \
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readl((hace)->regs + (offset))
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void aspeed_register_hace_hash_algs(struct aspeed_hace_dev *hace_dev);
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void aspeed_unregister_hace_hash_algs(struct aspeed_hace_dev *hace_dev);
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void aspeed_register_hace_crypto_algs(struct aspeed_hace_dev *hace_dev);
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void aspeed_unregister_hace_crypto_algs(struct aspeed_hace_dev *hace_dev);
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#endif
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