1001 lines
25 KiB
C
1001 lines
25 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* PLL clock driver for TI Davinci SoCs
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*
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* Copyright (C) 2018 David Lechner <david@lechnology.com>
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*
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* Based on arch/arm/mach-davinci/clock.c
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* Copyright (C) 2006-2007 Texas Instruments.
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* Copyright (C) 2008-2009 Deep Root Systems, LLC
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*/
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#include <linux/clk-provider.h>
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#include <linux/clk.h>
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#include <linux/clk/davinci.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/mfd/syscon.h>
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#include <linux/notifier.h>
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#include <linux/of_address.h>
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#include <linux/of_device.h>
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#include <linux/of.h>
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#include <linux/platform_data/clk-davinci-pll.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include <linux/slab.h>
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#include <linux/types.h>
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#include "pll.h"
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#define MAX_NAME_SIZE 20
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#define OSCIN_CLK_NAME "oscin"
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#define REVID 0x000
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#define PLLCTL 0x100
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#define OCSEL 0x104
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#define PLLSECCTL 0x108
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#define PLLM 0x110
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#define PREDIV 0x114
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#define PLLDIV1 0x118
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#define PLLDIV2 0x11c
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#define PLLDIV3 0x120
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#define OSCDIV 0x124
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#define POSTDIV 0x128
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#define BPDIV 0x12c
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#define PLLCMD 0x138
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#define PLLSTAT 0x13c
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#define ALNCTL 0x140
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#define DCHANGE 0x144
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#define CKEN 0x148
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#define CKSTAT 0x14c
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#define SYSTAT 0x150
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#define PLLDIV4 0x160
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#define PLLDIV5 0x164
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#define PLLDIV6 0x168
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#define PLLDIV7 0x16c
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#define PLLDIV8 0x170
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#define PLLDIV9 0x174
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#define PLLCTL_PLLEN BIT(0)
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#define PLLCTL_PLLPWRDN BIT(1)
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#define PLLCTL_PLLRST BIT(3)
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#define PLLCTL_PLLDIS BIT(4)
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#define PLLCTL_PLLENSRC BIT(5)
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#define PLLCTL_CLKMODE BIT(8)
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/* shared by most *DIV registers */
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#define DIV_RATIO_SHIFT 0
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#define DIV_RATIO_WIDTH 5
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#define DIV_ENABLE_SHIFT 15
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#define PLLCMD_GOSET BIT(0)
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#define PLLSTAT_GOSTAT BIT(0)
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#define CKEN_OBSCLK_SHIFT 1
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#define CKEN_AUXEN_SHIFT 0
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/*
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* OMAP-L138 system reference guide recommends a wait for 4 OSCIN/CLKIN
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* cycles to ensure that the PLLC has switched to bypass mode. Delay of 1us
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* ensures we are good for all > 4MHz OSCIN/CLKIN inputs. Typically the input
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* is ~25MHz. Units are micro seconds.
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*/
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#define PLL_BYPASS_TIME 1
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/* From OMAP-L138 datasheet table 6-4. Units are micro seconds */
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#define PLL_RESET_TIME 1
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/*
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* From OMAP-L138 datasheet table 6-4; assuming prediv = 1, sqrt(pllm) = 4
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* Units are micro seconds.
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*/
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#define PLL_LOCK_TIME 20
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/**
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* struct davinci_pll_clk - Main PLL clock (aka PLLOUT)
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* @hw: clk_hw for the pll
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* @base: Base memory address
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* @pllm_min: The minimum allowable PLLM[PLLM] value
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* @pllm_max: The maximum allowable PLLM[PLLM] value
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* @pllm_mask: Bitmask for PLLM[PLLM] value
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*/
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struct davinci_pll_clk {
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struct clk_hw hw;
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void __iomem *base;
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u32 pllm_min;
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u32 pllm_max;
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u32 pllm_mask;
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};
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#define to_davinci_pll_clk(_hw) \
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container_of((_hw), struct davinci_pll_clk, hw)
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static unsigned long davinci_pll_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct davinci_pll_clk *pll = to_davinci_pll_clk(hw);
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unsigned long rate = parent_rate;
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u32 mult;
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mult = readl(pll->base + PLLM) & pll->pllm_mask;
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rate *= mult + 1;
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return rate;
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}
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static int davinci_pll_determine_rate(struct clk_hw *hw,
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struct clk_rate_request *req)
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{
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struct davinci_pll_clk *pll = to_davinci_pll_clk(hw);
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struct clk_hw *parent = req->best_parent_hw;
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unsigned long parent_rate = req->best_parent_rate;
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unsigned long rate = req->rate;
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unsigned long best_rate, r;
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u32 mult;
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/* there is a limited range of valid outputs (see datasheet) */
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if (rate < req->min_rate)
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return -EINVAL;
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rate = min(rate, req->max_rate);
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mult = rate / parent_rate;
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best_rate = parent_rate * mult;
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/* easy case when there is no PREDIV */
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if (!(clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT)) {
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if (best_rate < req->min_rate)
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return -EINVAL;
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if (mult < pll->pllm_min || mult > pll->pllm_max)
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return -EINVAL;
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req->rate = best_rate;
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return 0;
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}
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/* see if the PREDIV clock can help us */
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best_rate = 0;
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for (mult = pll->pllm_min; mult <= pll->pllm_max; mult++) {
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parent_rate = clk_hw_round_rate(parent, rate / mult);
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r = parent_rate * mult;
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if (r < req->min_rate)
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continue;
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if (r > rate || r > req->max_rate)
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break;
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if (r > best_rate) {
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best_rate = r;
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req->rate = best_rate;
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req->best_parent_rate = parent_rate;
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if (best_rate == rate)
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break;
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}
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}
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return 0;
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}
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static int davinci_pll_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct davinci_pll_clk *pll = to_davinci_pll_clk(hw);
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u32 mult;
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mult = rate / parent_rate;
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writel(mult - 1, pll->base + PLLM);
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return 0;
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}
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#ifdef CONFIG_DEBUG_FS
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static void davinci_pll_debug_init(struct clk_hw *hw, struct dentry *dentry);
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#else
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#define davinci_pll_debug_init NULL
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#endif
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static const struct clk_ops davinci_pll_ops = {
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.recalc_rate = davinci_pll_recalc_rate,
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.determine_rate = davinci_pll_determine_rate,
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.set_rate = davinci_pll_set_rate,
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.debug_init = davinci_pll_debug_init,
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};
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/* PLLM works differently on DM365 */
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static unsigned long dm365_pll_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct davinci_pll_clk *pll = to_davinci_pll_clk(hw);
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unsigned long rate = parent_rate;
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u32 mult;
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mult = readl(pll->base + PLLM) & pll->pllm_mask;
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rate *= mult * 2;
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return rate;
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}
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static const struct clk_ops dm365_pll_ops = {
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.recalc_rate = dm365_pll_recalc_rate,
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.debug_init = davinci_pll_debug_init,
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};
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/**
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* davinci_pll_div_register - common *DIV clock implementation
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* @dev: The PLL platform device or NULL
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* @name: the clock name
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* @parent_name: the parent clock name
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* @reg: the *DIV register
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* @fixed: if true, the divider is a fixed value
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* @flags: bitmap of CLK_* flags from clock-provider.h
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*/
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static struct clk *davinci_pll_div_register(struct device *dev,
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const char *name,
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const char *parent_name,
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void __iomem *reg,
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bool fixed, u32 flags)
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{
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const char * const *parent_names = parent_name ? &parent_name : NULL;
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int num_parents = parent_name ? 1 : 0;
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const struct clk_ops *divider_ops = &clk_divider_ops;
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struct clk_gate *gate;
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struct clk_divider *divider;
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struct clk *clk;
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int ret;
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gate = kzalloc(sizeof(*gate), GFP_KERNEL);
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if (!gate)
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return ERR_PTR(-ENOMEM);
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gate->reg = reg;
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gate->bit_idx = DIV_ENABLE_SHIFT;
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divider = kzalloc(sizeof(*divider), GFP_KERNEL);
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if (!divider) {
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ret = -ENOMEM;
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goto err_free_gate;
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}
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divider->reg = reg;
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divider->shift = DIV_RATIO_SHIFT;
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divider->width = DIV_RATIO_WIDTH;
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if (fixed) {
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divider->flags |= CLK_DIVIDER_READ_ONLY;
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divider_ops = &clk_divider_ro_ops;
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}
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clk = clk_register_composite(dev, name, parent_names, num_parents,
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NULL, NULL, ÷r->hw, divider_ops,
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&gate->hw, &clk_gate_ops, flags);
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if (IS_ERR(clk)) {
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ret = PTR_ERR(clk);
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goto err_free_divider;
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}
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return clk;
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err_free_divider:
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kfree(divider);
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err_free_gate:
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kfree(gate);
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return ERR_PTR(ret);
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}
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struct davinci_pllen_clk {
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struct clk_hw hw;
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void __iomem *base;
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};
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#define to_davinci_pllen_clk(_hw) \
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container_of((_hw), struct davinci_pllen_clk, hw)
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static const struct clk_ops davinci_pllen_ops = {
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/* this clocks just uses the clock notification feature */
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};
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/*
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* The PLL has to be switched into bypass mode while we are chaning the rate,
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* so we do that on the PLLEN clock since it is the end of the line. This will
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* switch to bypass before any of the parent clocks (PREDIV, PLL, POSTDIV) are
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* changed and will switch back to the PLL after the changes have been made.
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*/
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static int davinci_pllen_rate_change(struct notifier_block *nb,
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unsigned long flags, void *data)
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{
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struct clk_notifier_data *cnd = data;
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struct clk_hw *hw = __clk_get_hw(cnd->clk);
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struct davinci_pllen_clk *pll = to_davinci_pllen_clk(hw);
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u32 ctrl;
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ctrl = readl(pll->base + PLLCTL);
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if (flags == PRE_RATE_CHANGE) {
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/* Switch the PLL to bypass mode */
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ctrl &= ~(PLLCTL_PLLENSRC | PLLCTL_PLLEN);
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writel(ctrl, pll->base + PLLCTL);
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udelay(PLL_BYPASS_TIME);
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/* Reset and enable PLL */
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ctrl &= ~(PLLCTL_PLLRST | PLLCTL_PLLDIS);
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writel(ctrl, pll->base + PLLCTL);
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} else {
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udelay(PLL_RESET_TIME);
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/* Bring PLL out of reset */
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ctrl |= PLLCTL_PLLRST;
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writel(ctrl, pll->base + PLLCTL);
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udelay(PLL_LOCK_TIME);
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/* Remove PLL from bypass mode */
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ctrl |= PLLCTL_PLLEN;
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writel(ctrl, pll->base + PLLCTL);
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}
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return NOTIFY_OK;
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}
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static struct notifier_block davinci_pllen_notifier = {
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.notifier_call = davinci_pllen_rate_change,
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};
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/**
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* davinci_pll_clk_register - Register a PLL clock
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* @dev: The PLL platform device or NULL
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* @info: The device-specific clock info
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* @parent_name: The parent clock name
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* @base: The PLL's memory region
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* @cfgchip: CFGCHIP syscon regmap for info->unlock_reg or NULL
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*
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* This creates a series of clocks that represent the PLL.
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*
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* OSCIN > [PREDIV >] PLL > [POSTDIV >] PLLEN
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*
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* - OSCIN is the parent clock (on secondary PLL, may come from primary PLL)
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* - PREDIV and POSTDIV are optional (depends on the PLL controller)
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* - PLL is the PLL output (aka PLLOUT)
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* - PLLEN is the bypass multiplexer
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*
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* Returns: The PLLOUT clock or a negative error code.
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*/
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struct clk *davinci_pll_clk_register(struct device *dev,
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const struct davinci_pll_clk_info *info,
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const char *parent_name,
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void __iomem *base,
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struct regmap *cfgchip)
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{
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char prediv_name[MAX_NAME_SIZE];
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char pllout_name[MAX_NAME_SIZE];
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char postdiv_name[MAX_NAME_SIZE];
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char pllen_name[MAX_NAME_SIZE];
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struct clk_init_data init;
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struct davinci_pll_clk *pllout;
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struct davinci_pllen_clk *pllen;
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struct clk *oscin_clk = NULL;
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struct clk *prediv_clk = NULL;
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struct clk *pllout_clk;
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struct clk *postdiv_clk = NULL;
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struct clk *pllen_clk;
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int ret;
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if (info->flags & PLL_HAS_CLKMODE) {
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/*
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* If a PLL has PLLCTL[CLKMODE], then it is the primary PLL.
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* We register a clock named "oscin" that serves as the internal
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* "input clock" domain shared by both PLLs (if there are 2)
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* and will be the parent clock to the AUXCLK, SYSCLKBP and
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* OBSCLK domains. NB: The various TRMs use "OSCIN" to mean
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* a number of different things. In this driver we use it to
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* mean the signal after the PLLCTL[CLKMODE] switch.
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*/
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oscin_clk = clk_register_fixed_factor(dev, OSCIN_CLK_NAME,
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parent_name, 0, 1, 1);
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if (IS_ERR(oscin_clk))
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return oscin_clk;
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parent_name = OSCIN_CLK_NAME;
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}
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if (info->flags & PLL_HAS_PREDIV) {
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bool fixed = info->flags & PLL_PREDIV_FIXED_DIV;
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u32 flags = 0;
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snprintf(prediv_name, MAX_NAME_SIZE, "%s_prediv", info->name);
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if (info->flags & PLL_PREDIV_ALWAYS_ENABLED)
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flags |= CLK_IS_CRITICAL;
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/* Some? DM355 chips don't correctly report the PREDIV value */
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if (info->flags & PLL_PREDIV_FIXED8)
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prediv_clk = clk_register_fixed_factor(dev, prediv_name,
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parent_name, flags, 1, 8);
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else
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prediv_clk = davinci_pll_div_register(dev, prediv_name,
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parent_name, base + PREDIV, fixed, flags);
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if (IS_ERR(prediv_clk)) {
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ret = PTR_ERR(prediv_clk);
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goto err_unregister_oscin;
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}
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parent_name = prediv_name;
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}
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/* Unlock writing to PLL registers */
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if (info->unlock_reg) {
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if (IS_ERR_OR_NULL(cfgchip))
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dev_warn(dev, "Failed to get CFGCHIP (%ld)\n",
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PTR_ERR(cfgchip));
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else
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regmap_write_bits(cfgchip, info->unlock_reg,
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info->unlock_mask, 0);
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}
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pllout = kzalloc(sizeof(*pllout), GFP_KERNEL);
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if (!pllout) {
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ret = -ENOMEM;
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goto err_unregister_prediv;
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}
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snprintf(pllout_name, MAX_NAME_SIZE, "%s_pllout", info->name);
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init.name = pllout_name;
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if (info->flags & PLL_PLLM_2X)
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init.ops = &dm365_pll_ops;
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else
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init.ops = &davinci_pll_ops;
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init.parent_names = &parent_name;
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init.num_parents = 1;
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init.flags = 0;
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if (info->flags & PLL_HAS_PREDIV)
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init.flags |= CLK_SET_RATE_PARENT;
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pllout->hw.init = &init;
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pllout->base = base;
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pllout->pllm_mask = info->pllm_mask;
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pllout->pllm_min = info->pllm_min;
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pllout->pllm_max = info->pllm_max;
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pllout_clk = clk_register(dev, &pllout->hw);
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if (IS_ERR(pllout_clk)) {
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ret = PTR_ERR(pllout_clk);
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goto err_free_pllout;
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}
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clk_hw_set_rate_range(&pllout->hw, info->pllout_min_rate,
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info->pllout_max_rate);
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parent_name = pllout_name;
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if (info->flags & PLL_HAS_POSTDIV) {
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bool fixed = info->flags & PLL_POSTDIV_FIXED_DIV;
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u32 flags = CLK_SET_RATE_PARENT;
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snprintf(postdiv_name, MAX_NAME_SIZE, "%s_postdiv", info->name);
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if (info->flags & PLL_POSTDIV_ALWAYS_ENABLED)
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flags |= CLK_IS_CRITICAL;
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postdiv_clk = davinci_pll_div_register(dev, postdiv_name,
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parent_name, base + POSTDIV, fixed, flags);
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if (IS_ERR(postdiv_clk)) {
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ret = PTR_ERR(postdiv_clk);
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goto err_unregister_pllout;
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}
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parent_name = postdiv_name;
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}
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pllen = kzalloc(sizeof(*pllen), GFP_KERNEL);
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if (!pllen) {
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ret = -ENOMEM;
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goto err_unregister_postdiv;
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}
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snprintf(pllen_name, MAX_NAME_SIZE, "%s_pllen", info->name);
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init.name = pllen_name;
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init.ops = &davinci_pllen_ops;
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init.parent_names = &parent_name;
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init.num_parents = 1;
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init.flags = CLK_SET_RATE_PARENT;
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|
|
pllen->hw.init = &init;
|
|
pllen->base = base;
|
|
|
|
pllen_clk = clk_register(dev, &pllen->hw);
|
|
if (IS_ERR(pllen_clk)) {
|
|
ret = PTR_ERR(pllen_clk);
|
|
goto err_free_pllen;
|
|
}
|
|
|
|
clk_notifier_register(pllen_clk, &davinci_pllen_notifier);
|
|
|
|
return pllout_clk;
|
|
|
|
err_free_pllen:
|
|
kfree(pllen);
|
|
err_unregister_postdiv:
|
|
clk_unregister(postdiv_clk);
|
|
err_unregister_pllout:
|
|
clk_unregister(pllout_clk);
|
|
err_free_pllout:
|
|
kfree(pllout);
|
|
err_unregister_prediv:
|
|
clk_unregister(prediv_clk);
|
|
err_unregister_oscin:
|
|
clk_unregister(oscin_clk);
|
|
|
|
return ERR_PTR(ret);
|
|
}
|
|
|
|
/**
|
|
* davinci_pll_auxclk_register - Register bypass clock (AUXCLK)
|
|
* @dev: The PLL platform device or NULL
|
|
* @name: The clock name
|
|
* @base: The PLL memory region
|
|
*/
|
|
struct clk *davinci_pll_auxclk_register(struct device *dev,
|
|
const char *name,
|
|
void __iomem *base)
|
|
{
|
|
return clk_register_gate(dev, name, OSCIN_CLK_NAME, 0, base + CKEN,
|
|
CKEN_AUXEN_SHIFT, 0, NULL);
|
|
}
|
|
|
|
/**
|
|
* davinci_pll_sysclkbp_clk_register - Register bypass divider clock (SYSCLKBP)
|
|
* @dev: The PLL platform device or NULL
|
|
* @name: The clock name
|
|
* @base: The PLL memory region
|
|
*/
|
|
struct clk *davinci_pll_sysclkbp_clk_register(struct device *dev,
|
|
const char *name,
|
|
void __iomem *base)
|
|
{
|
|
return clk_register_divider(dev, name, OSCIN_CLK_NAME, 0, base + BPDIV,
|
|
DIV_RATIO_SHIFT, DIV_RATIO_WIDTH,
|
|
CLK_DIVIDER_READ_ONLY, NULL);
|
|
}
|
|
|
|
/**
|
|
* davinci_pll_obsclk_register - Register oscillator divider clock (OBSCLK)
|
|
* @dev: The PLL platform device or NULL
|
|
* @info: The clock info
|
|
* @base: The PLL memory region
|
|
*/
|
|
struct clk *
|
|
davinci_pll_obsclk_register(struct device *dev,
|
|
const struct davinci_pll_obsclk_info *info,
|
|
void __iomem *base)
|
|
{
|
|
struct clk_mux *mux;
|
|
struct clk_gate *gate;
|
|
struct clk_divider *divider;
|
|
struct clk *clk;
|
|
u32 oscdiv;
|
|
int ret;
|
|
|
|
mux = kzalloc(sizeof(*mux), GFP_KERNEL);
|
|
if (!mux)
|
|
return ERR_PTR(-ENOMEM);
|
|
|
|
mux->reg = base + OCSEL;
|
|
mux->table = info->table;
|
|
mux->mask = info->ocsrc_mask;
|
|
|
|
gate = kzalloc(sizeof(*gate), GFP_KERNEL);
|
|
if (!gate) {
|
|
ret = -ENOMEM;
|
|
goto err_free_mux;
|
|
}
|
|
|
|
gate->reg = base + CKEN;
|
|
gate->bit_idx = CKEN_OBSCLK_SHIFT;
|
|
|
|
divider = kzalloc(sizeof(*divider), GFP_KERNEL);
|
|
if (!divider) {
|
|
ret = -ENOMEM;
|
|
goto err_free_gate;
|
|
}
|
|
|
|
divider->reg = base + OSCDIV;
|
|
divider->shift = DIV_RATIO_SHIFT;
|
|
divider->width = DIV_RATIO_WIDTH;
|
|
|
|
/* make sure divider is enabled just in case bootloader disabled it */
|
|
oscdiv = readl(base + OSCDIV);
|
|
oscdiv |= BIT(DIV_ENABLE_SHIFT);
|
|
writel(oscdiv, base + OSCDIV);
|
|
|
|
clk = clk_register_composite(dev, info->name, info->parent_names,
|
|
info->num_parents,
|
|
&mux->hw, &clk_mux_ops,
|
|
÷r->hw, &clk_divider_ops,
|
|
&gate->hw, &clk_gate_ops, 0);
|
|
|
|
if (IS_ERR(clk)) {
|
|
ret = PTR_ERR(clk);
|
|
goto err_free_divider;
|
|
}
|
|
|
|
return clk;
|
|
|
|
err_free_divider:
|
|
kfree(divider);
|
|
err_free_gate:
|
|
kfree(gate);
|
|
err_free_mux:
|
|
kfree(mux);
|
|
|
|
return ERR_PTR(ret);
|
|
}
|
|
|
|
/* The PLL SYSCLKn clocks have a mechanism for synchronizing rate changes. */
|
|
static int davinci_pll_sysclk_rate_change(struct notifier_block *nb,
|
|
unsigned long flags, void *data)
|
|
{
|
|
struct clk_notifier_data *cnd = data;
|
|
struct clk_hw *hw = __clk_get_hw(clk_get_parent(cnd->clk));
|
|
struct davinci_pllen_clk *pll = to_davinci_pllen_clk(hw);
|
|
u32 pllcmd, pllstat;
|
|
|
|
switch (flags) {
|
|
case POST_RATE_CHANGE:
|
|
/* apply the changes */
|
|
pllcmd = readl(pll->base + PLLCMD);
|
|
pllcmd |= PLLCMD_GOSET;
|
|
writel(pllcmd, pll->base + PLLCMD);
|
|
fallthrough;
|
|
case PRE_RATE_CHANGE:
|
|
/* Wait until for outstanding changes to take effect */
|
|
do {
|
|
pllstat = readl(pll->base + PLLSTAT);
|
|
} while (pllstat & PLLSTAT_GOSTAT);
|
|
break;
|
|
}
|
|
|
|
return NOTIFY_OK;
|
|
}
|
|
|
|
static struct notifier_block davinci_pll_sysclk_notifier = {
|
|
.notifier_call = davinci_pll_sysclk_rate_change,
|
|
};
|
|
|
|
/**
|
|
* davinci_pll_sysclk_register - Register divider clocks (SYSCLKn)
|
|
* @dev: The PLL platform device or NULL
|
|
* @info: The clock info
|
|
* @base: The PLL memory region
|
|
*/
|
|
struct clk *
|
|
davinci_pll_sysclk_register(struct device *dev,
|
|
const struct davinci_pll_sysclk_info *info,
|
|
void __iomem *base)
|
|
{
|
|
const struct clk_ops *divider_ops = &clk_divider_ops;
|
|
struct clk_gate *gate;
|
|
struct clk_divider *divider;
|
|
struct clk *clk;
|
|
u32 reg;
|
|
u32 flags = 0;
|
|
int ret;
|
|
|
|
/* PLLDIVn registers are not entirely consecutive */
|
|
if (info->id < 4)
|
|
reg = PLLDIV1 + 4 * (info->id - 1);
|
|
else
|
|
reg = PLLDIV4 + 4 * (info->id - 4);
|
|
|
|
gate = kzalloc(sizeof(*gate), GFP_KERNEL);
|
|
if (!gate)
|
|
return ERR_PTR(-ENOMEM);
|
|
|
|
gate->reg = base + reg;
|
|
gate->bit_idx = DIV_ENABLE_SHIFT;
|
|
|
|
divider = kzalloc(sizeof(*divider), GFP_KERNEL);
|
|
if (!divider) {
|
|
ret = -ENOMEM;
|
|
goto err_free_gate;
|
|
}
|
|
|
|
divider->reg = base + reg;
|
|
divider->shift = DIV_RATIO_SHIFT;
|
|
divider->width = info->ratio_width;
|
|
divider->flags = 0;
|
|
|
|
if (info->flags & SYSCLK_FIXED_DIV) {
|
|
divider->flags |= CLK_DIVIDER_READ_ONLY;
|
|
divider_ops = &clk_divider_ro_ops;
|
|
}
|
|
|
|
/* Only the ARM clock can change the parent PLL rate */
|
|
if (info->flags & SYSCLK_ARM_RATE)
|
|
flags |= CLK_SET_RATE_PARENT;
|
|
|
|
if (info->flags & SYSCLK_ALWAYS_ENABLED)
|
|
flags |= CLK_IS_CRITICAL;
|
|
|
|
clk = clk_register_composite(dev, info->name, &info->parent_name, 1,
|
|
NULL, NULL, ÷r->hw, divider_ops,
|
|
&gate->hw, &clk_gate_ops, flags);
|
|
if (IS_ERR(clk)) {
|
|
ret = PTR_ERR(clk);
|
|
goto err_free_divider;
|
|
}
|
|
|
|
clk_notifier_register(clk, &davinci_pll_sysclk_notifier);
|
|
|
|
return clk;
|
|
|
|
err_free_divider:
|
|
kfree(divider);
|
|
err_free_gate:
|
|
kfree(gate);
|
|
|
|
return ERR_PTR(ret);
|
|
}
|
|
|
|
int of_davinci_pll_init(struct device *dev, struct device_node *node,
|
|
const struct davinci_pll_clk_info *info,
|
|
const struct davinci_pll_obsclk_info *obsclk_info,
|
|
const struct davinci_pll_sysclk_info **div_info,
|
|
u8 max_sysclk_id,
|
|
void __iomem *base,
|
|
struct regmap *cfgchip)
|
|
{
|
|
struct device_node *child;
|
|
const char *parent_name;
|
|
struct clk *clk;
|
|
|
|
if (info->flags & PLL_HAS_CLKMODE)
|
|
parent_name = of_clk_get_parent_name(node, 0);
|
|
else
|
|
parent_name = OSCIN_CLK_NAME;
|
|
|
|
clk = davinci_pll_clk_register(dev, info, parent_name, base, cfgchip);
|
|
if (IS_ERR(clk)) {
|
|
dev_err(dev, "failed to register %s\n", info->name);
|
|
return PTR_ERR(clk);
|
|
}
|
|
|
|
child = of_get_child_by_name(node, "pllout");
|
|
if (of_device_is_available(child))
|
|
of_clk_add_provider(child, of_clk_src_simple_get, clk);
|
|
of_node_put(child);
|
|
|
|
child = of_get_child_by_name(node, "sysclk");
|
|
if (of_device_is_available(child)) {
|
|
struct clk_onecell_data *clk_data;
|
|
struct clk **clks;
|
|
int n_clks = max_sysclk_id + 1;
|
|
int i;
|
|
|
|
clk_data = kzalloc(sizeof(*clk_data), GFP_KERNEL);
|
|
if (!clk_data) {
|
|
of_node_put(child);
|
|
return -ENOMEM;
|
|
}
|
|
|
|
clks = kmalloc_array(n_clks, sizeof(*clks), GFP_KERNEL);
|
|
if (!clks) {
|
|
kfree(clk_data);
|
|
of_node_put(child);
|
|
return -ENOMEM;
|
|
}
|
|
|
|
clk_data->clks = clks;
|
|
clk_data->clk_num = n_clks;
|
|
|
|
for (i = 0; i < n_clks; i++)
|
|
clks[i] = ERR_PTR(-ENOENT);
|
|
|
|
for (; *div_info; div_info++) {
|
|
clk = davinci_pll_sysclk_register(dev, *div_info, base);
|
|
if (IS_ERR(clk))
|
|
dev_warn(dev, "failed to register %s (%ld)\n",
|
|
(*div_info)->name, PTR_ERR(clk));
|
|
else
|
|
clks[(*div_info)->id] = clk;
|
|
}
|
|
of_clk_add_provider(child, of_clk_src_onecell_get, clk_data);
|
|
}
|
|
of_node_put(child);
|
|
|
|
child = of_get_child_by_name(node, "auxclk");
|
|
if (of_device_is_available(child)) {
|
|
char child_name[MAX_NAME_SIZE];
|
|
|
|
snprintf(child_name, MAX_NAME_SIZE, "%s_auxclk", info->name);
|
|
|
|
clk = davinci_pll_auxclk_register(dev, child_name, base);
|
|
if (IS_ERR(clk))
|
|
dev_warn(dev, "failed to register %s (%ld)\n",
|
|
child_name, PTR_ERR(clk));
|
|
else
|
|
of_clk_add_provider(child, of_clk_src_simple_get, clk);
|
|
}
|
|
of_node_put(child);
|
|
|
|
child = of_get_child_by_name(node, "obsclk");
|
|
if (of_device_is_available(child)) {
|
|
if (obsclk_info)
|
|
clk = davinci_pll_obsclk_register(dev, obsclk_info, base);
|
|
else
|
|
clk = ERR_PTR(-EINVAL);
|
|
|
|
if (IS_ERR(clk))
|
|
dev_warn(dev, "failed to register obsclk (%ld)\n",
|
|
PTR_ERR(clk));
|
|
else
|
|
of_clk_add_provider(child, of_clk_src_simple_get, clk);
|
|
}
|
|
of_node_put(child);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct davinci_pll_platform_data *davinci_pll_get_pdata(struct device *dev)
|
|
{
|
|
struct davinci_pll_platform_data *pdata = dev_get_platdata(dev);
|
|
|
|
/*
|
|
* Platform data is optional, so allocate a new struct if one was not
|
|
* provided. For device tree, this will always be the case.
|
|
*/
|
|
if (!pdata)
|
|
pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
|
|
if (!pdata)
|
|
return NULL;
|
|
|
|
/* for device tree, we need to fill in the struct */
|
|
if (dev->of_node)
|
|
pdata->cfgchip =
|
|
syscon_regmap_lookup_by_compatible("ti,da830-cfgchip");
|
|
|
|
return pdata;
|
|
}
|
|
|
|
/* needed in early boot for clocksource/clockevent */
|
|
#ifdef CONFIG_ARCH_DAVINCI_DA850
|
|
CLK_OF_DECLARE(da850_pll0, "ti,da850-pll0", of_da850_pll0_init);
|
|
#endif
|
|
|
|
static const struct of_device_id davinci_pll_of_match[] = {
|
|
#ifdef CONFIG_ARCH_DAVINCI_DA850
|
|
{ .compatible = "ti,da850-pll1", .data = of_da850_pll1_init },
|
|
#endif
|
|
{ }
|
|
};
|
|
|
|
static const struct platform_device_id davinci_pll_id_table[] = {
|
|
#ifdef CONFIG_ARCH_DAVINCI_DA830
|
|
{ .name = "da830-pll", .driver_data = (kernel_ulong_t)da830_pll_init },
|
|
#endif
|
|
#ifdef CONFIG_ARCH_DAVINCI_DA850
|
|
{ .name = "da850-pll0", .driver_data = (kernel_ulong_t)da850_pll0_init },
|
|
{ .name = "da850-pll1", .driver_data = (kernel_ulong_t)da850_pll1_init },
|
|
#endif
|
|
#ifdef CONFIG_ARCH_DAVINCI_DM355
|
|
{ .name = "dm355-pll1", .driver_data = (kernel_ulong_t)dm355_pll1_init },
|
|
{ .name = "dm355-pll2", .driver_data = (kernel_ulong_t)dm355_pll2_init },
|
|
#endif
|
|
#ifdef CONFIG_ARCH_DAVINCI_DM365
|
|
{ .name = "dm365-pll1", .driver_data = (kernel_ulong_t)dm365_pll1_init },
|
|
{ .name = "dm365-pll2", .driver_data = (kernel_ulong_t)dm365_pll2_init },
|
|
#endif
|
|
{ }
|
|
};
|
|
|
|
typedef int (*davinci_pll_init)(struct device *dev, void __iomem *base,
|
|
struct regmap *cfgchip);
|
|
|
|
static int davinci_pll_probe(struct platform_device *pdev)
|
|
{
|
|
struct device *dev = &pdev->dev;
|
|
struct davinci_pll_platform_data *pdata;
|
|
const struct of_device_id *of_id;
|
|
davinci_pll_init pll_init = NULL;
|
|
void __iomem *base;
|
|
|
|
of_id = of_match_device(davinci_pll_of_match, dev);
|
|
if (of_id)
|
|
pll_init = of_id->data;
|
|
else if (pdev->id_entry)
|
|
pll_init = (void *)pdev->id_entry->driver_data;
|
|
|
|
if (!pll_init) {
|
|
dev_err(dev, "unable to find driver data\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
pdata = davinci_pll_get_pdata(dev);
|
|
if (!pdata) {
|
|
dev_err(dev, "missing platform data\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
base = devm_platform_ioremap_resource(pdev, 0);
|
|
if (IS_ERR(base))
|
|
return PTR_ERR(base);
|
|
|
|
return pll_init(dev, base, pdata->cfgchip);
|
|
}
|
|
|
|
static struct platform_driver davinci_pll_driver = {
|
|
.probe = davinci_pll_probe,
|
|
.driver = {
|
|
.name = "davinci-pll-clk",
|
|
.of_match_table = davinci_pll_of_match,
|
|
},
|
|
.id_table = davinci_pll_id_table,
|
|
};
|
|
|
|
static int __init davinci_pll_driver_init(void)
|
|
{
|
|
return platform_driver_register(&davinci_pll_driver);
|
|
}
|
|
|
|
/* has to be postcore_initcall because PSC devices depend on PLL parent clocks */
|
|
postcore_initcall(davinci_pll_driver_init);
|
|
|
|
#ifdef CONFIG_DEBUG_FS
|
|
#include <linux/debugfs.h>
|
|
|
|
#define DEBUG_REG(n) \
|
|
{ \
|
|
.name = #n, \
|
|
.offset = n, \
|
|
}
|
|
|
|
static const struct debugfs_reg32 davinci_pll_regs[] = {
|
|
DEBUG_REG(REVID),
|
|
DEBUG_REG(PLLCTL),
|
|
DEBUG_REG(OCSEL),
|
|
DEBUG_REG(PLLSECCTL),
|
|
DEBUG_REG(PLLM),
|
|
DEBUG_REG(PREDIV),
|
|
DEBUG_REG(PLLDIV1),
|
|
DEBUG_REG(PLLDIV2),
|
|
DEBUG_REG(PLLDIV3),
|
|
DEBUG_REG(OSCDIV),
|
|
DEBUG_REG(POSTDIV),
|
|
DEBUG_REG(BPDIV),
|
|
DEBUG_REG(PLLCMD),
|
|
DEBUG_REG(PLLSTAT),
|
|
DEBUG_REG(ALNCTL),
|
|
DEBUG_REG(DCHANGE),
|
|
DEBUG_REG(CKEN),
|
|
DEBUG_REG(CKSTAT),
|
|
DEBUG_REG(SYSTAT),
|
|
DEBUG_REG(PLLDIV4),
|
|
DEBUG_REG(PLLDIV5),
|
|
DEBUG_REG(PLLDIV6),
|
|
DEBUG_REG(PLLDIV7),
|
|
DEBUG_REG(PLLDIV8),
|
|
DEBUG_REG(PLLDIV9),
|
|
};
|
|
|
|
static void davinci_pll_debug_init(struct clk_hw *hw, struct dentry *dentry)
|
|
{
|
|
struct davinci_pll_clk *pll = to_davinci_pll_clk(hw);
|
|
struct debugfs_regset32 *regset;
|
|
|
|
regset = kzalloc(sizeof(*regset), GFP_KERNEL);
|
|
if (!regset)
|
|
return;
|
|
|
|
regset->regs = davinci_pll_regs;
|
|
regset->nregs = ARRAY_SIZE(davinci_pll_regs);
|
|
regset->base = pll->base;
|
|
|
|
debugfs_create_regset32("registers", 0400, dentry, regset);
|
|
}
|
|
#endif
|