267 lines
6.9 KiB
C
267 lines
6.9 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2012 Regents of the University of California
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*/
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#include <linux/cpu.h>
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#include <linux/init.h>
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#include <linux/seq_file.h>
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#include <linux/of.h>
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#include <asm/csr.h>
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#include <asm/hwcap.h>
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#include <asm/sbi.h>
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#include <asm/smp.h>
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#include <asm/pgtable.h>
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/*
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* Returns the hart ID of the given device tree node, or -ENODEV if the node
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* isn't an enabled and valid RISC-V hart node.
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*/
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int riscv_of_processor_hartid(struct device_node *node, unsigned long *hart)
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{
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const char *isa;
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if (!of_device_is_compatible(node, "riscv")) {
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pr_warn("Found incompatible CPU\n");
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return -ENODEV;
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}
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*hart = (unsigned long) of_get_cpu_hwid(node, 0);
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if (*hart == ~0UL) {
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pr_warn("Found CPU without hart ID\n");
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return -ENODEV;
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}
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if (!of_device_is_available(node)) {
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pr_info("CPU with hartid=%lu is not available\n", *hart);
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return -ENODEV;
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}
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if (of_property_read_string(node, "riscv,isa", &isa)) {
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pr_warn("CPU with hartid=%lu has no \"riscv,isa\" property\n", *hart);
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return -ENODEV;
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}
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if (isa[0] != 'r' || isa[1] != 'v') {
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pr_warn("CPU with hartid=%lu has an invalid ISA of \"%s\"\n", *hart, isa);
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return -ENODEV;
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}
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return 0;
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}
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/*
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* Find hart ID of the CPU DT node under which given DT node falls.
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*
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* To achieve this, we walk up the DT tree until we find an active
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* RISC-V core (HART) node and extract the cpuid from it.
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*/
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int riscv_of_parent_hartid(struct device_node *node, unsigned long *hartid)
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{
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int rc;
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for (; node; node = node->parent) {
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if (of_device_is_compatible(node, "riscv")) {
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rc = riscv_of_processor_hartid(node, hartid);
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if (!rc)
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return 0;
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}
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}
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return -1;
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}
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#ifdef CONFIG_PROC_FS
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struct riscv_cpuinfo {
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unsigned long mvendorid;
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unsigned long marchid;
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unsigned long mimpid;
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};
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static DEFINE_PER_CPU(struct riscv_cpuinfo, riscv_cpuinfo);
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static int riscv_cpuinfo_starting(unsigned int cpu)
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{
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struct riscv_cpuinfo *ci = this_cpu_ptr(&riscv_cpuinfo);
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#if IS_ENABLED(CONFIG_RISCV_SBI)
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ci->mvendorid = sbi_spec_is_0_1() ? 0 : sbi_get_mvendorid();
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ci->marchid = sbi_spec_is_0_1() ? 0 : sbi_get_marchid();
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ci->mimpid = sbi_spec_is_0_1() ? 0 : sbi_get_mimpid();
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#elif IS_ENABLED(CONFIG_RISCV_M_MODE)
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ci->mvendorid = csr_read(CSR_MVENDORID);
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ci->marchid = csr_read(CSR_MARCHID);
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ci->mimpid = csr_read(CSR_MIMPID);
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#else
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ci->mvendorid = 0;
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ci->marchid = 0;
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ci->mimpid = 0;
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#endif
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return 0;
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}
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static int __init riscv_cpuinfo_init(void)
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{
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int ret;
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ret = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "riscv/cpuinfo:starting",
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riscv_cpuinfo_starting, NULL);
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if (ret < 0) {
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pr_err("cpuinfo: failed to register hotplug callbacks.\n");
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return ret;
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}
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return 0;
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}
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device_initcall(riscv_cpuinfo_init);
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#define __RISCV_ISA_EXT_DATA(UPROP, EXTID) \
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{ \
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.uprop = #UPROP, \
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.isa_ext_id = EXTID, \
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}
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/*
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* Here are the ordering rules of extension naming defined by RISC-V
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* specification :
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* 1. All extensions should be separated from other multi-letter extensions
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* by an underscore.
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* 2. The first letter following the 'Z' conventionally indicates the most
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* closely related alphabetical extension category, IMAFDQLCBKJTPVH.
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* If multiple 'Z' extensions are named, they should be ordered first
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* by category, then alphabetically within a category.
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* 3. Standard supervisor-level extensions (starts with 'S') should be
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* listed after standard unprivileged extensions. If multiple
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* supervisor-level extensions are listed, they should be ordered
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* alphabetically.
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* 4. Non-standard extensions (starts with 'X') must be listed after all
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* standard extensions. They must be separated from other multi-letter
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* extensions by an underscore.
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*/
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static struct riscv_isa_ext_data isa_ext_arr[] = {
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__RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF),
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__RISCV_ISA_EXT_DATA(sstc, RISCV_ISA_EXT_SSTC),
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__RISCV_ISA_EXT_DATA(svinval, RISCV_ISA_EXT_SVINVAL),
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__RISCV_ISA_EXT_DATA(svpbmt, RISCV_ISA_EXT_SVPBMT),
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__RISCV_ISA_EXT_DATA(zicbom, RISCV_ISA_EXT_ZICBOM),
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__RISCV_ISA_EXT_DATA(zihintpause, RISCV_ISA_EXT_ZIHINTPAUSE),
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__RISCV_ISA_EXT_DATA("", RISCV_ISA_EXT_MAX),
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};
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static void print_isa_ext(struct seq_file *f)
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{
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struct riscv_isa_ext_data *edata;
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int i = 0, arr_sz;
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arr_sz = ARRAY_SIZE(isa_ext_arr) - 1;
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/* No extension support available */
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if (arr_sz <= 0)
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return;
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for (i = 0; i <= arr_sz; i++) {
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edata = &isa_ext_arr[i];
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if (!__riscv_isa_extension_available(NULL, edata->isa_ext_id))
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continue;
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seq_printf(f, "_%s", edata->uprop);
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}
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}
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/*
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* These are the only valid base (single letter) ISA extensions as per the spec.
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* It also specifies the canonical order in which it appears in the spec.
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* Some of the extension may just be a place holder for now (B, K, P, J).
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* This should be updated once corresponding extensions are ratified.
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*/
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static const char base_riscv_exts[13] = "imafdqcbkjpvh";
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static void print_isa(struct seq_file *f, const char *isa)
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{
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int i;
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seq_puts(f, "isa\t\t: ");
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/* Print the rv[64/32] part */
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seq_write(f, isa, 4);
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for (i = 0; i < sizeof(base_riscv_exts); i++) {
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if (__riscv_isa_extension_available(NULL, base_riscv_exts[i] - 'a'))
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/* Print only enabled the base ISA extensions */
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seq_write(f, &base_riscv_exts[i], 1);
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}
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print_isa_ext(f);
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seq_puts(f, "\n");
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}
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static void print_mmu(struct seq_file *f)
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{
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char sv_type[16];
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#ifdef CONFIG_MMU
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#if defined(CONFIG_32BIT)
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strncpy(sv_type, "sv32", 5);
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#elif defined(CONFIG_64BIT)
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if (pgtable_l5_enabled)
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strncpy(sv_type, "sv57", 5);
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else if (pgtable_l4_enabled)
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strncpy(sv_type, "sv48", 5);
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else
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strncpy(sv_type, "sv39", 5);
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#endif
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#else
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strncpy(sv_type, "none", 5);
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#endif /* CONFIG_MMU */
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seq_printf(f, "mmu\t\t: %s\n", sv_type);
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}
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static void *c_start(struct seq_file *m, loff_t *pos)
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{
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if (*pos == nr_cpu_ids)
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return NULL;
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*pos = cpumask_next(*pos - 1, cpu_online_mask);
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if ((*pos) < nr_cpu_ids)
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return (void *)(uintptr_t)(1 + *pos);
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return NULL;
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}
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static void *c_next(struct seq_file *m, void *v, loff_t *pos)
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{
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(*pos)++;
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return c_start(m, pos);
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}
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static void c_stop(struct seq_file *m, void *v)
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{
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}
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static int c_show(struct seq_file *m, void *v)
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{
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unsigned long cpu_id = (unsigned long)v - 1;
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struct device_node *node = of_get_cpu_node(cpu_id, NULL);
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struct riscv_cpuinfo *ci = per_cpu_ptr(&riscv_cpuinfo, cpu_id);
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const char *compat, *isa;
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seq_printf(m, "processor\t: %lu\n", cpu_id);
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seq_printf(m, "hart\t\t: %lu\n", cpuid_to_hartid_map(cpu_id));
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if (!of_property_read_string(node, "riscv,isa", &isa))
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print_isa(m, isa);
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print_mmu(m);
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if (!of_property_read_string(node, "compatible", &compat)
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&& strcmp(compat, "riscv"))
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seq_printf(m, "uarch\t\t: %s\n", compat);
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seq_printf(m, "mvendorid\t: 0x%lx\n", ci->mvendorid);
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seq_printf(m, "marchid\t\t: 0x%lx\n", ci->marchid);
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seq_printf(m, "mimpid\t\t: 0x%lx\n", ci->mimpid);
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seq_puts(m, "\n");
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of_node_put(node);
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return 0;
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}
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const struct seq_operations cpuinfo_op = {
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.start = c_start,
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.next = c_next,
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.stop = c_stop,
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.show = c_show
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};
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#endif /* CONFIG_PROC_FS */
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