777 lines
21 KiB
C
777 lines
21 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 1999-2006 Helge Deller <deller@gmx.de> (07-13-1999)
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* Copyright (C) 1999 SuSE GmbH Nuernberg
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* Copyright (C) 2000 Philipp Rumpf (prumpf@tux.org)
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*
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* Cache and TLB management
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*
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*/
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/mm.h>
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#include <linux/module.h>
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#include <linux/seq_file.h>
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#include <linux/pagemap.h>
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#include <linux/sched.h>
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#include <linux/sched/mm.h>
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#include <asm/pdc.h>
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#include <asm/cache.h>
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#include <asm/cacheflush.h>
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#include <asm/tlbflush.h>
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#include <asm/page.h>
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#include <asm/processor.h>
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#include <asm/sections.h>
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#include <asm/shmparam.h>
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#include <asm/mmu_context.h>
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int split_tlb __ro_after_init;
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int dcache_stride __ro_after_init;
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int icache_stride __ro_after_init;
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EXPORT_SYMBOL(dcache_stride);
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void flush_dcache_page_asm(unsigned long phys_addr, unsigned long vaddr);
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EXPORT_SYMBOL(flush_dcache_page_asm);
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void purge_dcache_page_asm(unsigned long phys_addr, unsigned long vaddr);
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void flush_icache_page_asm(unsigned long phys_addr, unsigned long vaddr);
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/* Internal implementation in arch/parisc/kernel/pacache.S */
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void flush_data_cache_local(void *); /* flushes local data-cache only */
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void flush_instruction_cache_local(void); /* flushes local code-cache only */
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/* On some machines (i.e., ones with the Merced bus), there can be
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* only a single PxTLB broadcast at a time; this must be guaranteed
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* by software. We need a spinlock around all TLB flushes to ensure
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* this.
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*/
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DEFINE_SPINLOCK(pa_tlb_flush_lock);
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#if defined(CONFIG_64BIT) && defined(CONFIG_SMP)
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int pa_serialize_tlb_flushes __ro_after_init;
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#endif
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struct pdc_cache_info cache_info __ro_after_init;
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#ifndef CONFIG_PA20
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static struct pdc_btlb_info btlb_info __ro_after_init;
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#endif
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DEFINE_STATIC_KEY_TRUE(parisc_has_cache);
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DEFINE_STATIC_KEY_TRUE(parisc_has_dcache);
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DEFINE_STATIC_KEY_TRUE(parisc_has_icache);
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static void cache_flush_local_cpu(void *dummy)
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{
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if (static_branch_likely(&parisc_has_icache))
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flush_instruction_cache_local();
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if (static_branch_likely(&parisc_has_dcache))
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flush_data_cache_local(NULL);
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}
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void flush_cache_all_local(void)
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{
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cache_flush_local_cpu(NULL);
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}
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void flush_cache_all(void)
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{
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if (static_branch_likely(&parisc_has_cache))
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on_each_cpu(cache_flush_local_cpu, NULL, 1);
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}
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static inline void flush_data_cache(void)
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{
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if (static_branch_likely(&parisc_has_dcache))
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on_each_cpu(flush_data_cache_local, NULL, 1);
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}
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/* Kernel virtual address of pfn. */
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#define pfn_va(pfn) __va(PFN_PHYS(pfn))
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void
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__update_cache(pte_t pte)
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{
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unsigned long pfn = pte_pfn(pte);
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struct page *page;
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/* We don't have pte special. As a result, we can be called with
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an invalid pfn and we don't need to flush the kernel dcache page.
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This occurs with FireGL card in C8000. */
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if (!pfn_valid(pfn))
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return;
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page = pfn_to_page(pfn);
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if (page_mapping_file(page) &&
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test_bit(PG_dcache_dirty, &page->flags)) {
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flush_kernel_dcache_page_addr(pfn_va(pfn));
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clear_bit(PG_dcache_dirty, &page->flags);
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} else if (parisc_requires_coherency())
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flush_kernel_dcache_page_addr(pfn_va(pfn));
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}
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void
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show_cache_info(struct seq_file *m)
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{
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char buf[32];
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seq_printf(m, "I-cache\t\t: %ld KB\n",
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cache_info.ic_size/1024 );
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if (cache_info.dc_loop != 1)
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snprintf(buf, 32, "%lu-way associative", cache_info.dc_loop);
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seq_printf(m, "D-cache\t\t: %ld KB (%s%s, %s, alias=%d)\n",
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cache_info.dc_size/1024,
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(cache_info.dc_conf.cc_wt ? "WT":"WB"),
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(cache_info.dc_conf.cc_sh ? ", shared I/D":""),
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((cache_info.dc_loop == 1) ? "direct mapped" : buf),
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cache_info.dc_conf.cc_alias
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);
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seq_printf(m, "ITLB entries\t: %ld\n" "DTLB entries\t: %ld%s\n",
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cache_info.it_size,
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cache_info.dt_size,
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cache_info.dt_conf.tc_sh ? " - shared with ITLB":""
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);
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#ifndef CONFIG_PA20
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/* BTLB - Block TLB */
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if (btlb_info.max_size==0) {
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seq_printf(m, "BTLB\t\t: not supported\n" );
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} else {
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seq_printf(m,
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"BTLB fixed\t: max. %d pages, pagesize=%d (%dMB)\n"
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"BTLB fix-entr.\t: %d instruction, %d data (%d combined)\n"
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"BTLB var-entr.\t: %d instruction, %d data (%d combined)\n",
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btlb_info.max_size, (int)4096,
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btlb_info.max_size>>8,
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btlb_info.fixed_range_info.num_i,
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btlb_info.fixed_range_info.num_d,
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btlb_info.fixed_range_info.num_comb,
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btlb_info.variable_range_info.num_i,
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btlb_info.variable_range_info.num_d,
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btlb_info.variable_range_info.num_comb
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);
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}
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#endif
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}
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void __init
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parisc_cache_init(void)
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{
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if (pdc_cache_info(&cache_info) < 0)
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panic("parisc_cache_init: pdc_cache_info failed");
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#if 0
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printk("ic_size %lx dc_size %lx it_size %lx\n",
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cache_info.ic_size,
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cache_info.dc_size,
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cache_info.it_size);
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printk("DC base 0x%lx stride 0x%lx count 0x%lx loop 0x%lx\n",
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cache_info.dc_base,
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cache_info.dc_stride,
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cache_info.dc_count,
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cache_info.dc_loop);
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printk("dc_conf = 0x%lx alias %d blk %d line %d shift %d\n",
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*(unsigned long *) (&cache_info.dc_conf),
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cache_info.dc_conf.cc_alias,
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cache_info.dc_conf.cc_block,
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cache_info.dc_conf.cc_line,
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cache_info.dc_conf.cc_shift);
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printk(" wt %d sh %d cst %d hv %d\n",
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cache_info.dc_conf.cc_wt,
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cache_info.dc_conf.cc_sh,
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cache_info.dc_conf.cc_cst,
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cache_info.dc_conf.cc_hv);
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printk("IC base 0x%lx stride 0x%lx count 0x%lx loop 0x%lx\n",
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cache_info.ic_base,
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cache_info.ic_stride,
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cache_info.ic_count,
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cache_info.ic_loop);
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printk("IT base 0x%lx stride 0x%lx count 0x%lx loop 0x%lx off_base 0x%lx off_stride 0x%lx off_count 0x%lx\n",
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cache_info.it_sp_base,
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cache_info.it_sp_stride,
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cache_info.it_sp_count,
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cache_info.it_loop,
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cache_info.it_off_base,
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cache_info.it_off_stride,
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cache_info.it_off_count);
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printk("DT base 0x%lx stride 0x%lx count 0x%lx loop 0x%lx off_base 0x%lx off_stride 0x%lx off_count 0x%lx\n",
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cache_info.dt_sp_base,
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cache_info.dt_sp_stride,
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cache_info.dt_sp_count,
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cache_info.dt_loop,
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cache_info.dt_off_base,
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cache_info.dt_off_stride,
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cache_info.dt_off_count);
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printk("ic_conf = 0x%lx alias %d blk %d line %d shift %d\n",
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*(unsigned long *) (&cache_info.ic_conf),
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cache_info.ic_conf.cc_alias,
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cache_info.ic_conf.cc_block,
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cache_info.ic_conf.cc_line,
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cache_info.ic_conf.cc_shift);
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printk(" wt %d sh %d cst %d hv %d\n",
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cache_info.ic_conf.cc_wt,
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cache_info.ic_conf.cc_sh,
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cache_info.ic_conf.cc_cst,
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cache_info.ic_conf.cc_hv);
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printk("D-TLB conf: sh %d page %d cst %d aid %d sr %d\n",
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cache_info.dt_conf.tc_sh,
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cache_info.dt_conf.tc_page,
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cache_info.dt_conf.tc_cst,
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cache_info.dt_conf.tc_aid,
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cache_info.dt_conf.tc_sr);
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printk("I-TLB conf: sh %d page %d cst %d aid %d sr %d\n",
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cache_info.it_conf.tc_sh,
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cache_info.it_conf.tc_page,
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cache_info.it_conf.tc_cst,
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cache_info.it_conf.tc_aid,
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cache_info.it_conf.tc_sr);
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#endif
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split_tlb = 0;
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if (cache_info.dt_conf.tc_sh == 0 || cache_info.dt_conf.tc_sh == 2) {
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if (cache_info.dt_conf.tc_sh == 2)
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printk(KERN_WARNING "Unexpected TLB configuration. "
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"Will flush I/D separately (could be optimized).\n");
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split_tlb = 1;
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}
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/* "New and Improved" version from Jim Hull
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* (1 << (cc_block-1)) * (cc_line << (4 + cnf.cc_shift))
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* The following CAFL_STRIDE is an optimized version, see
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* http://lists.parisc-linux.org/pipermail/parisc-linux/2004-June/023625.html
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* http://lists.parisc-linux.org/pipermail/parisc-linux/2004-June/023671.html
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*/
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#define CAFL_STRIDE(cnf) (cnf.cc_line << (3 + cnf.cc_block + cnf.cc_shift))
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dcache_stride = CAFL_STRIDE(cache_info.dc_conf);
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icache_stride = CAFL_STRIDE(cache_info.ic_conf);
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#undef CAFL_STRIDE
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#ifndef CONFIG_PA20
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if (pdc_btlb_info(&btlb_info) < 0) {
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memset(&btlb_info, 0, sizeof btlb_info);
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}
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#endif
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if ((boot_cpu_data.pdc.capabilities & PDC_MODEL_NVA_MASK) ==
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PDC_MODEL_NVA_UNSUPPORTED) {
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printk(KERN_WARNING "parisc_cache_init: Only equivalent aliasing supported!\n");
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#if 0
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panic("SMP kernel required to avoid non-equivalent aliasing");
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#endif
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}
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}
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void disable_sr_hashing(void)
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{
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int srhash_type, retval;
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unsigned long space_bits;
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switch (boot_cpu_data.cpu_type) {
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case pcx: /* We shouldn't get this far. setup.c should prevent it. */
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BUG();
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return;
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case pcxs:
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case pcxt:
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case pcxt_:
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srhash_type = SRHASH_PCXST;
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break;
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case pcxl:
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srhash_type = SRHASH_PCXL;
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break;
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case pcxl2: /* pcxl2 doesn't support space register hashing */
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return;
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default: /* Currently all PA2.0 machines use the same ins. sequence */
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srhash_type = SRHASH_PA20;
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break;
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}
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disable_sr_hashing_asm(srhash_type);
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retval = pdc_spaceid_bits(&space_bits);
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/* If this procedure isn't implemented, don't panic. */
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if (retval < 0 && retval != PDC_BAD_OPTION)
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panic("pdc_spaceid_bits call failed.\n");
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if (space_bits != 0)
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panic("SpaceID hashing is still on!\n");
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}
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static inline void
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__flush_cache_page(struct vm_area_struct *vma, unsigned long vmaddr,
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unsigned long physaddr)
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{
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if (!static_branch_likely(&parisc_has_cache))
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return;
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preempt_disable();
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flush_dcache_page_asm(physaddr, vmaddr);
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if (vma->vm_flags & VM_EXEC)
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flush_icache_page_asm(physaddr, vmaddr);
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preempt_enable();
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}
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static void flush_user_cache_page(struct vm_area_struct *vma, unsigned long vmaddr)
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{
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unsigned long flags, space, pgd, prot;
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#ifdef CONFIG_TLB_PTLOCK
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unsigned long pgd_lock;
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#endif
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vmaddr &= PAGE_MASK;
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preempt_disable();
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/* Set context for flush */
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local_irq_save(flags);
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prot = mfctl(8);
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space = mfsp(SR_USER);
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pgd = mfctl(25);
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#ifdef CONFIG_TLB_PTLOCK
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pgd_lock = mfctl(28);
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#endif
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switch_mm_irqs_off(NULL, vma->vm_mm, NULL);
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local_irq_restore(flags);
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flush_user_dcache_range_asm(vmaddr, vmaddr + PAGE_SIZE);
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if (vma->vm_flags & VM_EXEC)
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flush_user_icache_range_asm(vmaddr, vmaddr + PAGE_SIZE);
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flush_tlb_page(vma, vmaddr);
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/* Restore previous context */
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local_irq_save(flags);
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#ifdef CONFIG_TLB_PTLOCK
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mtctl(pgd_lock, 28);
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#endif
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mtctl(pgd, 25);
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mtsp(space, SR_USER);
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mtctl(prot, 8);
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local_irq_restore(flags);
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preempt_enable();
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}
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static inline pte_t *get_ptep(struct mm_struct *mm, unsigned long addr)
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{
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pte_t *ptep = NULL;
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pgd_t *pgd = mm->pgd;
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p4d_t *p4d;
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pud_t *pud;
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pmd_t *pmd;
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if (!pgd_none(*pgd)) {
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p4d = p4d_offset(pgd, addr);
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if (!p4d_none(*p4d)) {
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pud = pud_offset(p4d, addr);
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if (!pud_none(*pud)) {
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pmd = pmd_offset(pud, addr);
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if (!pmd_none(*pmd))
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ptep = pte_offset_map(pmd, addr);
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}
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}
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}
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return ptep;
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}
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static inline bool pte_needs_flush(pte_t pte)
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{
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return (pte_val(pte) & (_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_NO_CACHE))
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== (_PAGE_PRESENT | _PAGE_ACCESSED);
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}
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void flush_dcache_page(struct page *page)
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{
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struct address_space *mapping = page_mapping_file(page);
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struct vm_area_struct *mpnt;
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unsigned long offset;
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unsigned long addr, old_addr = 0;
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unsigned long count = 0;
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unsigned long flags;
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pgoff_t pgoff;
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if (mapping && !mapping_mapped(mapping)) {
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set_bit(PG_dcache_dirty, &page->flags);
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return;
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}
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flush_kernel_dcache_page_addr(page_address(page));
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if (!mapping)
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return;
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pgoff = page->index;
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/*
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* We have carefully arranged in arch_get_unmapped_area() that
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* *any* mappings of a file are always congruently mapped (whether
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* declared as MAP_PRIVATE or MAP_SHARED), so we only need
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* to flush one address here for them all to become coherent
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* on machines that support equivalent aliasing
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*/
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flush_dcache_mmap_lock_irqsave(mapping, flags);
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vma_interval_tree_foreach(mpnt, &mapping->i_mmap, pgoff, pgoff) {
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offset = (pgoff - mpnt->vm_pgoff) << PAGE_SHIFT;
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addr = mpnt->vm_start + offset;
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if (parisc_requires_coherency()) {
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pte_t *ptep;
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ptep = get_ptep(mpnt->vm_mm, addr);
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if (ptep && pte_needs_flush(*ptep))
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flush_user_cache_page(mpnt, addr);
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} else {
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/*
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* The TLB is the engine of coherence on parisc:
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* The CPU is entitled to speculate any page
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* with a TLB mapping, so here we kill the
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* mapping then flush the page along a special
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* flush only alias mapping. This guarantees that
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* the page is no-longer in the cache for any
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* process and nor may it be speculatively read
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* in (until the user or kernel specifically
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* accesses it, of course)
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*/
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flush_tlb_page(mpnt, addr);
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if (old_addr == 0 || (old_addr & (SHM_COLOUR - 1))
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!= (addr & (SHM_COLOUR - 1))) {
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__flush_cache_page(mpnt, addr, page_to_phys(page));
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/*
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* Software is allowed to have any number
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* of private mappings to a page.
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*/
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if (!(mpnt->vm_flags & VM_SHARED))
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continue;
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if (old_addr)
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pr_err("INEQUIVALENT ALIASES 0x%lx and 0x%lx in file %pD\n",
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old_addr, addr, mpnt->vm_file);
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old_addr = addr;
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}
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}
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WARN_ON(++count == 4096);
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}
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flush_dcache_mmap_unlock_irqrestore(mapping, flags);
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}
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EXPORT_SYMBOL(flush_dcache_page);
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/* Defined in arch/parisc/kernel/pacache.S */
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EXPORT_SYMBOL(flush_kernel_dcache_range_asm);
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EXPORT_SYMBOL(flush_kernel_icache_range_asm);
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#define FLUSH_THRESHOLD 0x80000 /* 0.5MB */
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static unsigned long parisc_cache_flush_threshold __ro_after_init = FLUSH_THRESHOLD;
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#define FLUSH_TLB_THRESHOLD (16*1024) /* 16 KiB minimum TLB threshold */
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static unsigned long parisc_tlb_flush_threshold __ro_after_init = ~0UL;
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void __init parisc_setup_cache_timing(void)
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{
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unsigned long rangetime, alltime;
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unsigned long size;
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unsigned long threshold, threshold2;
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alltime = mfctl(16);
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flush_data_cache();
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alltime = mfctl(16) - alltime;
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size = (unsigned long)(_end - _text);
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rangetime = mfctl(16);
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flush_kernel_dcache_range((unsigned long)_text, size);
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rangetime = mfctl(16) - rangetime;
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printk(KERN_DEBUG "Whole cache flush %lu cycles, flushing %lu bytes %lu cycles\n",
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alltime, size, rangetime);
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threshold = L1_CACHE_ALIGN((unsigned long)((uint64_t)size * alltime / rangetime));
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pr_info("Calculated flush threshold is %lu KiB\n",
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threshold/1024);
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/*
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* The threshold computed above isn't very reliable. The following
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* heuristic works reasonably well on c8000/rp3440.
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*/
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threshold2 = cache_info.dc_size * num_online_cpus();
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parisc_cache_flush_threshold = threshold2;
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printk(KERN_INFO "Cache flush threshold set to %lu KiB\n",
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parisc_cache_flush_threshold/1024);
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/* calculate TLB flush threshold */
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/* On SMP machines, skip the TLB measure of kernel text which
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* has been mapped as huge pages. */
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if (num_online_cpus() > 1 && !parisc_requires_coherency()) {
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threshold = max(cache_info.it_size, cache_info.dt_size);
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threshold *= PAGE_SIZE;
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threshold /= num_online_cpus();
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goto set_tlb_threshold;
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}
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size = (unsigned long)_end - (unsigned long)_text;
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rangetime = mfctl(16);
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flush_tlb_kernel_range((unsigned long)_text, (unsigned long)_end);
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rangetime = mfctl(16) - rangetime;
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alltime = mfctl(16);
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flush_tlb_all();
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alltime = mfctl(16) - alltime;
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printk(KERN_INFO "Whole TLB flush %lu cycles, Range flush %lu bytes %lu cycles\n",
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alltime, size, rangetime);
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threshold = PAGE_ALIGN((num_online_cpus() * size * alltime) / rangetime);
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printk(KERN_INFO "Calculated TLB flush threshold %lu KiB\n",
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threshold/1024);
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set_tlb_threshold:
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if (threshold > FLUSH_TLB_THRESHOLD)
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parisc_tlb_flush_threshold = threshold;
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else
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parisc_tlb_flush_threshold = FLUSH_TLB_THRESHOLD;
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printk(KERN_INFO "TLB flush threshold set to %lu KiB\n",
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parisc_tlb_flush_threshold/1024);
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}
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extern void purge_kernel_dcache_page_asm(unsigned long);
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extern void clear_user_page_asm(void *, unsigned long);
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extern void copy_user_page_asm(void *, void *, unsigned long);
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void flush_kernel_dcache_page_addr(const void *addr)
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{
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unsigned long flags;
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flush_kernel_dcache_page_asm(addr);
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purge_tlb_start(flags);
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pdtlb(SR_KERNEL, addr);
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purge_tlb_end(flags);
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}
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EXPORT_SYMBOL(flush_kernel_dcache_page_addr);
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static void flush_cache_page_if_present(struct vm_area_struct *vma,
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unsigned long vmaddr, unsigned long pfn)
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{
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pte_t *ptep = get_ptep(vma->vm_mm, vmaddr);
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/*
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* The pte check is racy and sometimes the flush will trigger
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* a non-access TLB miss. Hopefully, the page has already been
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* flushed.
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*/
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if (ptep && pte_needs_flush(*ptep))
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flush_cache_page(vma, vmaddr, pfn);
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}
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void copy_user_highpage(struct page *to, struct page *from,
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unsigned long vaddr, struct vm_area_struct *vma)
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{
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void *kto, *kfrom;
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kfrom = kmap_local_page(from);
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kto = kmap_local_page(to);
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flush_cache_page_if_present(vma, vaddr, page_to_pfn(from));
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copy_page_asm(kto, kfrom);
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kunmap_local(kto);
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kunmap_local(kfrom);
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}
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void copy_to_user_page(struct vm_area_struct *vma, struct page *page,
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unsigned long user_vaddr, void *dst, void *src, int len)
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{
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flush_cache_page_if_present(vma, user_vaddr, page_to_pfn(page));
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memcpy(dst, src, len);
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flush_kernel_dcache_range_asm((unsigned long)dst, (unsigned long)dst + len);
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}
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void copy_from_user_page(struct vm_area_struct *vma, struct page *page,
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unsigned long user_vaddr, void *dst, void *src, int len)
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{
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flush_cache_page_if_present(vma, user_vaddr, page_to_pfn(page));
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memcpy(dst, src, len);
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}
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/* __flush_tlb_range()
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*
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* returns 1 if all TLBs were flushed.
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*/
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int __flush_tlb_range(unsigned long sid, unsigned long start,
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unsigned long end)
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{
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unsigned long flags;
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if ((!IS_ENABLED(CONFIG_SMP) || !arch_irqs_disabled()) &&
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end - start >= parisc_tlb_flush_threshold) {
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flush_tlb_all();
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return 1;
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}
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/* Purge TLB entries for small ranges using the pdtlb and
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pitlb instructions. These instructions execute locally
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but cause a purge request to be broadcast to other TLBs. */
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while (start < end) {
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purge_tlb_start(flags);
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mtsp(sid, SR_TEMP1);
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pdtlb(SR_TEMP1, start);
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pitlb(SR_TEMP1, start);
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purge_tlb_end(flags);
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start += PAGE_SIZE;
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}
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return 0;
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}
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static void flush_cache_pages(struct vm_area_struct *vma, unsigned long start, unsigned long end)
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{
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unsigned long addr, pfn;
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pte_t *ptep;
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for (addr = start; addr < end; addr += PAGE_SIZE) {
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/*
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* The vma can contain pages that aren't present. Although
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* the pte search is expensive, we need the pte to find the
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* page pfn and to check whether the page should be flushed.
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*/
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ptep = get_ptep(vma->vm_mm, addr);
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if (ptep && pte_needs_flush(*ptep)) {
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if (parisc_requires_coherency()) {
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flush_user_cache_page(vma, addr);
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} else {
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pfn = pte_pfn(*ptep);
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if (WARN_ON(!pfn_valid(pfn)))
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return;
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__flush_cache_page(vma, addr, PFN_PHYS(pfn));
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}
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}
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}
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}
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static inline unsigned long mm_total_size(struct mm_struct *mm)
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{
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struct vm_area_struct *vma;
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unsigned long usize = 0;
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VMA_ITERATOR(vmi, mm, 0);
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for_each_vma(vmi, vma) {
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if (usize >= parisc_cache_flush_threshold)
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break;
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usize += vma->vm_end - vma->vm_start;
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}
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return usize;
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}
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void flush_cache_mm(struct mm_struct *mm)
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{
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struct vm_area_struct *vma;
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VMA_ITERATOR(vmi, mm, 0);
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/*
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* Flushing the whole cache on each cpu takes forever on
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* rp3440, etc. So, avoid it if the mm isn't too big.
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*
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* Note that we must flush the entire cache on machines
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* with aliasing caches to prevent random segmentation
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* faults.
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*/
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if (!parisc_requires_coherency()
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|| mm_total_size(mm) >= parisc_cache_flush_threshold) {
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if (WARN_ON(IS_ENABLED(CONFIG_SMP) && arch_irqs_disabled()))
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return;
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flush_tlb_all();
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flush_cache_all();
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return;
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}
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/* Flush mm */
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for_each_vma(vmi, vma)
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flush_cache_pages(vma, vma->vm_start, vma->vm_end);
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}
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void flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end)
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{
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if (!parisc_requires_coherency()
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|| end - start >= parisc_cache_flush_threshold) {
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if (WARN_ON(IS_ENABLED(CONFIG_SMP) && arch_irqs_disabled()))
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return;
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flush_tlb_range(vma, start, end);
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flush_cache_all();
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return;
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}
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flush_cache_pages(vma, start, end);
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}
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void flush_cache_page(struct vm_area_struct *vma, unsigned long vmaddr, unsigned long pfn)
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{
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if (WARN_ON(!pfn_valid(pfn)))
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return;
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if (parisc_requires_coherency())
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flush_user_cache_page(vma, vmaddr);
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else
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__flush_cache_page(vma, vmaddr, PFN_PHYS(pfn));
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}
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void flush_anon_page(struct vm_area_struct *vma, struct page *page, unsigned long vmaddr)
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{
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if (!PageAnon(page))
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return;
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if (parisc_requires_coherency()) {
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if (vma->vm_flags & VM_SHARED)
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flush_data_cache();
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else
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flush_user_cache_page(vma, vmaddr);
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return;
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}
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flush_tlb_page(vma, vmaddr);
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preempt_disable();
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flush_dcache_page_asm(page_to_phys(page), vmaddr);
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preempt_enable();
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}
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void flush_kernel_vmap_range(void *vaddr, int size)
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{
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unsigned long start = (unsigned long)vaddr;
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unsigned long end = start + size;
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if ((!IS_ENABLED(CONFIG_SMP) || !arch_irqs_disabled()) &&
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(unsigned long)size >= parisc_cache_flush_threshold) {
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flush_tlb_kernel_range(start, end);
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flush_data_cache();
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return;
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}
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flush_kernel_dcache_range_asm(start, end);
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flush_tlb_kernel_range(start, end);
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}
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EXPORT_SYMBOL(flush_kernel_vmap_range);
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void invalidate_kernel_vmap_range(void *vaddr, int size)
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{
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unsigned long start = (unsigned long)vaddr;
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unsigned long end = start + size;
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/* Ensure DMA is complete */
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asm_syncdma();
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if ((!IS_ENABLED(CONFIG_SMP) || !arch_irqs_disabled()) &&
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(unsigned long)size >= parisc_cache_flush_threshold) {
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flush_tlb_kernel_range(start, end);
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flush_data_cache();
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return;
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}
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purge_kernel_dcache_range_asm(start, end);
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flush_tlb_kernel_range(start, end);
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}
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EXPORT_SYMBOL(invalidate_kernel_vmap_range);
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