228 lines
6.1 KiB
C
228 lines
6.1 KiB
C
// SPDX-License-Identifier: GPL-2.0
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#include <linux/smp.h>
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#include <linux/types.h>
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#include <asm/cpu.h>
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#include <asm/cpu-info.h>
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#include <asm/elf.h>
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#include <loongson_regs.h>
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#include <cpucfg-emul.h>
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static bool is_loongson(struct cpuinfo_mips *c)
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{
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switch (c->processor_id & PRID_COMP_MASK) {
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case PRID_COMP_LEGACY:
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return ((c->processor_id & PRID_IMP_MASK) ==
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PRID_IMP_LOONGSON_64C);
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case PRID_COMP_LOONGSON:
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return true;
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default:
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return false;
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}
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}
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static u32 get_loongson_fprev(struct cpuinfo_mips *c)
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{
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return c->fpu_id & LOONGSON_FPREV_MASK;
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}
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static bool cpu_has_uca(void)
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{
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u32 diag = read_c0_diag();
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u32 new_diag;
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if (diag & LOONGSON_DIAG_UCAC)
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/* UCA is already enabled. */
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return true;
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/* See if UCAC bit can be flipped on. This should be safe. */
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new_diag = diag | LOONGSON_DIAG_UCAC;
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write_c0_diag(new_diag);
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new_diag = read_c0_diag();
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write_c0_diag(diag);
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return (new_diag & LOONGSON_DIAG_UCAC) != 0;
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}
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static void probe_uca(struct cpuinfo_mips *c)
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{
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if (cpu_has_uca())
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c->loongson3_cpucfg_data[0] |= LOONGSON_CFG1_LSUCA;
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}
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static void decode_loongson_config6(struct cpuinfo_mips *c)
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{
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u32 config6 = read_c0_config6();
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if (config6 & LOONGSON_CONF6_SFBEN)
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c->loongson3_cpucfg_data[0] |= LOONGSON_CFG1_SFBP;
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if (config6 & LOONGSON_CONF6_LLEXC)
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c->loongson3_cpucfg_data[0] |= LOONGSON_CFG1_LLEXC;
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if (config6 & LOONGSON_CONF6_SCRAND)
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c->loongson3_cpucfg_data[0] |= LOONGSON_CFG1_SCRAND;
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}
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static void patch_cpucfg_sel1(struct cpuinfo_mips *c)
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{
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u64 ases = c->ases;
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u64 options = c->options;
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u32 data = c->loongson3_cpucfg_data[0];
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if (options & MIPS_CPU_FPU) {
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data |= LOONGSON_CFG1_FP;
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data |= get_loongson_fprev(c) << LOONGSON_CFG1_FPREV_OFFSET;
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}
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if (ases & MIPS_ASE_LOONGSON_MMI)
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data |= LOONGSON_CFG1_MMI;
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if (ases & MIPS_ASE_MSA)
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data |= LOONGSON_CFG1_MSA1;
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c->loongson3_cpucfg_data[0] = data;
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}
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static void patch_cpucfg_sel2(struct cpuinfo_mips *c)
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{
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u64 ases = c->ases;
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u64 options = c->options;
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u32 data = c->loongson3_cpucfg_data[1];
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if (ases & MIPS_ASE_LOONGSON_EXT)
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data |= LOONGSON_CFG2_LEXT1;
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if (ases & MIPS_ASE_LOONGSON_EXT2)
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data |= LOONGSON_CFG2_LEXT2;
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if (options & MIPS_CPU_LDPTE)
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data |= LOONGSON_CFG2_LSPW;
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if (ases & MIPS_ASE_VZ)
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data |= LOONGSON_CFG2_LVZP;
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else
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data &= ~LOONGSON_CFG2_LVZREV;
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c->loongson3_cpucfg_data[1] = data;
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}
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static void patch_cpucfg_sel3(struct cpuinfo_mips *c)
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{
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u64 ases = c->ases;
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u32 data = c->loongson3_cpucfg_data[2];
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if (ases & MIPS_ASE_LOONGSON_CAM) {
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data |= LOONGSON_CFG3_LCAMP;
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} else {
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data &= ~LOONGSON_CFG3_LCAMREV;
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data &= ~LOONGSON_CFG3_LCAMNUM;
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data &= ~LOONGSON_CFG3_LCAMKW;
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data &= ~LOONGSON_CFG3_LCAMVW;
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}
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c->loongson3_cpucfg_data[2] = data;
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}
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void loongson3_cpucfg_synthesize_data(struct cpuinfo_mips *c)
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{
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/* Only engage the logic on Loongson processors. */
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if (!is_loongson(c))
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return;
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/* CPUs with CPUCFG support don't need to synthesize anything. */
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if (cpu_has_cfg())
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goto have_cpucfg_now;
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c->loongson3_cpucfg_data[0] = 0;
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c->loongson3_cpucfg_data[1] = 0;
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c->loongson3_cpucfg_data[2] = 0;
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/* Add CPUCFG features non-discoverable otherwise. */
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switch (c->processor_id & (PRID_IMP_MASK | PRID_REV_MASK)) {
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case PRID_IMP_LOONGSON_64R | PRID_REV_LOONGSON2K_R1_0:
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case PRID_IMP_LOONGSON_64R | PRID_REV_LOONGSON2K_R1_1:
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case PRID_IMP_LOONGSON_64R | PRID_REV_LOONGSON2K_R1_2:
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case PRID_IMP_LOONGSON_64R | PRID_REV_LOONGSON2K_R1_3:
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decode_loongson_config6(c);
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probe_uca(c);
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c->loongson3_cpucfg_data[0] |= (LOONGSON_CFG1_LSLDR0 |
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LOONGSON_CFG1_LSSYNCI | LOONGSON_CFG1_LLSYNC |
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LOONGSON_CFG1_TGTSYNC);
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c->loongson3_cpucfg_data[1] |= (LOONGSON_CFG2_LBT1 |
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LOONGSON_CFG2_LBT2 | LOONGSON_CFG2_LPMP |
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LOONGSON_CFG2_LPM_REV2);
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c->loongson3_cpucfg_data[2] = 0;
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break;
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case PRID_IMP_LOONGSON_64C | PRID_REV_LOONGSON3A_R1:
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c->loongson3_cpucfg_data[0] |= (LOONGSON_CFG1_LSLDR0 |
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LOONGSON_CFG1_LSSYNCI | LOONGSON_CFG1_LSUCA |
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LOONGSON_CFG1_LLSYNC | LOONGSON_CFG1_TGTSYNC);
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c->loongson3_cpucfg_data[1] |= (LOONGSON_CFG2_LBT1 |
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LOONGSON_CFG2_LPMP | LOONGSON_CFG2_LPM_REV1);
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c->loongson3_cpucfg_data[2] |= (
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LOONGSON_CFG3_LCAM_REV1 |
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LOONGSON_CFG3_LCAMNUM_REV1 |
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LOONGSON_CFG3_LCAMKW_REV1 |
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LOONGSON_CFG3_LCAMVW_REV1);
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break;
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case PRID_IMP_LOONGSON_64C | PRID_REV_LOONGSON3B_R1:
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case PRID_IMP_LOONGSON_64C | PRID_REV_LOONGSON3B_R2:
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c->loongson3_cpucfg_data[0] |= (LOONGSON_CFG1_LSLDR0 |
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LOONGSON_CFG1_LSSYNCI | LOONGSON_CFG1_LSUCA |
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LOONGSON_CFG1_LLSYNC | LOONGSON_CFG1_TGTSYNC);
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c->loongson3_cpucfg_data[1] |= (LOONGSON_CFG2_LBT1 |
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LOONGSON_CFG2_LPMP | LOONGSON_CFG2_LPM_REV1);
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c->loongson3_cpucfg_data[2] |= (
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LOONGSON_CFG3_LCAM_REV1 |
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LOONGSON_CFG3_LCAMNUM_REV1 |
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LOONGSON_CFG3_LCAMKW_REV1 |
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LOONGSON_CFG3_LCAMVW_REV1);
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break;
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case PRID_IMP_LOONGSON_64C | PRID_REV_LOONGSON3A_R2_0:
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case PRID_IMP_LOONGSON_64C | PRID_REV_LOONGSON3A_R2_1:
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case PRID_IMP_LOONGSON_64C | PRID_REV_LOONGSON3A_R3_0:
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case PRID_IMP_LOONGSON_64C | PRID_REV_LOONGSON3A_R3_1:
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decode_loongson_config6(c);
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probe_uca(c);
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c->loongson3_cpucfg_data[0] |= (LOONGSON_CFG1_CNT64 |
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LOONGSON_CFG1_LSLDR0 | LOONGSON_CFG1_LSPREF |
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LOONGSON_CFG1_LSPREFX | LOONGSON_CFG1_LSSYNCI |
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LOONGSON_CFG1_LLSYNC | LOONGSON_CFG1_TGTSYNC);
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c->loongson3_cpucfg_data[1] |= (LOONGSON_CFG2_LBT1 |
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LOONGSON_CFG2_LBT2 | LOONGSON_CFG2_LBTMMU |
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LOONGSON_CFG2_LPMP | LOONGSON_CFG2_LPM_REV1 |
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LOONGSON_CFG2_LVZ_REV1);
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c->loongson3_cpucfg_data[2] |= (LOONGSON_CFG3_LCAM_REV1 |
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LOONGSON_CFG3_LCAMNUM_REV1 |
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LOONGSON_CFG3_LCAMKW_REV1 |
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LOONGSON_CFG3_LCAMVW_REV1);
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break;
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default:
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/* It is possible that some future Loongson cores still do
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* not have CPUCFG, so do not emulate anything for these
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* cores.
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*/
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return;
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}
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/* This feature is set by firmware, but all known Loongson-64 systems
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* are configured this way.
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*/
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c->loongson3_cpucfg_data[0] |= LOONGSON_CFG1_CDMAP;
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/* Patch in dynamically probed bits. */
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patch_cpucfg_sel1(c);
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patch_cpucfg_sel2(c);
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patch_cpucfg_sel3(c);
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have_cpucfg_now:
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/* We have usable CPUCFG now, emulated or not.
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* Announce CPUCFG availability to userspace via hwcap.
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*/
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elf_hwcap |= HWCAP_LOONGSON_CPUCFG;
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}
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