76 lines
2.7 KiB
C
76 lines
2.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* DRA7xx PRCM MPU instance offset macros
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*
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* Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com
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*
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* Generated by code originally written by:
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* Paul Walmsley (paul@pwsan.com)
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* Rajendra Nayak (rnayak@ti.com)
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* Benoit Cousson (b-cousson@ti.com)
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*
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* This file is automatically generated from the OMAP hardware databases.
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* We respectfully ask that any modifications to this file be coordinated
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* with the public linux-omap@vger.kernel.org mailing list and the
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* authors above to ensure that the autogeneration scripts are kept
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* up-to-date with the file contents.
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*/
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#ifndef __ARCH_ARM_MACH_OMAP2_PRCM_MPU7XX_H
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#define __ARCH_ARM_MACH_OMAP2_PRCM_MPU7XX_H
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#include "prcm_mpu_44xx_54xx.h"
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#define DRA7XX_PRCM_MPU_BASE 0x48243000
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#define DRA7XX_PRCM_MPU_REGADDR(inst, reg) \
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OMAP2_L4_IO_ADDRESS(DRA7XX_PRCM_MPU_BASE + (inst) + (reg))
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/* MPU_PRCM instances */
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#define DRA7XX_MPU_PRCM_OCP_SOCKET_INST 0x0000
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#define DRA7XX_MPU_PRCM_DEVICE_INST 0x0200
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#define DRA7XX_MPU_PRCM_PRM_C0_INST 0x0400
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#define DRA7XX_MPU_PRCM_CM_C0_INST 0x0600
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#define DRA7XX_MPU_PRCM_PRM_C1_INST 0x0800
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#define DRA7XX_MPU_PRCM_CM_C1_INST 0x0a00
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/* PRCM_MPU clockdomain register offsets (from instance start) */
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#define DRA7XX_MPU_PRCM_CM_C0_CPU0_CDOFFS 0x0000
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#define DRA7XX_MPU_PRCM_CM_C1_CPU1_CDOFFS 0x0000
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/* MPU_PRCM */
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/* MPU_PRCM.PRCM_MPU_OCP_SOCKET register offsets */
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#define DRA7XX_REVISION_PRCM_MPU_OFFSET 0x0000
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/* MPU_PRCM.PRCM_MPU_DEVICE register offsets */
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#define DRA7XX_PRM_FRAC_INCREMENTER_NUMERATOR_OFFSET 0x0010
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#define DRA7XX_PRM_FRAC_INCREMENTER_DENUMERATOR_RELOAD_OFFSET 0x0014
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/* MPU_PRCM.PRCM_MPU_PRM_C0 register offsets */
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#define DRA7XX_PM_CPU0_PWRSTCTRL_OFFSET 0x0000
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#define DRA7XX_PM_CPU0_PWRSTST_OFFSET 0x0004
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#define DRA7XX_RM_CPU0_CPU0_RSTCTRL_OFFSET 0x0010
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#define DRA7XX_RM_CPU0_CPU0_RSTST_OFFSET 0x0014
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#define DRA7XX_RM_CPU0_CPU0_CONTEXT_OFFSET 0x0024
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/* MPU_PRCM.PRCM_MPU_CM_C0 register offsets */
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#define DRA7XX_CM_CPU0_CLKSTCTRL_OFFSET 0x0000
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#define DRA7XX_CM_CPU0_CPU0_CLKCTRL_OFFSET 0x0020
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#define DRA7XX_CM_CPU0_CPU0_CLKCTRL DRA7XX_MPU_PRCM_REGADDR(DRA7XX_MPU_PRCM_CM_C0_INST, 0x0020)
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/* MPU_PRCM.PRCM_MPU_PRM_C1 register offsets */
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#define DRA7XX_PM_CPU1_PWRSTCTRL_OFFSET 0x0000
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#define DRA7XX_PM_CPU1_PWRSTST_OFFSET 0x0004
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#define DRA7XX_RM_CPU1_CPU1_RSTCTRL_OFFSET 0x0010
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#define DRA7XX_RM_CPU1_CPU1_RSTST_OFFSET 0x0014
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#define DRA7XX_RM_CPU1_CPU1_CONTEXT_OFFSET 0x0024
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/* MPU_PRCM.PRCM_MPU_CM_C1 register offsets */
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#define DRA7XX_CM_CPU1_CLKSTCTRL_OFFSET 0x0000
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#define DRA7XX_CM_CPU1_CPU1_CLKCTRL_OFFSET 0x0020
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#define DRA7XX_CM_CPU1_CPU1_CLKCTRL DRA7XX_MPU_PRCM_REGADDR(DRA7XX_MPU_PRCM_CM_C1_INST, 0x0020)
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#endif
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