286 lines
6.5 KiB
C
286 lines
6.5 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Copyright 2011-2013 Freescale Semiconductor, Inc.
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* Copyright 2011 Linaro Ltd.
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*/
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <linux/irqchip.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include "common.h"
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#include "hardware.h"
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#define GPC_CNTR 0x0
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#define GPC_IMR1 0x008
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#define GPC_PGC_CPU_PDN 0x2a0
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#define GPC_PGC_CPU_PUPSCR 0x2a4
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#define GPC_PGC_CPU_PDNSCR 0x2a8
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#define GPC_PGC_SW2ISO_SHIFT 0x8
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#define GPC_PGC_SW_SHIFT 0x0
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#define GPC_CNTR_L2_PGE_SHIFT 22
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#define IMR_NUM 4
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#define GPC_MAX_IRQS (IMR_NUM * 32)
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static void __iomem *gpc_base;
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static u32 gpc_wake_irqs[IMR_NUM];
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static u32 gpc_saved_imrs[IMR_NUM];
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void imx_gpc_set_arm_power_up_timing(u32 sw2iso, u32 sw)
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{
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writel_relaxed((sw2iso << GPC_PGC_SW2ISO_SHIFT) |
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(sw << GPC_PGC_SW_SHIFT), gpc_base + GPC_PGC_CPU_PUPSCR);
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}
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void imx_gpc_set_arm_power_down_timing(u32 sw2iso, u32 sw)
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{
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writel_relaxed((sw2iso << GPC_PGC_SW2ISO_SHIFT) |
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(sw << GPC_PGC_SW_SHIFT), gpc_base + GPC_PGC_CPU_PDNSCR);
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}
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void imx_gpc_set_arm_power_in_lpm(bool power_off)
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{
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writel_relaxed(power_off, gpc_base + GPC_PGC_CPU_PDN);
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}
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void imx_gpc_set_l2_mem_power_in_lpm(bool power_off)
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{
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u32 val;
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val = readl_relaxed(gpc_base + GPC_CNTR);
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val &= ~(1 << GPC_CNTR_L2_PGE_SHIFT);
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if (power_off)
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val |= 1 << GPC_CNTR_L2_PGE_SHIFT;
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writel_relaxed(val, gpc_base + GPC_CNTR);
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}
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void imx_gpc_pre_suspend(bool arm_power_off)
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{
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void __iomem *reg_imr1 = gpc_base + GPC_IMR1;
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int i;
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/* Tell GPC to power off ARM core when suspend */
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if (arm_power_off)
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imx_gpc_set_arm_power_in_lpm(arm_power_off);
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for (i = 0; i < IMR_NUM; i++) {
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gpc_saved_imrs[i] = readl_relaxed(reg_imr1 + i * 4);
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writel_relaxed(~gpc_wake_irqs[i], reg_imr1 + i * 4);
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}
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}
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void imx_gpc_post_resume(void)
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{
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void __iomem *reg_imr1 = gpc_base + GPC_IMR1;
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int i;
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/* Keep ARM core powered on for other low-power modes */
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imx_gpc_set_arm_power_in_lpm(false);
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for (i = 0; i < IMR_NUM; i++)
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writel_relaxed(gpc_saved_imrs[i], reg_imr1 + i * 4);
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}
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static int imx_gpc_irq_set_wake(struct irq_data *d, unsigned int on)
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{
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unsigned int idx = d->hwirq / 32;
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u32 mask;
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mask = 1 << d->hwirq % 32;
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gpc_wake_irqs[idx] = on ? gpc_wake_irqs[idx] | mask :
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gpc_wake_irqs[idx] & ~mask;
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/*
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* Do *not* call into the parent, as the GIC doesn't have any
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* wake-up facility...
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*/
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return 0;
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}
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void imx_gpc_mask_all(void)
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{
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void __iomem *reg_imr1 = gpc_base + GPC_IMR1;
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int i;
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for (i = 0; i < IMR_NUM; i++) {
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gpc_saved_imrs[i] = readl_relaxed(reg_imr1 + i * 4);
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writel_relaxed(~0, reg_imr1 + i * 4);
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}
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}
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void imx_gpc_restore_all(void)
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{
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void __iomem *reg_imr1 = gpc_base + GPC_IMR1;
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int i;
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for (i = 0; i < IMR_NUM; i++)
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writel_relaxed(gpc_saved_imrs[i], reg_imr1 + i * 4);
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}
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void imx_gpc_hwirq_unmask(unsigned int hwirq)
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{
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void __iomem *reg;
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u32 val;
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reg = gpc_base + GPC_IMR1 + hwirq / 32 * 4;
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val = readl_relaxed(reg);
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val &= ~(1 << hwirq % 32);
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writel_relaxed(val, reg);
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}
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void imx_gpc_hwirq_mask(unsigned int hwirq)
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{
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void __iomem *reg;
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u32 val;
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reg = gpc_base + GPC_IMR1 + hwirq / 32 * 4;
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val = readl_relaxed(reg);
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val |= 1 << (hwirq % 32);
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writel_relaxed(val, reg);
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}
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static void imx_gpc_irq_unmask(struct irq_data *d)
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{
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imx_gpc_hwirq_unmask(d->hwirq);
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irq_chip_unmask_parent(d);
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}
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static void imx_gpc_irq_mask(struct irq_data *d)
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{
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imx_gpc_hwirq_mask(d->hwirq);
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irq_chip_mask_parent(d);
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}
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static struct irq_chip imx_gpc_chip = {
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.name = "GPC",
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.irq_eoi = irq_chip_eoi_parent,
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.irq_mask = imx_gpc_irq_mask,
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.irq_unmask = imx_gpc_irq_unmask,
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.irq_retrigger = irq_chip_retrigger_hierarchy,
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.irq_set_wake = imx_gpc_irq_set_wake,
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.irq_set_type = irq_chip_set_type_parent,
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#ifdef CONFIG_SMP
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.irq_set_affinity = irq_chip_set_affinity_parent,
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#endif
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};
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static int imx_gpc_domain_translate(struct irq_domain *d,
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struct irq_fwspec *fwspec,
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unsigned long *hwirq,
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unsigned int *type)
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{
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if (is_of_node(fwspec->fwnode)) {
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if (fwspec->param_count != 3)
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return -EINVAL;
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/* No PPI should point to this domain */
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if (fwspec->param[0] != 0)
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return -EINVAL;
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*hwirq = fwspec->param[1];
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*type = fwspec->param[2];
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return 0;
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}
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return -EINVAL;
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}
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static int imx_gpc_domain_alloc(struct irq_domain *domain,
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unsigned int irq,
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unsigned int nr_irqs, void *data)
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{
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struct irq_fwspec *fwspec = data;
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struct irq_fwspec parent_fwspec;
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irq_hw_number_t hwirq;
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int i;
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if (fwspec->param_count != 3)
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return -EINVAL; /* Not GIC compliant */
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if (fwspec->param[0] != 0)
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return -EINVAL; /* No PPI should point to this domain */
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hwirq = fwspec->param[1];
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if (hwirq >= GPC_MAX_IRQS)
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return -EINVAL; /* Can't deal with this */
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for (i = 0; i < nr_irqs; i++)
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irq_domain_set_hwirq_and_chip(domain, irq + i, hwirq + i,
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&imx_gpc_chip, NULL);
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parent_fwspec = *fwspec;
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parent_fwspec.fwnode = domain->parent->fwnode;
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return irq_domain_alloc_irqs_parent(domain, irq, nr_irqs,
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&parent_fwspec);
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}
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static const struct irq_domain_ops imx_gpc_domain_ops = {
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.translate = imx_gpc_domain_translate,
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.alloc = imx_gpc_domain_alloc,
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.free = irq_domain_free_irqs_common,
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};
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static int __init imx_gpc_init(struct device_node *node,
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struct device_node *parent)
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{
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struct irq_domain *parent_domain, *domain;
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int i;
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if (!parent) {
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pr_err("%pOF: no parent, giving up\n", node);
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return -ENODEV;
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}
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parent_domain = irq_find_host(parent);
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if (!parent_domain) {
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pr_err("%pOF: unable to obtain parent domain\n", node);
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return -ENXIO;
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}
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gpc_base = of_iomap(node, 0);
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if (WARN_ON(!gpc_base))
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return -ENOMEM;
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domain = irq_domain_add_hierarchy(parent_domain, 0, GPC_MAX_IRQS,
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node, &imx_gpc_domain_ops,
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NULL);
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if (!domain) {
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iounmap(gpc_base);
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return -ENOMEM;
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}
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/* Initially mask all interrupts */
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for (i = 0; i < IMR_NUM; i++)
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writel_relaxed(~0, gpc_base + GPC_IMR1 + i * 4);
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/*
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* Clear the OF_POPULATED flag set in of_irq_init so that
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* later the GPC power domain driver will not be skipped.
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*/
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of_node_clear_flag(node, OF_POPULATED);
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return 0;
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}
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IRQCHIP_DECLARE(imx_gpc, "fsl,imx6q-gpc", imx_gpc_init);
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void __init imx_gpc_check_dt(void)
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{
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struct device_node *np;
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np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-gpc");
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if (WARN_ON(!np))
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return;
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if (WARN_ON(!of_find_property(np, "interrupt-controller", NULL))) {
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pr_warn("Outdated DT detected, suspend/resume will NOT work\n");
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/* map GPC, so that at least CPUidle and WARs keep working */
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gpc_base = of_iomap(np, 0);
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}
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of_node_put(np);
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}
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