171 lines
5.8 KiB
YAML
171 lines
5.8 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
|
%YAML 1.2
|
|
---
|
|
$id: http://devicetree.org/schemas/pinctrl/renesas,rzv2m-pinctrl.yaml#
|
|
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
|
|
|
title: Renesas RZ/V2M combined Pin and GPIO controller
|
|
|
|
maintainers:
|
|
- Geert Uytterhoeven <geert+renesas@glider.be>
|
|
- Phil Edworthy <phil.edworthy@renesas.com>
|
|
|
|
description:
|
|
The Renesas RZ/V2M SoC features a combined Pin and GPIO controller.
|
|
Pin multiplexing and GPIO configuration is performed on a per-pin basis.
|
|
Each port features up to 16 pins, each of them configurable for GPIO function
|
|
(port mode) or in alternate function mode.
|
|
Up to 8 different alternate function modes exist for each single pin.
|
|
|
|
properties:
|
|
compatible:
|
|
const: renesas,r9a09g011-pinctrl # RZ/V2M
|
|
|
|
reg:
|
|
maxItems: 1
|
|
|
|
gpio-controller: true
|
|
|
|
'#gpio-cells':
|
|
const: 2
|
|
description:
|
|
The first cell contains the global GPIO port index, constructed using the
|
|
RZV2M_GPIO() helper macro in <dt-bindings/pinctrl/rzv2m-pinctrl.h> and the
|
|
second cell represents consumer flag as mentioned in ../gpio/gpio.txt
|
|
E.g. "RZV2M_GPIO(8, 1)" for P8_1.
|
|
|
|
gpio-ranges:
|
|
maxItems: 1
|
|
|
|
interrupts:
|
|
description: INEXINT[0..38] corresponding to individual pin inputs.
|
|
maxItems: 39
|
|
|
|
clocks:
|
|
maxItems: 1
|
|
|
|
power-domains:
|
|
maxItems: 1
|
|
|
|
resets:
|
|
maxItems: 1
|
|
|
|
additionalProperties:
|
|
anyOf:
|
|
- type: object
|
|
allOf:
|
|
- $ref: pincfg-node.yaml#
|
|
- $ref: pinmux-node.yaml#
|
|
|
|
description:
|
|
Pin controller client devices use pin configuration subnodes (children
|
|
and grandchildren) for desired pin configuration.
|
|
Client device subnodes use below standard properties.
|
|
|
|
properties:
|
|
phandle: true
|
|
pinmux:
|
|
description:
|
|
Values are constructed from GPIO port number, pin number, and
|
|
alternate function configuration number using the RZV2M_PORT_PINMUX()
|
|
helper macro in <dt-bindings/pinctrl/rzv2m-pinctrl.h>.
|
|
pins: true
|
|
bias-disable: true
|
|
bias-pull-down: true
|
|
bias-pull-up: true
|
|
drive-strength-microamp:
|
|
# Superset of supported values
|
|
enum: [ 1600, 1800, 2000, 3200, 3800, 4000, 6400, 7800, 8000,
|
|
9000, 9600, 11000, 12000, 13000, 18000 ]
|
|
slew-rate:
|
|
description: 0 is slow slew rate, 1 is fast slew rate
|
|
enum: [ 0, 1 ]
|
|
gpio-hog: true
|
|
gpios: true
|
|
output-high: true
|
|
output-low: true
|
|
line-name: true
|
|
|
|
- type: object
|
|
properties:
|
|
phandle: true
|
|
|
|
additionalProperties:
|
|
$ref: "#/additionalProperties/anyOf/0"
|
|
|
|
allOf:
|
|
- $ref: "pinctrl.yaml#"
|
|
|
|
required:
|
|
- compatible
|
|
- reg
|
|
- gpio-controller
|
|
- '#gpio-cells'
|
|
- gpio-ranges
|
|
- interrupts
|
|
- clocks
|
|
- power-domains
|
|
- resets
|
|
|
|
examples:
|
|
- |
|
|
#include <dt-bindings/pinctrl/rzv2m-pinctrl.h>
|
|
#include <dt-bindings/clock/r9a09g011-cpg.h>
|
|
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
|
|
|
pinctrl: pinctrl@b6250000 {
|
|
compatible = "renesas,r9a09g011-pinctrl";
|
|
reg = <0xb6250000 0x800>;
|
|
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
gpio-ranges = <&pinctrl 0 0 352>;
|
|
interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD R9A09G011_PFC_PCLK>;
|
|
resets = <&cpg R9A09G011_PFC_PRESETN>;
|
|
power-domains = <&cpg>;
|
|
|
|
i2c2_pins: i2c2 {
|
|
pinmux = <RZV2M_PORT_PINMUX(3, 8, 2)>, /* SDA */
|
|
<RZV2M_PORT_PINMUX(3, 9, 2)>; /* SCL */
|
|
};
|
|
};
|