159 lines
3.8 KiB
YAML
159 lines
3.8 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/net/dsa/renesas,rzn1-a5psw.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Renesas RZ/N1 Advanced 5 ports ethernet switch
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maintainers:
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- Clément Léger <clement.leger@bootlin.com>
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description: |
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The advanced 5 ports switch is present on the Renesas RZ/N1 SoC family and
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handles 4 ports + 1 CPU management port.
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allOf:
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- $ref: dsa.yaml#
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properties:
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compatible:
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items:
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- enum:
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- renesas,r9a06g032-a5psw
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- const: renesas,rzn1-a5psw
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reg:
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maxItems: 1
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interrupts:
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items:
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- description: Device Level Ring (DLR) interrupt
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- description: Switch interrupt
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- description: Parallel Redundancy Protocol (PRP) interrupt
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- description: Integrated HUB module interrupt
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- description: Receive Pattern Match interrupt
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interrupt-names:
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items:
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- const: dlr
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- const: switch
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- const: prp
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- const: hub
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- const: ptrn
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power-domains:
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maxItems: 1
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mdio:
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$ref: /schemas/net/mdio.yaml#
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unevaluatedProperties: false
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clocks:
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items:
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- description: AHB clock used for the switch register interface
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- description: Switch system clock
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clock-names:
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items:
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- const: hclk
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- const: clk
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ethernet-ports:
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type: object
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properties:
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'#address-cells':
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const: 1
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'#size-cells':
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const: 0
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patternProperties:
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"^(ethernet-)?port@[0-4]$":
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type: object
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description: Ethernet switch ports
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properties:
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pcs-handle:
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description:
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phandle pointing to a PCS sub-node compatible with
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renesas,rzn1-miic.yaml#
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$ref: /schemas/types.yaml#/definitions/phandle
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unevaluatedProperties: false
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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- power-domains
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examples:
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- |
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/clock/r9a06g032-sysctrl.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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switch@44050000 {
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compatible = "renesas,r9a06g032-a5psw", "renesas,rzn1-a5psw";
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reg = <0x44050000 0x10000>;
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clocks = <&sysctrl R9A06G032_HCLK_SWITCH>, <&sysctrl R9A06G032_CLK_SWITCH>;
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clock-names = "hclk", "clk";
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power-domains = <&sysctrl>;
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interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "dlr", "switch", "prp", "hub", "ptrn";
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dsa,member = <0 0>;
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ethernet-ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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label = "lan0";
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phy-handle = <&switch0phy3>;
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pcs-handle = <&mii_conv4>;
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};
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port@1 {
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reg = <1>;
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label = "lan1";
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phy-handle = <&switch0phy1>;
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pcs-handle = <&mii_conv3>;
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};
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port@4 {
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reg = <4>;
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ethernet = <&gmac2>;
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phy-mode = "internal";
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fixed-link {
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speed = <1000>;
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full-duplex;
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};
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};
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};
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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reset-gpios = <&gpio0a 2 GPIO_ACTIVE_HIGH>;
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reset-delay-us = <15>;
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clock-frequency = <2500000>;
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switch0phy1: ethernet-phy@1{
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reg = <1>;
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};
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switch0phy3: ethernet-phy@3{
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reg = <3>;
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};
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};
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};
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