153 lines
4.9 KiB
YAML
153 lines
4.9 KiB
YAML
# SPDX-License-Identifier: GPL-2.0
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/mtd/nand-controller.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: NAND Chip and NAND Controller Generic Binding
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maintainers:
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- Miquel Raynal <miquel.raynal@bootlin.com>
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- Richard Weinberger <richard@nod.at>
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description: |
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The NAND controller should be represented with its own DT node, and
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all NAND chips attached to this controller should be defined as
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children nodes of the NAND controller. This representation should be
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enforced even for simple controllers supporting only one chip.
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The ECC strength and ECC step size properties define the user
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desires in terms of correction capability of a controller. Together,
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they request the ECC engine to correct {strength} bit errors per
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{size} bytes.
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The interpretation of these parameters is implementation-defined, so
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not all implementations must support all possible
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combinations. However, implementations are encouraged to further
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specify the value(s) they support.
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properties:
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$nodename:
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pattern: "^nand-controller(@.*)?"
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"#address-cells":
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const: 1
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"#size-cells":
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const: 0
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ranges: true
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cs-gpios:
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description:
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Array of chip-select available to the controller. The first
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entries are a 1:1 mapping of the available chip-select on the
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NAND controller (even if they are not used). As many additional
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chip-select as needed may follow and should be phandles of GPIO
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lines. 'reg' entries of the NAND chip subnodes become indexes of
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this array when this property is present.
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minItems: 1
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maxItems: 8
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patternProperties:
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"^nand@[a-f0-9]$":
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type: object
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$ref: "nand-chip.yaml#"
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properties:
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reg:
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description:
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Contains the chip-select IDs.
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nand-ecc-placement:
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description:
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Location of the ECC bytes. This location is unknown by default
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but can be explicitly set to "oob", if all ECC bytes are
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known to be stored in the OOB area, or "interleaved" if ECC
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bytes will be interleaved with regular data in the main area.
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$ref: /schemas/types.yaml#/definitions/string
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enum: [ oob, interleaved ]
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nand-bus-width:
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description:
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Bus width to the NAND chip
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$ref: /schemas/types.yaml#/definitions/uint32
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enum: [8, 16]
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default: 8
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nand-on-flash-bbt:
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description:
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With this property, the OS will search the device for a Bad
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Block Table (BBT). If not found, it will create one, reserve
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a few blocks at the end of the device to store it and update
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it as the device ages. Otherwise, the out-of-band area of a
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few pages of all the blocks will be scanned at boot time to
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find Bad Block Markers (BBM). These markers will help to
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build a volatile BBT in RAM.
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$ref: /schemas/types.yaml#/definitions/flag
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nand-ecc-maximize:
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description:
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Whether or not the ECC strength should be maximized. The
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maximum ECC strength is both controller and chip
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dependent. The ECC engine has to select the ECC config
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providing the best strength and taking the OOB area size
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constraint into account. This is particularly useful when
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only the in-band area is used by the upper layers, and you
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want to make your NAND as reliable as possible.
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$ref: /schemas/types.yaml#/definitions/flag
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nand-is-boot-medium:
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description:
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Whether or not the NAND chip is a boot medium. Drivers might
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use this information to select ECC algorithms supported by
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the boot ROM or similar restrictions.
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$ref: /schemas/types.yaml#/definitions/flag
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nand-rb:
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description:
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Contains the native Ready/Busy IDs.
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$ref: /schemas/types.yaml#/definitions/uint32-array
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rb-gpios:
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description:
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Contains one or more GPIO descriptor (the numper of descriptor
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depends on the number of R/B pins exposed by the flash) for the
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Ready/Busy pins. Active state refers to the NAND ready state and
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should be set to GPIOD_ACTIVE_HIGH unless the signal is inverted.
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wp-gpios:
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description:
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Contains one GPIO descriptor for the Write Protect pin.
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Active state refers to the NAND Write Protect state and should be
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set to GPIOD_ACTIVE_LOW unless the signal is inverted.
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maxItems: 1
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required:
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- reg
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required:
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- "#address-cells"
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- "#size-cells"
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additionalProperties: true
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examples:
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- |
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nand-controller {
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#address-cells = <1>;
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#size-cells = <0>;
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cs-gpios = <0>, <&gpioA 1>; /* A single native CS is available */
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/* controller specific properties */
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nand@0 {
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reg = <0>; /* Native CS */
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/* NAND chip specific properties */
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};
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nand@1 {
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reg = <1>; /* GPIO CS */
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};
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};
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