83 lines
2.3 KiB
YAML
83 lines
2.3 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/renesas,cpg-mstp-clocks.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Renesas Clock Pulse Generator (CPG) Module Stop (MSTP) Clocks
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maintainers:
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- Geert Uytterhoeven <geert+renesas@glider.be>
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description:
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The Clock Pulse Generator (CPG) can gate SoC device clocks. The gates are
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organized in groups of up to 32 gates.
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This device tree binding describes a single 32 gate clocks group per node.
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Clocks are referenced by user nodes by the Module Stop (MSTP) node phandle
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and the clock index in the group, from 0 to 31.
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properties:
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compatible:
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items:
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- enum:
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- renesas,r7s72100-mstp-clocks # RZ/A1
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- renesas,r8a73a4-mstp-clocks # R-Mobile APE6
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- renesas,r8a7740-mstp-clocks # R-Mobile A1
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- renesas,r8a7778-mstp-clocks # R-Car M1
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- renesas,r8a7779-mstp-clocks # R-Car H1
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- renesas,sh73a0-mstp-clocks # SH-Mobile AG5
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- const: renesas,cpg-mstp-clocks
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reg:
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minItems: 1
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items:
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- description: Module Stop Control Register (MSTPCR)
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- description: Module Stop Status Register (MSTPSR)
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clocks:
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minItems: 1
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maxItems: 32
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'#clock-cells':
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const: 1
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clock-indices:
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minItems: 1
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maxItems: 32
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clock-output-names:
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minItems: 1
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maxItems: 32
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required:
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- compatible
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- reg
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- clocks
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- '#clock-cells'
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- clock-indices
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- clock-output-names
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/r8a73a4-clock.h>
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mstp2_clks: mstp2_clks@e6150138 {
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compatible = "renesas,r8a73a4-mstp-clocks",
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"renesas,cpg-mstp-clocks";
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reg = <0xe6150138 4>, <0xe6150040 4>;
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clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
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<&mp_clk>, <&cpg_clocks R8A73A4_CLK_HP>;
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#clock-cells = <1>;
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clock-indices = <
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R8A73A4_CLK_SCIFA0 R8A73A4_CLK_SCIFA1
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R8A73A4_CLK_SCIFB0 R8A73A4_CLK_SCIFB1
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R8A73A4_CLK_SCIFB2 R8A73A4_CLK_SCIFB3
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R8A73A4_CLK_DMAC
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>;
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clock-output-names =
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"scifa0", "scifa1", "scifb0", "scifb1", "scifb2", "scifb3",
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"dmac";
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};
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