341 lines
12 KiB
ReStructuredText
341 lines
12 KiB
ReStructuredText
.. contents::
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.. sectnum::
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========================================
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eBPF Instruction Set Specification, v1.0
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========================================
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This document specifies version 1.0 of the eBPF instruction set.
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Registers and calling convention
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================================
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eBPF has 10 general purpose registers and a read-only frame pointer register,
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all of which are 64-bits wide.
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The eBPF calling convention is defined as:
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* R0: return value from function calls, and exit value for eBPF programs
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* R1 - R5: arguments for function calls
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* R6 - R9: callee saved registers that function calls will preserve
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* R10: read-only frame pointer to access stack
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R0 - R5 are scratch registers and eBPF programs needs to spill/fill them if
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necessary across calls.
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Instruction encoding
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====================
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eBPF has two instruction encodings:
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* the basic instruction encoding, which uses 64 bits to encode an instruction
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* the wide instruction encoding, which appends a second 64-bit immediate value
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(imm64) after the basic instruction for a total of 128 bits.
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The basic instruction encoding looks as follows:
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============= ======= =============== ==================== ============
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32 bits (MSB) 16 bits 4 bits 4 bits 8 bits (LSB)
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============= ======= =============== ==================== ============
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immediate offset source register destination register opcode
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============= ======= =============== ==================== ============
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Note that most instructions do not use all of the fields.
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Unused fields shall be cleared to zero.
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Instruction classes
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-------------------
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The three LSB bits of the 'opcode' field store the instruction class:
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========= ===== =============================== ===================================
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class value description reference
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========= ===== =============================== ===================================
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BPF_LD 0x00 non-standard load operations `Load and store instructions`_
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BPF_LDX 0x01 load into register operations `Load and store instructions`_
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BPF_ST 0x02 store from immediate operations `Load and store instructions`_
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BPF_STX 0x03 store from register operations `Load and store instructions`_
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BPF_ALU 0x04 32-bit arithmetic operations `Arithmetic and jump instructions`_
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BPF_JMP 0x05 64-bit jump operations `Arithmetic and jump instructions`_
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BPF_JMP32 0x06 32-bit jump operations `Arithmetic and jump instructions`_
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BPF_ALU64 0x07 64-bit arithmetic operations `Arithmetic and jump instructions`_
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========= ===== =============================== ===================================
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Arithmetic and jump instructions
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================================
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For arithmetic and jump instructions (``BPF_ALU``, ``BPF_ALU64``, ``BPF_JMP`` and
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``BPF_JMP32``), the 8-bit 'opcode' field is divided into three parts:
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============== ====== =================
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4 bits (MSB) 1 bit 3 bits (LSB)
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============== ====== =================
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operation code source instruction class
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============== ====== =================
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The 4th bit encodes the source operand:
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====== ===== ========================================
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source value description
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====== ===== ========================================
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BPF_K 0x00 use 32-bit immediate as source operand
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BPF_X 0x08 use 'src_reg' register as source operand
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====== ===== ========================================
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The four MSB bits store the operation code.
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Arithmetic instructions
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-----------------------
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``BPF_ALU`` uses 32-bit wide operands while ``BPF_ALU64`` uses 64-bit wide operands for
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otherwise identical operations.
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The 'code' field encodes the operation as below:
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======== ===== ==========================================================
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code value description
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======== ===== ==========================================================
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BPF_ADD 0x00 dst += src
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BPF_SUB 0x10 dst -= src
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BPF_MUL 0x20 dst \*= src
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BPF_DIV 0x30 dst = (src != 0) ? (dst / src) : 0
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BPF_OR 0x40 dst \|= src
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BPF_AND 0x50 dst &= src
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BPF_LSH 0x60 dst <<= src
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BPF_RSH 0x70 dst >>= src
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BPF_NEG 0x80 dst = ~src
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BPF_MOD 0x90 dst = (src != 0) ? (dst % src) : dst
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BPF_XOR 0xa0 dst ^= src
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BPF_MOV 0xb0 dst = src
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BPF_ARSH 0xc0 sign extending shift right
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BPF_END 0xd0 byte swap operations (see `Byte swap instructions`_ below)
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======== ===== ==========================================================
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Underflow and overflow are allowed during arithmetic operations, meaning
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the 64-bit or 32-bit value will wrap. If eBPF program execution would
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result in division by zero, the destination register is instead set to zero.
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If execution would result in modulo by zero, for ``BPF_ALU64`` the value of
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the destination register is unchanged whereas for ``BPF_ALU`` the upper
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32 bits of the destination register are zeroed.
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``BPF_ADD | BPF_X | BPF_ALU`` means::
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dst_reg = (u32) dst_reg + (u32) src_reg;
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``BPF_ADD | BPF_X | BPF_ALU64`` means::
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dst_reg = dst_reg + src_reg
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``BPF_XOR | BPF_K | BPF_ALU`` means::
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src_reg = (u32) src_reg ^ (u32) imm32
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``BPF_XOR | BPF_K | BPF_ALU64`` means::
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src_reg = src_reg ^ imm32
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Also note that the division and modulo operations are unsigned. Thus, for
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``BPF_ALU``, 'imm' is first interpreted as an unsigned 32-bit value, whereas
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for ``BPF_ALU64``, 'imm' is first sign extended to 64 bits and the result
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interpreted as an unsigned 64-bit value. There are no instructions for
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signed division or modulo.
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Byte swap instructions
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~~~~~~~~~~~~~~~~~~~~~~
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The byte swap instructions use an instruction class of ``BPF_ALU`` and a 4-bit
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'code' field of ``BPF_END``.
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The byte swap instructions operate on the destination register
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only and do not use a separate source register or immediate value.
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The 1-bit source operand field in the opcode is used to select what byte
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order the operation convert from or to:
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========= ===== =================================================
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source value description
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========= ===== =================================================
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BPF_TO_LE 0x00 convert between host byte order and little endian
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BPF_TO_BE 0x08 convert between host byte order and big endian
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========= ===== =================================================
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The 'imm' field encodes the width of the swap operations. The following widths
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are supported: 16, 32 and 64.
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Examples:
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``BPF_ALU | BPF_TO_LE | BPF_END`` with imm = 16 means::
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dst_reg = htole16(dst_reg)
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``BPF_ALU | BPF_TO_BE | BPF_END`` with imm = 64 means::
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dst_reg = htobe64(dst_reg)
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Jump instructions
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-----------------
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``BPF_JMP32`` uses 32-bit wide operands while ``BPF_JMP`` uses 64-bit wide operands for
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otherwise identical operations.
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The 'code' field encodes the operation as below:
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======== ===== ========================= ============
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code value description notes
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======== ===== ========================= ============
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BPF_JA 0x00 PC += off BPF_JMP only
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BPF_JEQ 0x10 PC += off if dst == src
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BPF_JGT 0x20 PC += off if dst > src unsigned
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BPF_JGE 0x30 PC += off if dst >= src unsigned
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BPF_JSET 0x40 PC += off if dst & src
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BPF_JNE 0x50 PC += off if dst != src
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BPF_JSGT 0x60 PC += off if dst > src signed
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BPF_JSGE 0x70 PC += off if dst >= src signed
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BPF_CALL 0x80 function call
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BPF_EXIT 0x90 function / program return BPF_JMP only
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BPF_JLT 0xa0 PC += off if dst < src unsigned
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BPF_JLE 0xb0 PC += off if dst <= src unsigned
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BPF_JSLT 0xc0 PC += off if dst < src signed
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BPF_JSLE 0xd0 PC += off if dst <= src signed
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======== ===== ========================= ============
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The eBPF program needs to store the return value into register R0 before doing a
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BPF_EXIT.
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Load and store instructions
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===========================
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For load and store instructions (``BPF_LD``, ``BPF_LDX``, ``BPF_ST``, and ``BPF_STX``), the
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8-bit 'opcode' field is divided as:
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============ ====== =================
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3 bits (MSB) 2 bits 3 bits (LSB)
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============ ====== =================
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mode size instruction class
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============ ====== =================
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The mode modifier is one of:
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============= ===== ==================================== =============
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mode modifier value description reference
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============= ===== ==================================== =============
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BPF_IMM 0x00 64-bit immediate instructions `64-bit immediate instructions`_
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BPF_ABS 0x20 legacy BPF packet access (absolute) `Legacy BPF Packet access instructions`_
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BPF_IND 0x40 legacy BPF packet access (indirect) `Legacy BPF Packet access instructions`_
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BPF_MEM 0x60 regular load and store operations `Regular load and store operations`_
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BPF_ATOMIC 0xc0 atomic operations `Atomic operations`_
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============= ===== ==================================== =============
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The size modifier is one of:
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============= ===== =====================
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size modifier value description
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============= ===== =====================
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BPF_W 0x00 word (4 bytes)
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BPF_H 0x08 half word (2 bytes)
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BPF_B 0x10 byte
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BPF_DW 0x18 double word (8 bytes)
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============= ===== =====================
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Regular load and store operations
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---------------------------------
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The ``BPF_MEM`` mode modifier is used to encode regular load and store
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instructions that transfer data between a register and memory.
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``BPF_MEM | <size> | BPF_STX`` means::
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*(size *) (dst_reg + off) = src_reg
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``BPF_MEM | <size> | BPF_ST`` means::
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*(size *) (dst_reg + off) = imm32
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``BPF_MEM | <size> | BPF_LDX`` means::
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dst_reg = *(size *) (src_reg + off)
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Where size is one of: ``BPF_B``, ``BPF_H``, ``BPF_W``, or ``BPF_DW``.
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Atomic operations
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-----------------
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Atomic operations are operations that operate on memory and can not be
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interrupted or corrupted by other access to the same memory region
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by other eBPF programs or means outside of this specification.
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All atomic operations supported by eBPF are encoded as store operations
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that use the ``BPF_ATOMIC`` mode modifier as follows:
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* ``BPF_ATOMIC | BPF_W | BPF_STX`` for 32-bit operations
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* ``BPF_ATOMIC | BPF_DW | BPF_STX`` for 64-bit operations
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* 8-bit and 16-bit wide atomic operations are not supported.
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The 'imm' field is used to encode the actual atomic operation.
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Simple atomic operation use a subset of the values defined to encode
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arithmetic operations in the 'imm' field to encode the atomic operation:
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======== ===== ===========
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imm value description
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======== ===== ===========
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BPF_ADD 0x00 atomic add
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BPF_OR 0x40 atomic or
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BPF_AND 0x50 atomic and
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BPF_XOR 0xa0 atomic xor
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======== ===== ===========
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``BPF_ATOMIC | BPF_W | BPF_STX`` with 'imm' = BPF_ADD means::
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*(u32 *)(dst_reg + off16) += src_reg
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``BPF_ATOMIC | BPF_DW | BPF_STX`` with 'imm' = BPF ADD means::
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*(u64 *)(dst_reg + off16) += src_reg
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In addition to the simple atomic operations, there also is a modifier and
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two complex atomic operations:
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=========== ================ ===========================
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imm value description
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=========== ================ ===========================
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BPF_FETCH 0x01 modifier: return old value
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BPF_XCHG 0xe0 | BPF_FETCH atomic exchange
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BPF_CMPXCHG 0xf0 | BPF_FETCH atomic compare and exchange
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=========== ================ ===========================
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The ``BPF_FETCH`` modifier is optional for simple atomic operations, and
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always set for the complex atomic operations. If the ``BPF_FETCH`` flag
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is set, then the operation also overwrites ``src_reg`` with the value that
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was in memory before it was modified.
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The ``BPF_XCHG`` operation atomically exchanges ``src_reg`` with the value
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addressed by ``dst_reg + off``.
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The ``BPF_CMPXCHG`` operation atomically compares the value addressed by
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``dst_reg + off`` with ``R0``. If they match, the value addressed by
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``dst_reg + off`` is replaced with ``src_reg``. In either case, the
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value that was at ``dst_reg + off`` before the operation is zero-extended
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and loaded back to ``R0``.
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64-bit immediate instructions
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-----------------------------
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Instructions with the ``BPF_IMM`` 'mode' modifier use the wide instruction
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encoding for an extra imm64 value.
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There is currently only one such instruction.
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``BPF_LD | BPF_DW | BPF_IMM`` means::
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dst_reg = imm64
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Legacy BPF Packet access instructions
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-------------------------------------
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eBPF previously introduced special instructions for access to packet data that were
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carried over from classic BPF. However, these instructions are
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deprecated and should no longer be used.
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