46 lines
878 B
C
46 lines
878 B
C
/* SPDX-License-Identifier: GPL-2.0
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*
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* mt8186-audsys-clkid.h -- Mediatek 8186 audsys clock id definition
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*
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* Copyright (c) 2022 MediaTek Inc.
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* Author: Jiaxin Yu <jiaxin.yu@mediatek.com>
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*/
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#ifndef _MT8186_AUDSYS_CLKID_H_
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#define _MT8186_AUDSYS_CLKID_H_
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enum{
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CLK_AUD_AFE,
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CLK_AUD_22M,
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CLK_AUD_24M,
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CLK_AUD_APLL2_TUNER,
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CLK_AUD_APLL_TUNER,
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CLK_AUD_TDM,
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CLK_AUD_ADC,
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CLK_AUD_DAC,
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CLK_AUD_DAC_PREDIS,
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CLK_AUD_TML,
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CLK_AUD_NLE,
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CLK_AUD_I2S1_BCLK,
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CLK_AUD_I2S2_BCLK,
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CLK_AUD_I2S3_BCLK,
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CLK_AUD_I2S4_BCLK,
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CLK_AUD_CONNSYS_I2S_ASRC,
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CLK_AUD_GENERAL1_ASRC,
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CLK_AUD_GENERAL2_ASRC,
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CLK_AUD_DAC_HIRES,
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CLK_AUD_ADC_HIRES,
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CLK_AUD_ADC_HIRES_TML,
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CLK_AUD_ADDA6_ADC,
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CLK_AUD_ADDA6_ADC_HIRES,
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CLK_AUD_3RD_DAC,
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CLK_AUD_3RD_DAC_PREDIS,
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CLK_AUD_3RD_DAC_TML,
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CLK_AUD_3RD_DAC_HIRES,
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CLK_AUD_ETDM_IN1_BCLK,
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CLK_AUD_ETDM_OUT1_BCLK,
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CLK_AUD_NR_CLK,
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};
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#endif
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