449 lines
12 KiB
C
449 lines
12 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*****************************************************************************
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*
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* Copyright (C) 2008 Cedric Bregardis <cedric.bregardis@free.fr> and
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* Jean-Christian Hassler <jhassler@free.fr>
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*
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* This file is part of the Audiowerk2 ALSA driver
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*
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*****************************************************************************/
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#define AW2_SAA7146_M
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#include <linux/init.h>
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#include <linux/pci.h>
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#include <linux/interrupt.h>
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <sound/core.h>
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#include <sound/initval.h>
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#include <sound/pcm.h>
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#include <sound/pcm_params.h>
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#include "saa7146.h"
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#include "aw2-saa7146.h"
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#include "aw2-tsl.c"
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#define WRITEREG(value, addr) writel((value), chip->base_addr + (addr))
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#define READREG(addr) readl(chip->base_addr + (addr))
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static struct snd_aw2_saa7146_cb_param
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arr_substream_it_playback_cb[NB_STREAM_PLAYBACK];
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static struct snd_aw2_saa7146_cb_param
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arr_substream_it_capture_cb[NB_STREAM_CAPTURE];
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static int snd_aw2_saa7146_get_limit(int size);
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/* chip-specific destructor */
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int snd_aw2_saa7146_free(struct snd_aw2_saa7146 *chip)
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{
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/* disable all irqs */
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WRITEREG(0, IER);
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/* reset saa7146 */
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WRITEREG((MRST_N << 16), MC1);
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/* Unset base addr */
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chip->base_addr = NULL;
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return 0;
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}
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void snd_aw2_saa7146_setup(struct snd_aw2_saa7146 *chip,
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void __iomem *pci_base_addr)
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{
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/* set PCI burst/threshold
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Burst length definition
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VALUE BURST LENGTH
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000 1 Dword
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001 2 Dwords
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010 4 Dwords
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011 8 Dwords
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100 16 Dwords
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101 32 Dwords
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110 64 Dwords
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111 128 Dwords
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Threshold definition
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VALUE WRITE MODE READ MODE
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00 1 Dword of valid data 1 empty Dword
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01 4 Dwords of valid data 4 empty Dwords
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10 8 Dwords of valid data 8 empty Dwords
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11 16 Dwords of valid data 16 empty Dwords */
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unsigned int acon2;
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unsigned int acon1 = 0;
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int i;
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/* Set base addr */
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chip->base_addr = pci_base_addr;
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/* disable all irqs */
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WRITEREG(0, IER);
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/* reset saa7146 */
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WRITEREG((MRST_N << 16), MC1);
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/* enable audio interface */
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#ifdef __BIG_ENDIAN
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acon1 |= A1_SWAP;
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acon1 |= A2_SWAP;
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#endif
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/* WS0_CTRL, WS0_SYNC: input TSL1, I2S */
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/* At initialization WS1 and WS2 are disabled (configured as input) */
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acon1 |= 0 * WS1_CTRL;
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acon1 |= 0 * WS2_CTRL;
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/* WS4 is not used. So it must not restart A2.
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This is why it is configured as output (force to low) */
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acon1 |= 3 * WS4_CTRL;
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/* WS3_CTRL, WS3_SYNC: output TSL2, I2S */
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acon1 |= 2 * WS3_CTRL;
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/* A1 and A2 are active and asynchronous */
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acon1 |= 3 * AUDIO_MODE;
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WRITEREG(acon1, ACON1);
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/* The following comes from original windows driver.
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It is needed to have a correct behavior of input and output
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simultenously, but I don't know why ! */
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WRITEREG(3 * (BurstA1_in) + 3 * (ThreshA1_in) +
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3 * (BurstA1_out) + 3 * (ThreshA1_out) +
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3 * (BurstA2_out) + 3 * (ThreshA2_out), PCI_BT_A);
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/* enable audio port pins */
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WRITEREG((EAP << 16) | EAP, MC1);
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/* enable I2C */
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WRITEREG((EI2C << 16) | EI2C, MC1);
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/* enable interrupts */
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WRITEREG(A1_out | A2_out | A1_in | IIC_S | IIC_E, IER);
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/* audio configuration */
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acon2 = A2_CLKSRC | BCLK1_OEN;
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WRITEREG(acon2, ACON2);
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/* By default use analog input */
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snd_aw2_saa7146_use_digital_input(chip, 0);
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/* TSL setup */
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for (i = 0; i < 8; ++i) {
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WRITEREG(tsl1[i], TSL1 + (i * 4));
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WRITEREG(tsl2[i], TSL2 + (i * 4));
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}
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}
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void snd_aw2_saa7146_pcm_init_playback(struct snd_aw2_saa7146 *chip,
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int stream_number,
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unsigned long dma_addr,
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unsigned long period_size,
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unsigned long buffer_size)
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{
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unsigned long dw_page, dw_limit;
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/* Configure DMA for substream
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Configuration informations: ALSA has allocated continuous memory
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pages. So we don't need to use MMU of saa7146.
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*/
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/* No MMU -> nothing to do with PageA1, we only configure the limit of
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PageAx_out register */
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/* Disable MMU */
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dw_page = (0L << 11);
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/* Configure Limit for DMA access.
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The limit register defines an address limit, which generates
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an interrupt if passed by the actual PCI address pointer.
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'0001' means an interrupt will be generated if the lower
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6 bits (64 bytes) of the PCI address are zero. '0010'
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defines a limit of 128 bytes, '0011' one of 256 bytes, and
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so on up to 1 Mbyte defined by '1111'. This interrupt range
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can be calculated as follows:
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Range = 2^(5 + Limit) bytes.
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*/
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dw_limit = snd_aw2_saa7146_get_limit(period_size);
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dw_page |= (dw_limit << 4);
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if (stream_number == 0) {
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WRITEREG(dw_page, PageA2_out);
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/* Base address for DMA transfert. */
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/* This address has been reserved by ALSA. */
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/* This is a physical address */
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WRITEREG(dma_addr, BaseA2_out);
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/* Define upper limit for DMA access */
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WRITEREG(dma_addr + buffer_size, ProtA2_out);
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} else if (stream_number == 1) {
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WRITEREG(dw_page, PageA1_out);
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/* Base address for DMA transfert. */
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/* This address has been reserved by ALSA. */
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/* This is a physical address */
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WRITEREG(dma_addr, BaseA1_out);
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/* Define upper limit for DMA access */
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WRITEREG(dma_addr + buffer_size, ProtA1_out);
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} else {
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pr_err("aw2: snd_aw2_saa7146_pcm_init_playback: "
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"Substream number is not 0 or 1 -> not managed\n");
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}
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}
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void snd_aw2_saa7146_pcm_init_capture(struct snd_aw2_saa7146 *chip,
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int stream_number, unsigned long dma_addr,
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unsigned long period_size,
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unsigned long buffer_size)
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{
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unsigned long dw_page, dw_limit;
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/* Configure DMA for substream
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Configuration informations: ALSA has allocated continuous memory
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pages. So we don't need to use MMU of saa7146.
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*/
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/* No MMU -> nothing to do with PageA1, we only configure the limit of
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PageAx_out register */
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/* Disable MMU */
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dw_page = (0L << 11);
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/* Configure Limit for DMA access.
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The limit register defines an address limit, which generates
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an interrupt if passed by the actual PCI address pointer.
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'0001' means an interrupt will be generated if the lower
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6 bits (64 bytes) of the PCI address are zero. '0010'
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defines a limit of 128 bytes, '0011' one of 256 bytes, and
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so on up to 1 Mbyte defined by '1111'. This interrupt range
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can be calculated as follows:
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Range = 2^(5 + Limit) bytes.
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*/
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dw_limit = snd_aw2_saa7146_get_limit(period_size);
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dw_page |= (dw_limit << 4);
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if (stream_number == 0) {
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WRITEREG(dw_page, PageA1_in);
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/* Base address for DMA transfert. */
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/* This address has been reserved by ALSA. */
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/* This is a physical address */
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WRITEREG(dma_addr, BaseA1_in);
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/* Define upper limit for DMA access */
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WRITEREG(dma_addr + buffer_size, ProtA1_in);
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} else {
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pr_err("aw2: snd_aw2_saa7146_pcm_init_capture: "
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"Substream number is not 0 -> not managed\n");
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}
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}
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void snd_aw2_saa7146_define_it_playback_callback(unsigned int stream_number,
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snd_aw2_saa7146_it_cb
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p_it_callback,
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void *p_callback_param)
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{
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if (stream_number < NB_STREAM_PLAYBACK) {
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arr_substream_it_playback_cb[stream_number].p_it_callback =
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(snd_aw2_saa7146_it_cb) p_it_callback;
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arr_substream_it_playback_cb[stream_number].p_callback_param =
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(void *)p_callback_param;
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}
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}
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void snd_aw2_saa7146_define_it_capture_callback(unsigned int stream_number,
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snd_aw2_saa7146_it_cb
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p_it_callback,
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void *p_callback_param)
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{
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if (stream_number < NB_STREAM_CAPTURE) {
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arr_substream_it_capture_cb[stream_number].p_it_callback =
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(snd_aw2_saa7146_it_cb) p_it_callback;
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arr_substream_it_capture_cb[stream_number].p_callback_param =
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(void *)p_callback_param;
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}
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}
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void snd_aw2_saa7146_pcm_trigger_start_playback(struct snd_aw2_saa7146 *chip,
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int stream_number)
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{
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unsigned int acon1 = 0;
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/* In aw8 driver, dma transfert is always active. It is
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started and stopped in a larger "space" */
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acon1 = READREG(ACON1);
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if (stream_number == 0) {
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WRITEREG((TR_E_A2_OUT << 16) | TR_E_A2_OUT, MC1);
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/* WS2_CTRL, WS2_SYNC: output TSL2, I2S */
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acon1 |= 2 * WS2_CTRL;
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WRITEREG(acon1, ACON1);
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} else if (stream_number == 1) {
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WRITEREG((TR_E_A1_OUT << 16) | TR_E_A1_OUT, MC1);
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/* WS1_CTRL, WS1_SYNC: output TSL1, I2S */
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acon1 |= 1 * WS1_CTRL;
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WRITEREG(acon1, ACON1);
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}
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}
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void snd_aw2_saa7146_pcm_trigger_stop_playback(struct snd_aw2_saa7146 *chip,
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int stream_number)
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{
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unsigned int acon1 = 0;
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acon1 = READREG(ACON1);
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if (stream_number == 0) {
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/* WS2_CTRL, WS2_SYNC: output TSL2, I2S */
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acon1 &= ~(3 * WS2_CTRL);
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WRITEREG(acon1, ACON1);
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WRITEREG((TR_E_A2_OUT << 16), MC1);
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} else if (stream_number == 1) {
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/* WS1_CTRL, WS1_SYNC: output TSL1, I2S */
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acon1 &= ~(3 * WS1_CTRL);
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WRITEREG(acon1, ACON1);
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WRITEREG((TR_E_A1_OUT << 16), MC1);
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}
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}
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void snd_aw2_saa7146_pcm_trigger_start_capture(struct snd_aw2_saa7146 *chip,
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int stream_number)
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{
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/* In aw8 driver, dma transfert is always active. It is
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started and stopped in a larger "space" */
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if (stream_number == 0)
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WRITEREG((TR_E_A1_IN << 16) | TR_E_A1_IN, MC1);
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}
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void snd_aw2_saa7146_pcm_trigger_stop_capture(struct snd_aw2_saa7146 *chip,
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int stream_number)
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{
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if (stream_number == 0)
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WRITEREG((TR_E_A1_IN << 16), MC1);
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}
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irqreturn_t snd_aw2_saa7146_interrupt(int irq, void *dev_id)
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{
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unsigned int isr;
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__always_unused unsigned int iicsta;
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struct snd_aw2_saa7146 *chip = dev_id;
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isr = READREG(ISR);
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if (!isr)
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return IRQ_NONE;
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WRITEREG(isr, ISR);
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if (isr & (IIC_S | IIC_E)) {
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iicsta = READREG(IICSTA);
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WRITEREG(0x100, IICSTA);
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}
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if (isr & A1_out) {
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if (arr_substream_it_playback_cb[1].p_it_callback != NULL) {
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arr_substream_it_playback_cb[1].
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p_it_callback(arr_substream_it_playback_cb[1].
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p_callback_param);
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}
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}
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if (isr & A2_out) {
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if (arr_substream_it_playback_cb[0].p_it_callback != NULL) {
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arr_substream_it_playback_cb[0].
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p_it_callback(arr_substream_it_playback_cb[0].
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p_callback_param);
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}
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}
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if (isr & A1_in) {
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if (arr_substream_it_capture_cb[0].p_it_callback != NULL) {
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arr_substream_it_capture_cb[0].
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p_it_callback(arr_substream_it_capture_cb[0].
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p_callback_param);
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}
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}
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return IRQ_HANDLED;
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}
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unsigned int snd_aw2_saa7146_get_hw_ptr_playback(struct snd_aw2_saa7146 *chip,
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int stream_number,
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unsigned char *start_addr,
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unsigned int buffer_size)
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{
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long pci_adp = 0;
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size_t ptr = 0;
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if (stream_number == 0) {
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pci_adp = READREG(PCI_ADP3);
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ptr = pci_adp - (long)start_addr;
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if (ptr == buffer_size)
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ptr = 0;
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}
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if (stream_number == 1) {
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pci_adp = READREG(PCI_ADP1);
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ptr = pci_adp - (size_t) start_addr;
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if (ptr == buffer_size)
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ptr = 0;
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}
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return ptr;
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}
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unsigned int snd_aw2_saa7146_get_hw_ptr_capture(struct snd_aw2_saa7146 *chip,
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int stream_number,
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unsigned char *start_addr,
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unsigned int buffer_size)
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{
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size_t pci_adp = 0;
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size_t ptr = 0;
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if (stream_number == 0) {
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pci_adp = READREG(PCI_ADP2);
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ptr = pci_adp - (size_t) start_addr;
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if (ptr == buffer_size)
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ptr = 0;
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}
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return ptr;
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}
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void snd_aw2_saa7146_use_digital_input(struct snd_aw2_saa7146 *chip,
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int use_digital)
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{
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/* FIXME: switch between analog and digital input does not always work.
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It can produce a kind of white noise. It seams that received data
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are inverted sometime (endian inversion). Why ? I don't know, maybe
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a problem of synchronization... However for the time being I have
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not found the problem. Workaround: switch again (and again) between
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digital and analog input until it works. */
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if (use_digital)
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WRITEREG(0x40, GPIO_CTRL);
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else
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WRITEREG(0x50, GPIO_CTRL);
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}
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int snd_aw2_saa7146_is_using_digital_input(struct snd_aw2_saa7146 *chip)
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{
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unsigned int reg_val = READREG(GPIO_CTRL);
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if ((reg_val & 0xFF) == 0x40)
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return 1;
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else
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return 0;
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}
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static int snd_aw2_saa7146_get_limit(int size)
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{
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int limitsize = 32;
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int limit = 0;
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while (limitsize < size) {
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limitsize *= 2;
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limit++;
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}
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return limit;
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}
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