1003 lines
30 KiB
C
1003 lines
30 KiB
C
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/*
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* Driver for Microsemi VSC85xx PHYs - MACsec support
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*
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* Author: Antoine Tenart
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* License: Dual MIT/GPL
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* Copyright (c) 2020 Microsemi Corporation
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*/
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#include <linux/phy.h>
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#include <dt-bindings/net/mscc-phy-vsc8531.h>
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#include <crypto/aes.h>
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#include <net/macsec.h>
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#include "mscc.h"
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#include "mscc_mac.h"
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#include "mscc_macsec.h"
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#include "mscc_fc_buffer.h"
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static u32 vsc8584_macsec_phy_read(struct phy_device *phydev,
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enum macsec_bank bank, u32 reg)
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{
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u32 val, val_l = 0, val_h = 0;
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unsigned long deadline;
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int rc;
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rc = phy_select_page(phydev, MSCC_PHY_PAGE_MACSEC);
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if (rc < 0)
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goto failed;
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__phy_write(phydev, MSCC_EXT_PAGE_MACSEC_20,
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MSCC_PHY_MACSEC_20_TARGET(bank >> 2));
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if (bank >> 2 == 0x1)
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/* non-MACsec access */
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bank &= 0x3;
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else
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bank = 0;
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__phy_write(phydev, MSCC_EXT_PAGE_MACSEC_19,
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MSCC_PHY_MACSEC_19_CMD | MSCC_PHY_MACSEC_19_READ |
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MSCC_PHY_MACSEC_19_REG_ADDR(reg) |
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MSCC_PHY_MACSEC_19_TARGET(bank));
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deadline = jiffies + msecs_to_jiffies(PROC_CMD_NCOMPLETED_TIMEOUT_MS);
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do {
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val = __phy_read(phydev, MSCC_EXT_PAGE_MACSEC_19);
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} while (time_before(jiffies, deadline) && !(val & MSCC_PHY_MACSEC_19_CMD));
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val_l = __phy_read(phydev, MSCC_EXT_PAGE_MACSEC_17);
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val_h = __phy_read(phydev, MSCC_EXT_PAGE_MACSEC_18);
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failed:
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phy_restore_page(phydev, rc, rc);
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return (val_h << 16) | val_l;
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}
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static void vsc8584_macsec_phy_write(struct phy_device *phydev,
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enum macsec_bank bank, u32 reg, u32 val)
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{
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unsigned long deadline;
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int rc;
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rc = phy_select_page(phydev, MSCC_PHY_PAGE_MACSEC);
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if (rc < 0)
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goto failed;
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__phy_write(phydev, MSCC_EXT_PAGE_MACSEC_20,
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MSCC_PHY_MACSEC_20_TARGET(bank >> 2));
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if ((bank >> 2 == 0x1) || (bank >> 2 == 0x3))
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bank &= 0x3;
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else
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/* MACsec access */
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bank = 0;
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__phy_write(phydev, MSCC_EXT_PAGE_MACSEC_17, (u16)val);
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__phy_write(phydev, MSCC_EXT_PAGE_MACSEC_18, (u16)(val >> 16));
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__phy_write(phydev, MSCC_EXT_PAGE_MACSEC_19,
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MSCC_PHY_MACSEC_19_CMD | MSCC_PHY_MACSEC_19_REG_ADDR(reg) |
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MSCC_PHY_MACSEC_19_TARGET(bank));
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deadline = jiffies + msecs_to_jiffies(PROC_CMD_NCOMPLETED_TIMEOUT_MS);
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do {
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val = __phy_read(phydev, MSCC_EXT_PAGE_MACSEC_19);
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} while (time_before(jiffies, deadline) && !(val & MSCC_PHY_MACSEC_19_CMD));
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failed:
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phy_restore_page(phydev, rc, rc);
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}
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static void vsc8584_macsec_classification(struct phy_device *phydev,
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enum macsec_bank bank)
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{
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/* enable VLAN tag parsing */
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vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_SAM_CP_TAG,
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MSCC_MS_SAM_CP_TAG_PARSE_STAG |
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MSCC_MS_SAM_CP_TAG_PARSE_QTAG |
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MSCC_MS_SAM_CP_TAG_PARSE_QINQ);
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}
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static void vsc8584_macsec_flow_default_action(struct phy_device *phydev,
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enum macsec_bank bank,
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bool block)
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{
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u32 port = (bank == MACSEC_INGR) ?
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MSCC_MS_PORT_UNCONTROLLED : MSCC_MS_PORT_COMMON;
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u32 action = MSCC_MS_FLOW_BYPASS;
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if (block)
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action = MSCC_MS_FLOW_DROP;
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vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_SAM_NM_FLOW_NCP,
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/* MACsec untagged */
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MSCC_MS_SAM_NM_FLOW_NCP_UNTAGGED_FLOW_TYPE(action) |
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MSCC_MS_SAM_NM_FLOW_NCP_UNTAGGED_DROP_ACTION(MSCC_MS_ACTION_DROP) |
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MSCC_MS_SAM_NM_FLOW_NCP_UNTAGGED_DEST_PORT(port) |
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/* MACsec tagged */
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MSCC_MS_SAM_NM_FLOW_NCP_TAGGED_FLOW_TYPE(action) |
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MSCC_MS_SAM_NM_FLOW_NCP_TAGGED_DROP_ACTION(MSCC_MS_ACTION_DROP) |
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MSCC_MS_SAM_NM_FLOW_NCP_TAGGED_DEST_PORT(port) |
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/* Bad tag */
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MSCC_MS_SAM_NM_FLOW_NCP_BADTAG_FLOW_TYPE(action) |
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MSCC_MS_SAM_NM_FLOW_NCP_BADTAG_DROP_ACTION(MSCC_MS_ACTION_DROP) |
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MSCC_MS_SAM_NM_FLOW_NCP_BADTAG_DEST_PORT(port) |
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/* Kay tag */
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MSCC_MS_SAM_NM_FLOW_NCP_KAY_FLOW_TYPE(action) |
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MSCC_MS_SAM_NM_FLOW_NCP_KAY_DROP_ACTION(MSCC_MS_ACTION_DROP) |
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MSCC_MS_SAM_NM_FLOW_NCP_KAY_DEST_PORT(port));
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vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_SAM_NM_FLOW_CP,
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/* MACsec untagged */
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MSCC_MS_SAM_NM_FLOW_NCP_UNTAGGED_FLOW_TYPE(action) |
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MSCC_MS_SAM_NM_FLOW_CP_UNTAGGED_DROP_ACTION(MSCC_MS_ACTION_DROP) |
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MSCC_MS_SAM_NM_FLOW_CP_UNTAGGED_DEST_PORT(port) |
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/* MACsec tagged */
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MSCC_MS_SAM_NM_FLOW_NCP_TAGGED_FLOW_TYPE(action) |
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MSCC_MS_SAM_NM_FLOW_CP_TAGGED_DROP_ACTION(MSCC_MS_ACTION_DROP) |
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MSCC_MS_SAM_NM_FLOW_CP_TAGGED_DEST_PORT(port) |
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/* Bad tag */
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MSCC_MS_SAM_NM_FLOW_NCP_BADTAG_FLOW_TYPE(action) |
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MSCC_MS_SAM_NM_FLOW_CP_BADTAG_DROP_ACTION(MSCC_MS_ACTION_DROP) |
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MSCC_MS_SAM_NM_FLOW_CP_BADTAG_DEST_PORT(port) |
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/* Kay tag */
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MSCC_MS_SAM_NM_FLOW_NCP_KAY_FLOW_TYPE(action) |
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MSCC_MS_SAM_NM_FLOW_CP_KAY_DROP_ACTION(MSCC_MS_ACTION_DROP) |
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MSCC_MS_SAM_NM_FLOW_CP_KAY_DEST_PORT(port));
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}
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static void vsc8584_macsec_integrity_checks(struct phy_device *phydev,
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enum macsec_bank bank)
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{
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u32 val;
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if (bank != MACSEC_INGR)
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return;
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/* Set default rules to pass unmatched frames */
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val = vsc8584_macsec_phy_read(phydev, bank,
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MSCC_MS_PARAMS2_IG_CC_CONTROL);
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val |= MSCC_MS_PARAMS2_IG_CC_CONTROL_NON_MATCH_CTRL_ACT |
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MSCC_MS_PARAMS2_IG_CC_CONTROL_NON_MATCH_ACT;
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vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_PARAMS2_IG_CC_CONTROL,
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val);
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vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_PARAMS2_IG_CP_TAG,
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MSCC_MS_PARAMS2_IG_CP_TAG_PARSE_STAG |
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MSCC_MS_PARAMS2_IG_CP_TAG_PARSE_QTAG |
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MSCC_MS_PARAMS2_IG_CP_TAG_PARSE_QINQ);
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}
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static void vsc8584_macsec_block_init(struct phy_device *phydev,
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enum macsec_bank bank)
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{
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u32 val;
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int i;
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vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_ENA_CFG,
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MSCC_MS_ENA_CFG_SW_RST |
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MSCC_MS_ENA_CFG_MACSEC_BYPASS_ENA);
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/* Set the MACsec block out of s/w reset and enable clocks */
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vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_ENA_CFG,
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MSCC_MS_ENA_CFG_CLK_ENA);
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vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_STATUS_CONTEXT_CTRL,
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bank == MACSEC_INGR ? 0xe5880214 : 0xe5880218);
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vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_MISC_CONTROL,
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MSCC_MS_MISC_CONTROL_MC_LATENCY_FIX(bank == MACSEC_INGR ? 57 : 40) |
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MSCC_MS_MISC_CONTROL_XFORM_REC_SIZE(bank == MACSEC_INGR ? 1 : 2));
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/* Clear the counters */
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val = vsc8584_macsec_phy_read(phydev, bank, MSCC_MS_COUNT_CONTROL);
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val |= MSCC_MS_COUNT_CONTROL_AUTO_CNTR_RESET;
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vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_COUNT_CONTROL, val);
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/* Enable octet increment mode */
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vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_PP_CTRL,
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MSCC_MS_PP_CTRL_MACSEC_OCTET_INCR_MODE);
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vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_BLOCK_CTX_UPDATE, 0x3);
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val = vsc8584_macsec_phy_read(phydev, bank, MSCC_MS_COUNT_CONTROL);
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val |= MSCC_MS_COUNT_CONTROL_RESET_ALL;
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vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_COUNT_CONTROL, val);
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/* Set the MTU */
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vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_NON_VLAN_MTU_CHECK,
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MSCC_MS_NON_VLAN_MTU_CHECK_NV_MTU_COMPARE(32761) |
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MSCC_MS_NON_VLAN_MTU_CHECK_NV_MTU_COMP_DROP);
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for (i = 0; i < 8; i++)
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vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_VLAN_MTU_CHECK(i),
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MSCC_MS_VLAN_MTU_CHECK_MTU_COMPARE(32761) |
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MSCC_MS_VLAN_MTU_CHECK_MTU_COMP_DROP);
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if (bank == MACSEC_EGR) {
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val = vsc8584_macsec_phy_read(phydev, bank, MSCC_MS_INTR_CTRL_STATUS);
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val &= ~MSCC_MS_INTR_CTRL_STATUS_INTR_ENABLE_M;
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vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_INTR_CTRL_STATUS, val);
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vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_FC_CFG,
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MSCC_MS_FC_CFG_FCBUF_ENA |
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MSCC_MS_FC_CFG_LOW_THRESH(0x1) |
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MSCC_MS_FC_CFG_HIGH_THRESH(0x4) |
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MSCC_MS_FC_CFG_LOW_BYTES_VAL(0x4) |
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MSCC_MS_FC_CFG_HIGH_BYTES_VAL(0x6));
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}
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vsc8584_macsec_classification(phydev, bank);
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vsc8584_macsec_flow_default_action(phydev, bank, false);
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vsc8584_macsec_integrity_checks(phydev, bank);
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/* Enable the MACsec block */
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vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_ENA_CFG,
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MSCC_MS_ENA_CFG_CLK_ENA |
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MSCC_MS_ENA_CFG_MACSEC_ENA |
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MSCC_MS_ENA_CFG_MACSEC_SPEED_MODE(0x5));
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}
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static void vsc8584_macsec_mac_init(struct phy_device *phydev,
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enum macsec_bank bank)
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{
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u32 val;
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int i;
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/* Clear host & line stats */
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for (i = 0; i < 36; i++)
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vsc8584_macsec_phy_write(phydev, bank, 0x1c + i, 0);
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val = vsc8584_macsec_phy_read(phydev, bank,
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MSCC_MAC_PAUSE_CFG_TX_FRAME_CTRL);
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val &= ~MSCC_MAC_PAUSE_CFG_TX_FRAME_CTRL_PAUSE_MODE_M;
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val |= MSCC_MAC_PAUSE_CFG_TX_FRAME_CTRL_PAUSE_MODE(2) |
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MSCC_MAC_PAUSE_CFG_TX_FRAME_CTRL_PAUSE_VALUE(0xffff);
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vsc8584_macsec_phy_write(phydev, bank,
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MSCC_MAC_PAUSE_CFG_TX_FRAME_CTRL, val);
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val = vsc8584_macsec_phy_read(phydev, bank,
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MSCC_MAC_PAUSE_CFG_TX_FRAME_CTRL_2);
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val |= 0xffff;
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vsc8584_macsec_phy_write(phydev, bank,
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MSCC_MAC_PAUSE_CFG_TX_FRAME_CTRL_2, val);
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val = vsc8584_macsec_phy_read(phydev, bank,
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MSCC_MAC_PAUSE_CFG_RX_FRAME_CTRL);
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if (bank == HOST_MAC)
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val |= MSCC_MAC_PAUSE_CFG_RX_FRAME_CTRL_PAUSE_TIMER_ENA |
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MSCC_MAC_PAUSE_CFG_RX_FRAME_CTRL_PAUSE_FRAME_DROP_ENA;
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else
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val |= MSCC_MAC_PAUSE_CFG_RX_FRAME_CTRL_PAUSE_REACT_ENA |
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MSCC_MAC_PAUSE_CFG_RX_FRAME_CTRL_PAUSE_FRAME_DROP_ENA |
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MSCC_MAC_PAUSE_CFG_RX_FRAME_CTRL_PAUSE_MODE |
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MSCC_MAC_PAUSE_CFG_RX_FRAME_CTRL_EARLY_PAUSE_DETECT_ENA;
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vsc8584_macsec_phy_write(phydev, bank,
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MSCC_MAC_PAUSE_CFG_RX_FRAME_CTRL, val);
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vsc8584_macsec_phy_write(phydev, bank, MSCC_MAC_CFG_PKTINF_CFG,
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MSCC_MAC_CFG_PKTINF_CFG_STRIP_FCS_ENA |
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MSCC_MAC_CFG_PKTINF_CFG_INSERT_FCS_ENA |
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MSCC_MAC_CFG_PKTINF_CFG_LPI_RELAY_ENA |
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MSCC_MAC_CFG_PKTINF_CFG_STRIP_PREAMBLE_ENA |
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MSCC_MAC_CFG_PKTINF_CFG_INSERT_PREAMBLE_ENA |
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(bank == HOST_MAC ?
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MSCC_MAC_CFG_PKTINF_CFG_ENABLE_TX_PADDING : 0) |
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(IS_ENABLED(CONFIG_NETWORK_PHY_TIMESTAMPING) ?
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MSCC_MAC_CFG_PKTINF_CFG_MACSEC_BYPASS_NUM_PTP_STALL_CLKS(0x8) : 0));
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val = vsc8584_macsec_phy_read(phydev, bank, MSCC_MAC_CFG_MODE_CFG);
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val &= ~MSCC_MAC_CFG_MODE_CFG_DISABLE_DIC;
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vsc8584_macsec_phy_write(phydev, bank, MSCC_MAC_CFG_MODE_CFG, val);
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val = vsc8584_macsec_phy_read(phydev, bank, MSCC_MAC_CFG_MAXLEN_CFG);
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val &= ~MSCC_MAC_CFG_MAXLEN_CFG_MAX_LEN_M;
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val |= MSCC_MAC_CFG_MAXLEN_CFG_MAX_LEN(10240);
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vsc8584_macsec_phy_write(phydev, bank, MSCC_MAC_CFG_MAXLEN_CFG, val);
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vsc8584_macsec_phy_write(phydev, bank, MSCC_MAC_CFG_ADV_CHK_CFG,
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MSCC_MAC_CFG_ADV_CHK_CFG_SFD_CHK_ENA |
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MSCC_MAC_CFG_ADV_CHK_CFG_PRM_CHK_ENA |
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MSCC_MAC_CFG_ADV_CHK_CFG_OOR_ERR_ENA |
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MSCC_MAC_CFG_ADV_CHK_CFG_INR_ERR_ENA);
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val = vsc8584_macsec_phy_read(phydev, bank, MSCC_MAC_CFG_LFS_CFG);
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val &= ~MSCC_MAC_CFG_LFS_CFG_LFS_MODE_ENA;
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vsc8584_macsec_phy_write(phydev, bank, MSCC_MAC_CFG_LFS_CFG, val);
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vsc8584_macsec_phy_write(phydev, bank, MSCC_MAC_CFG_ENA_CFG,
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MSCC_MAC_CFG_ENA_CFG_RX_CLK_ENA |
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MSCC_MAC_CFG_ENA_CFG_TX_CLK_ENA |
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MSCC_MAC_CFG_ENA_CFG_RX_ENA |
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MSCC_MAC_CFG_ENA_CFG_TX_ENA);
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}
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/* Must be called with mdio_lock taken */
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static int __vsc8584_macsec_init(struct phy_device *phydev)
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{
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struct vsc8531_private *priv = phydev->priv;
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enum macsec_bank proc_bank;
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u32 val;
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vsc8584_macsec_block_init(phydev, MACSEC_INGR);
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vsc8584_macsec_block_init(phydev, MACSEC_EGR);
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vsc8584_macsec_mac_init(phydev, HOST_MAC);
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vsc8584_macsec_mac_init(phydev, LINE_MAC);
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vsc8584_macsec_phy_write(phydev, FC_BUFFER,
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MSCC_FCBUF_FC_READ_THRESH_CFG,
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MSCC_FCBUF_FC_READ_THRESH_CFG_TX_THRESH(4) |
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MSCC_FCBUF_FC_READ_THRESH_CFG_RX_THRESH(5));
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val = vsc8584_macsec_phy_read(phydev, FC_BUFFER, MSCC_FCBUF_MODE_CFG);
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val |= MSCC_FCBUF_MODE_CFG_PAUSE_GEN_ENA |
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MSCC_FCBUF_MODE_CFG_RX_PPM_RATE_ADAPT_ENA |
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MSCC_FCBUF_MODE_CFG_TX_PPM_RATE_ADAPT_ENA;
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vsc8584_macsec_phy_write(phydev, FC_BUFFER, MSCC_FCBUF_MODE_CFG, val);
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vsc8584_macsec_phy_write(phydev, FC_BUFFER, MSCC_FCBUF_PPM_RATE_ADAPT_THRESH_CFG,
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MSCC_FCBUF_PPM_RATE_ADAPT_THRESH_CFG_TX_THRESH(8) |
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MSCC_FCBUF_PPM_RATE_ADAPT_THRESH_CFG_TX_OFFSET(9));
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val = vsc8584_macsec_phy_read(phydev, FC_BUFFER,
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MSCC_FCBUF_TX_DATA_QUEUE_CFG);
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val &= ~(MSCC_FCBUF_TX_DATA_QUEUE_CFG_START_M |
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MSCC_FCBUF_TX_DATA_QUEUE_CFG_END_M);
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val |= MSCC_FCBUF_TX_DATA_QUEUE_CFG_START(0) |
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MSCC_FCBUF_TX_DATA_QUEUE_CFG_END(5119);
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vsc8584_macsec_phy_write(phydev, FC_BUFFER,
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MSCC_FCBUF_TX_DATA_QUEUE_CFG, val);
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val = vsc8584_macsec_phy_read(phydev, FC_BUFFER, MSCC_FCBUF_ENA_CFG);
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val |= MSCC_FCBUF_ENA_CFG_TX_ENA | MSCC_FCBUF_ENA_CFG_RX_ENA;
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vsc8584_macsec_phy_write(phydev, FC_BUFFER, MSCC_FCBUF_ENA_CFG, val);
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proc_bank = (priv->addr < 2) ? PROC_0 : PROC_2;
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val = vsc8584_macsec_phy_read(phydev, proc_bank,
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MSCC_PROC_IP_1588_TOP_CFG_STAT_MODE_CTL);
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val &= ~MSCC_PROC_IP_1588_TOP_CFG_STAT_MODE_CTL_PROTOCOL_MODE_M;
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val |= MSCC_PROC_IP_1588_TOP_CFG_STAT_MODE_CTL_PROTOCOL_MODE(4);
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vsc8584_macsec_phy_write(phydev, proc_bank,
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MSCC_PROC_IP_1588_TOP_CFG_STAT_MODE_CTL, val);
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return 0;
|
|
}
|
|
|
|
static void vsc8584_macsec_flow(struct phy_device *phydev,
|
|
struct macsec_flow *flow)
|
|
{
|
|
struct vsc8531_private *priv = phydev->priv;
|
|
enum macsec_bank bank = flow->bank;
|
|
u32 val, match = 0, mask = 0, action = 0, idx = flow->index;
|
|
|
|
if (flow->match.tagged)
|
|
match |= MSCC_MS_SAM_MISC_MATCH_TAGGED;
|
|
if (flow->match.untagged)
|
|
match |= MSCC_MS_SAM_MISC_MATCH_UNTAGGED;
|
|
|
|
if (bank == MACSEC_INGR && flow->assoc_num >= 0) {
|
|
match |= MSCC_MS_SAM_MISC_MATCH_AN(flow->assoc_num);
|
|
mask |= MSCC_MS_SAM_MASK_AN_MASK(0x3);
|
|
}
|
|
|
|
if (bank == MACSEC_INGR && flow->match.sci && flow->rx_sa->sc->sci) {
|
|
u64 sci = (__force u64)flow->rx_sa->sc->sci;
|
|
|
|
match |= MSCC_MS_SAM_MISC_MATCH_TCI(BIT(3));
|
|
mask |= MSCC_MS_SAM_MASK_TCI_MASK(BIT(3)) |
|
|
MSCC_MS_SAM_MASK_SCI_MASK;
|
|
|
|
vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_SAM_MATCH_SCI_LO(idx),
|
|
lower_32_bits(sci));
|
|
vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_SAM_MATCH_SCI_HI(idx),
|
|
upper_32_bits(sci));
|
|
}
|
|
|
|
if (flow->match.etype) {
|
|
mask |= MSCC_MS_SAM_MASK_MAC_ETYPE_MASK;
|
|
|
|
vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_SAM_MAC_SA_MATCH_HI(idx),
|
|
MSCC_MS_SAM_MAC_SA_MATCH_HI_ETYPE((__force u32)htons(flow->etype)));
|
|
}
|
|
|
|
match |= MSCC_MS_SAM_MISC_MATCH_PRIORITY(flow->priority);
|
|
|
|
vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_SAM_MISC_MATCH(idx), match);
|
|
vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_SAM_MASK(idx), mask);
|
|
|
|
/* Action for matching packets */
|
|
if (flow->action.drop)
|
|
action = MSCC_MS_FLOW_DROP;
|
|
else if (flow->action.bypass || flow->port == MSCC_MS_PORT_UNCONTROLLED)
|
|
action = MSCC_MS_FLOW_BYPASS;
|
|
else
|
|
action = (bank == MACSEC_INGR) ?
|
|
MSCC_MS_FLOW_INGRESS : MSCC_MS_FLOW_EGRESS;
|
|
|
|
val = MSCC_MS_SAM_FLOW_CTRL_FLOW_TYPE(action) |
|
|
MSCC_MS_SAM_FLOW_CTRL_DROP_ACTION(MSCC_MS_ACTION_DROP) |
|
|
MSCC_MS_SAM_FLOW_CTRL_DEST_PORT(flow->port);
|
|
|
|
if (action == MSCC_MS_FLOW_BYPASS)
|
|
goto write_ctrl;
|
|
|
|
if (bank == MACSEC_INGR) {
|
|
if (priv->secy->replay_protect)
|
|
val |= MSCC_MS_SAM_FLOW_CTRL_REPLAY_PROTECT;
|
|
if (priv->secy->validate_frames == MACSEC_VALIDATE_STRICT)
|
|
val |= MSCC_MS_SAM_FLOW_CTRL_VALIDATE_FRAMES(MSCC_MS_VALIDATE_STRICT);
|
|
else if (priv->secy->validate_frames == MACSEC_VALIDATE_CHECK)
|
|
val |= MSCC_MS_SAM_FLOW_CTRL_VALIDATE_FRAMES(MSCC_MS_VALIDATE_CHECK);
|
|
} else if (bank == MACSEC_EGR) {
|
|
if (priv->secy->protect_frames)
|
|
val |= MSCC_MS_SAM_FLOW_CTRL_PROTECT_FRAME;
|
|
if (priv->secy->tx_sc.encrypt)
|
|
val |= MSCC_MS_SAM_FLOW_CTRL_CONF_PROTECT;
|
|
if (priv->secy->tx_sc.send_sci)
|
|
val |= MSCC_MS_SAM_FLOW_CTRL_INCLUDE_SCI;
|
|
}
|
|
|
|
write_ctrl:
|
|
vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_SAM_FLOW_CTRL(idx), val);
|
|
}
|
|
|
|
static struct macsec_flow *vsc8584_macsec_find_flow(struct macsec_context *ctx,
|
|
enum macsec_bank bank)
|
|
{
|
|
struct vsc8531_private *priv = ctx->phydev->priv;
|
|
struct macsec_flow *pos, *tmp;
|
|
|
|
list_for_each_entry_safe(pos, tmp, &priv->macsec_flows, list)
|
|
if (pos->assoc_num == ctx->sa.assoc_num && pos->bank == bank)
|
|
return pos;
|
|
|
|
return ERR_PTR(-ENOENT);
|
|
}
|
|
|
|
static void vsc8584_macsec_flow_enable(struct phy_device *phydev,
|
|
struct macsec_flow *flow)
|
|
{
|
|
enum macsec_bank bank = flow->bank;
|
|
u32 val, idx = flow->index;
|
|
|
|
if ((flow->bank == MACSEC_INGR && flow->rx_sa && !flow->rx_sa->active) ||
|
|
(flow->bank == MACSEC_EGR && flow->tx_sa && !flow->tx_sa->active))
|
|
return;
|
|
|
|
/* Enable */
|
|
vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_SAM_ENTRY_SET1, BIT(idx));
|
|
|
|
/* Set in-use */
|
|
val = vsc8584_macsec_phy_read(phydev, bank, MSCC_MS_SAM_FLOW_CTRL(idx));
|
|
val |= MSCC_MS_SAM_FLOW_CTRL_SA_IN_USE;
|
|
vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_SAM_FLOW_CTRL(idx), val);
|
|
}
|
|
|
|
static void vsc8584_macsec_flow_disable(struct phy_device *phydev,
|
|
struct macsec_flow *flow)
|
|
{
|
|
enum macsec_bank bank = flow->bank;
|
|
u32 val, idx = flow->index;
|
|
|
|
/* Disable */
|
|
vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_SAM_ENTRY_CLEAR1, BIT(idx));
|
|
|
|
/* Clear in-use */
|
|
val = vsc8584_macsec_phy_read(phydev, bank, MSCC_MS_SAM_FLOW_CTRL(idx));
|
|
val &= ~MSCC_MS_SAM_FLOW_CTRL_SA_IN_USE;
|
|
vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_SAM_FLOW_CTRL(idx), val);
|
|
}
|
|
|
|
static u32 vsc8584_macsec_flow_context_id(struct macsec_flow *flow)
|
|
{
|
|
if (flow->bank == MACSEC_INGR)
|
|
return flow->index + MSCC_MS_MAX_FLOWS;
|
|
|
|
return flow->index;
|
|
}
|
|
|
|
/* Derive the AES key to get a key for the hash autentication */
|
|
static int vsc8584_macsec_derive_key(const u8 key[MACSEC_MAX_KEY_LEN],
|
|
u16 key_len, u8 hkey[16])
|
|
{
|
|
const u8 input[AES_BLOCK_SIZE] = {0};
|
|
struct crypto_aes_ctx ctx;
|
|
int ret;
|
|
|
|
ret = aes_expandkey(&ctx, key, key_len);
|
|
if (ret)
|
|
return ret;
|
|
|
|
aes_encrypt(&ctx, hkey, input);
|
|
memzero_explicit(&ctx, sizeof(ctx));
|
|
return 0;
|
|
}
|
|
|
|
static int vsc8584_macsec_transformation(struct phy_device *phydev,
|
|
struct macsec_flow *flow)
|
|
{
|
|
struct vsc8531_private *priv = phydev->priv;
|
|
enum macsec_bank bank = flow->bank;
|
|
int i, ret, index = flow->index;
|
|
u32 rec = 0, control = 0;
|
|
u8 hkey[16];
|
|
u64 sci;
|
|
|
|
ret = vsc8584_macsec_derive_key(flow->key, priv->secy->key_len, hkey);
|
|
if (ret)
|
|
return ret;
|
|
|
|
switch (priv->secy->key_len) {
|
|
case 16:
|
|
control |= CONTROL_CRYPTO_ALG(CTRYPTO_ALG_AES_CTR_128);
|
|
break;
|
|
case 32:
|
|
control |= CONTROL_CRYPTO_ALG(CTRYPTO_ALG_AES_CTR_256);
|
|
break;
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
|
|
control |= (bank == MACSEC_EGR) ?
|
|
(CONTROL_TYPE_EGRESS | CONTROL_AN(priv->secy->tx_sc.encoding_sa)) :
|
|
(CONTROL_TYPE_INGRESS | CONTROL_SEQ_MASK);
|
|
|
|
control |= CONTROL_UPDATE_SEQ | CONTROL_ENCRYPT_AUTH | CONTROL_KEY_IN_CTX |
|
|
CONTROL_IV0 | CONTROL_IV1 | CONTROL_IV_IN_SEQ |
|
|
CONTROL_DIGEST_TYPE(0x2) | CONTROL_SEQ_TYPE(0x1) |
|
|
CONTROL_AUTH_ALG(AUTH_ALG_AES_GHAS) | CONTROL_CONTEXT_ID;
|
|
|
|
/* Set the control word */
|
|
vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_XFORM_REC(index, rec++),
|
|
control);
|
|
|
|
/* Set the context ID. Must be unique. */
|
|
vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_XFORM_REC(index, rec++),
|
|
vsc8584_macsec_flow_context_id(flow));
|
|
|
|
/* Set the encryption/decryption key */
|
|
for (i = 0; i < priv->secy->key_len / sizeof(u32); i++)
|
|
vsc8584_macsec_phy_write(phydev, bank,
|
|
MSCC_MS_XFORM_REC(index, rec++),
|
|
((u32 *)flow->key)[i]);
|
|
|
|
/* Set the authentication key */
|
|
for (i = 0; i < 4; i++)
|
|
vsc8584_macsec_phy_write(phydev, bank,
|
|
MSCC_MS_XFORM_REC(index, rec++),
|
|
((u32 *)hkey)[i]);
|
|
|
|
/* Initial sequence number */
|
|
vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_XFORM_REC(index, rec++),
|
|
bank == MACSEC_INGR ?
|
|
flow->rx_sa->next_pn : flow->tx_sa->next_pn);
|
|
|
|
if (bank == MACSEC_INGR)
|
|
/* Set the mask (replay window size) */
|
|
vsc8584_macsec_phy_write(phydev, bank,
|
|
MSCC_MS_XFORM_REC(index, rec++),
|
|
priv->secy->replay_window);
|
|
|
|
/* Set the input vectors */
|
|
sci = (__force u64)(bank == MACSEC_INGR ? flow->rx_sa->sc->sci : priv->secy->sci);
|
|
vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_XFORM_REC(index, rec++),
|
|
lower_32_bits(sci));
|
|
vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_XFORM_REC(index, rec++),
|
|
upper_32_bits(sci));
|
|
|
|
while (rec < 20)
|
|
vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_XFORM_REC(index, rec++),
|
|
0);
|
|
|
|
flow->has_transformation = true;
|
|
return 0;
|
|
}
|
|
|
|
static struct macsec_flow *vsc8584_macsec_alloc_flow(struct vsc8531_private *priv,
|
|
enum macsec_bank bank)
|
|
{
|
|
unsigned long *bitmap = bank == MACSEC_INGR ?
|
|
&priv->ingr_flows : &priv->egr_flows;
|
|
struct macsec_flow *flow;
|
|
int index;
|
|
|
|
index = find_first_zero_bit(bitmap, MSCC_MS_MAX_FLOWS);
|
|
|
|
if (index == MSCC_MS_MAX_FLOWS)
|
|
return ERR_PTR(-ENOMEM);
|
|
|
|
flow = kzalloc(sizeof(*flow), GFP_KERNEL);
|
|
if (!flow)
|
|
return ERR_PTR(-ENOMEM);
|
|
|
|
set_bit(index, bitmap);
|
|
flow->index = index;
|
|
flow->bank = bank;
|
|
flow->priority = 8;
|
|
flow->assoc_num = -1;
|
|
|
|
list_add_tail(&flow->list, &priv->macsec_flows);
|
|
return flow;
|
|
}
|
|
|
|
static void vsc8584_macsec_free_flow(struct vsc8531_private *priv,
|
|
struct macsec_flow *flow)
|
|
{
|
|
unsigned long *bitmap = flow->bank == MACSEC_INGR ?
|
|
&priv->ingr_flows : &priv->egr_flows;
|
|
|
|
list_del(&flow->list);
|
|
clear_bit(flow->index, bitmap);
|
|
memzero_explicit(flow->key, sizeof(flow->key));
|
|
kfree(flow);
|
|
}
|
|
|
|
static int vsc8584_macsec_add_flow(struct phy_device *phydev,
|
|
struct macsec_flow *flow, bool update)
|
|
{
|
|
int ret;
|
|
|
|
flow->port = MSCC_MS_PORT_CONTROLLED;
|
|
vsc8584_macsec_flow(phydev, flow);
|
|
|
|
if (update)
|
|
return 0;
|
|
|
|
ret = vsc8584_macsec_transformation(phydev, flow);
|
|
if (ret) {
|
|
vsc8584_macsec_free_flow(phydev->priv, flow);
|
|
return ret;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int vsc8584_macsec_default_flows(struct phy_device *phydev)
|
|
{
|
|
struct macsec_flow *flow;
|
|
|
|
/* Add a rule to let the MKA traffic go through, ingress */
|
|
flow = vsc8584_macsec_alloc_flow(phydev->priv, MACSEC_INGR);
|
|
if (IS_ERR(flow))
|
|
return PTR_ERR(flow);
|
|
|
|
flow->priority = 15;
|
|
flow->port = MSCC_MS_PORT_UNCONTROLLED;
|
|
flow->match.tagged = 1;
|
|
flow->match.untagged = 1;
|
|
flow->match.etype = 1;
|
|
flow->etype = ETH_P_PAE;
|
|
flow->action.bypass = 1;
|
|
|
|
vsc8584_macsec_flow(phydev, flow);
|
|
vsc8584_macsec_flow_enable(phydev, flow);
|
|
|
|
/* Add a rule to let the MKA traffic go through, egress */
|
|
flow = vsc8584_macsec_alloc_flow(phydev->priv, MACSEC_EGR);
|
|
if (IS_ERR(flow))
|
|
return PTR_ERR(flow);
|
|
|
|
flow->priority = 15;
|
|
flow->port = MSCC_MS_PORT_COMMON;
|
|
flow->match.untagged = 1;
|
|
flow->match.etype = 1;
|
|
flow->etype = ETH_P_PAE;
|
|
flow->action.bypass = 1;
|
|
|
|
vsc8584_macsec_flow(phydev, flow);
|
|
vsc8584_macsec_flow_enable(phydev, flow);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void vsc8584_macsec_del_flow(struct phy_device *phydev,
|
|
struct macsec_flow *flow)
|
|
{
|
|
vsc8584_macsec_flow_disable(phydev, flow);
|
|
vsc8584_macsec_free_flow(phydev->priv, flow);
|
|
}
|
|
|
|
static int __vsc8584_macsec_add_rxsa(struct macsec_context *ctx,
|
|
struct macsec_flow *flow, bool update)
|
|
{
|
|
struct phy_device *phydev = ctx->phydev;
|
|
struct vsc8531_private *priv = phydev->priv;
|
|
|
|
flow->assoc_num = ctx->sa.assoc_num;
|
|
flow->rx_sa = ctx->sa.rx_sa;
|
|
|
|
/* Always match tagged packets on ingress */
|
|
flow->match.tagged = 1;
|
|
flow->match.sci = 1;
|
|
|
|
if (priv->secy->validate_frames != MACSEC_VALIDATE_DISABLED)
|
|
flow->match.untagged = 1;
|
|
|
|
return vsc8584_macsec_add_flow(phydev, flow, update);
|
|
}
|
|
|
|
static int __vsc8584_macsec_add_txsa(struct macsec_context *ctx,
|
|
struct macsec_flow *flow, bool update)
|
|
{
|
|
flow->assoc_num = ctx->sa.assoc_num;
|
|
flow->tx_sa = ctx->sa.tx_sa;
|
|
|
|
/* Always match untagged packets on egress */
|
|
flow->match.untagged = 1;
|
|
|
|
return vsc8584_macsec_add_flow(ctx->phydev, flow, update);
|
|
}
|
|
|
|
static int vsc8584_macsec_dev_open(struct macsec_context *ctx)
|
|
{
|
|
struct vsc8531_private *priv = ctx->phydev->priv;
|
|
struct macsec_flow *flow, *tmp;
|
|
|
|
list_for_each_entry_safe(flow, tmp, &priv->macsec_flows, list)
|
|
vsc8584_macsec_flow_enable(ctx->phydev, flow);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int vsc8584_macsec_dev_stop(struct macsec_context *ctx)
|
|
{
|
|
struct vsc8531_private *priv = ctx->phydev->priv;
|
|
struct macsec_flow *flow, *tmp;
|
|
|
|
list_for_each_entry_safe(flow, tmp, &priv->macsec_flows, list)
|
|
vsc8584_macsec_flow_disable(ctx->phydev, flow);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int vsc8584_macsec_add_secy(struct macsec_context *ctx)
|
|
{
|
|
struct vsc8531_private *priv = ctx->phydev->priv;
|
|
struct macsec_secy *secy = ctx->secy;
|
|
|
|
if (priv->secy)
|
|
return -EEXIST;
|
|
|
|
priv->secy = secy;
|
|
|
|
vsc8584_macsec_flow_default_action(ctx->phydev, MACSEC_EGR,
|
|
secy->validate_frames != MACSEC_VALIDATE_DISABLED);
|
|
vsc8584_macsec_flow_default_action(ctx->phydev, MACSEC_INGR,
|
|
secy->validate_frames != MACSEC_VALIDATE_DISABLED);
|
|
|
|
return vsc8584_macsec_default_flows(ctx->phydev);
|
|
}
|
|
|
|
static int vsc8584_macsec_del_secy(struct macsec_context *ctx)
|
|
{
|
|
struct vsc8531_private *priv = ctx->phydev->priv;
|
|
struct macsec_flow *flow, *tmp;
|
|
|
|
list_for_each_entry_safe(flow, tmp, &priv->macsec_flows, list)
|
|
vsc8584_macsec_del_flow(ctx->phydev, flow);
|
|
|
|
vsc8584_macsec_flow_default_action(ctx->phydev, MACSEC_EGR, false);
|
|
vsc8584_macsec_flow_default_action(ctx->phydev, MACSEC_INGR, false);
|
|
|
|
priv->secy = NULL;
|
|
return 0;
|
|
}
|
|
|
|
static int vsc8584_macsec_upd_secy(struct macsec_context *ctx)
|
|
{
|
|
vsc8584_macsec_del_secy(ctx);
|
|
return vsc8584_macsec_add_secy(ctx);
|
|
}
|
|
|
|
static int vsc8584_macsec_add_rxsc(struct macsec_context *ctx)
|
|
{
|
|
/* Nothing to do */
|
|
return 0;
|
|
}
|
|
|
|
static int vsc8584_macsec_upd_rxsc(struct macsec_context *ctx)
|
|
{
|
|
return -EOPNOTSUPP;
|
|
}
|
|
|
|
static int vsc8584_macsec_del_rxsc(struct macsec_context *ctx)
|
|
{
|
|
struct vsc8531_private *priv = ctx->phydev->priv;
|
|
struct macsec_flow *flow, *tmp;
|
|
|
|
list_for_each_entry_safe(flow, tmp, &priv->macsec_flows, list) {
|
|
if (flow->bank == MACSEC_INGR && flow->rx_sa &&
|
|
flow->rx_sa->sc->sci == ctx->rx_sc->sci)
|
|
vsc8584_macsec_del_flow(ctx->phydev, flow);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int vsc8584_macsec_add_rxsa(struct macsec_context *ctx)
|
|
{
|
|
struct phy_device *phydev = ctx->phydev;
|
|
struct vsc8531_private *priv = phydev->priv;
|
|
struct macsec_flow *flow;
|
|
int ret;
|
|
|
|
flow = vsc8584_macsec_alloc_flow(priv, MACSEC_INGR);
|
|
if (IS_ERR(flow))
|
|
return PTR_ERR(flow);
|
|
|
|
memcpy(flow->key, ctx->sa.key, priv->secy->key_len);
|
|
|
|
ret = __vsc8584_macsec_add_rxsa(ctx, flow, false);
|
|
if (ret)
|
|
return ret;
|
|
|
|
vsc8584_macsec_flow_enable(phydev, flow);
|
|
return 0;
|
|
}
|
|
|
|
static int vsc8584_macsec_upd_rxsa(struct macsec_context *ctx)
|
|
{
|
|
struct macsec_flow *flow;
|
|
int ret;
|
|
|
|
flow = vsc8584_macsec_find_flow(ctx, MACSEC_INGR);
|
|
if (IS_ERR(flow))
|
|
return PTR_ERR(flow);
|
|
|
|
/* Make sure the flow is disabled before updating it */
|
|
vsc8584_macsec_flow_disable(ctx->phydev, flow);
|
|
|
|
ret = __vsc8584_macsec_add_rxsa(ctx, flow, true);
|
|
if (ret)
|
|
return ret;
|
|
|
|
vsc8584_macsec_flow_enable(ctx->phydev, flow);
|
|
return 0;
|
|
}
|
|
|
|
static int vsc8584_macsec_del_rxsa(struct macsec_context *ctx)
|
|
{
|
|
struct macsec_flow *flow;
|
|
|
|
flow = vsc8584_macsec_find_flow(ctx, MACSEC_INGR);
|
|
if (IS_ERR(flow))
|
|
return PTR_ERR(flow);
|
|
|
|
vsc8584_macsec_del_flow(ctx->phydev, flow);
|
|
return 0;
|
|
}
|
|
|
|
static int vsc8584_macsec_add_txsa(struct macsec_context *ctx)
|
|
{
|
|
struct phy_device *phydev = ctx->phydev;
|
|
struct vsc8531_private *priv = phydev->priv;
|
|
struct macsec_flow *flow;
|
|
int ret;
|
|
|
|
flow = vsc8584_macsec_alloc_flow(priv, MACSEC_EGR);
|
|
if (IS_ERR(flow))
|
|
return PTR_ERR(flow);
|
|
|
|
memcpy(flow->key, ctx->sa.key, priv->secy->key_len);
|
|
|
|
ret = __vsc8584_macsec_add_txsa(ctx, flow, false);
|
|
if (ret)
|
|
return ret;
|
|
|
|
vsc8584_macsec_flow_enable(phydev, flow);
|
|
return 0;
|
|
}
|
|
|
|
static int vsc8584_macsec_upd_txsa(struct macsec_context *ctx)
|
|
{
|
|
struct macsec_flow *flow;
|
|
int ret;
|
|
|
|
flow = vsc8584_macsec_find_flow(ctx, MACSEC_EGR);
|
|
if (IS_ERR(flow))
|
|
return PTR_ERR(flow);
|
|
|
|
/* Make sure the flow is disabled before updating it */
|
|
vsc8584_macsec_flow_disable(ctx->phydev, flow);
|
|
|
|
ret = __vsc8584_macsec_add_txsa(ctx, flow, true);
|
|
if (ret)
|
|
return ret;
|
|
|
|
vsc8584_macsec_flow_enable(ctx->phydev, flow);
|
|
return 0;
|
|
}
|
|
|
|
static int vsc8584_macsec_del_txsa(struct macsec_context *ctx)
|
|
{
|
|
struct macsec_flow *flow;
|
|
|
|
flow = vsc8584_macsec_find_flow(ctx, MACSEC_EGR);
|
|
if (IS_ERR(flow))
|
|
return PTR_ERR(flow);
|
|
|
|
vsc8584_macsec_del_flow(ctx->phydev, flow);
|
|
return 0;
|
|
}
|
|
|
|
static const struct macsec_ops vsc8584_macsec_ops = {
|
|
.mdo_dev_open = vsc8584_macsec_dev_open,
|
|
.mdo_dev_stop = vsc8584_macsec_dev_stop,
|
|
.mdo_add_secy = vsc8584_macsec_add_secy,
|
|
.mdo_upd_secy = vsc8584_macsec_upd_secy,
|
|
.mdo_del_secy = vsc8584_macsec_del_secy,
|
|
.mdo_add_rxsc = vsc8584_macsec_add_rxsc,
|
|
.mdo_upd_rxsc = vsc8584_macsec_upd_rxsc,
|
|
.mdo_del_rxsc = vsc8584_macsec_del_rxsc,
|
|
.mdo_add_rxsa = vsc8584_macsec_add_rxsa,
|
|
.mdo_upd_rxsa = vsc8584_macsec_upd_rxsa,
|
|
.mdo_del_rxsa = vsc8584_macsec_del_rxsa,
|
|
.mdo_add_txsa = vsc8584_macsec_add_txsa,
|
|
.mdo_upd_txsa = vsc8584_macsec_upd_txsa,
|
|
.mdo_del_txsa = vsc8584_macsec_del_txsa,
|
|
};
|
|
|
|
int vsc8584_macsec_init(struct phy_device *phydev)
|
|
{
|
|
struct vsc8531_private *vsc8531 = phydev->priv;
|
|
|
|
switch (phydev->phy_id & phydev->drv->phy_id_mask) {
|
|
case PHY_ID_VSC856X:
|
|
case PHY_ID_VSC8582:
|
|
case PHY_ID_VSC8584:
|
|
INIT_LIST_HEAD(&vsc8531->macsec_flows);
|
|
vsc8531->secy = NULL;
|
|
|
|
phydev->macsec_ops = &vsc8584_macsec_ops;
|
|
|
|
return __vsc8584_macsec_init(phydev);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
void vsc8584_handle_macsec_interrupt(struct phy_device *phydev)
|
|
{
|
|
struct vsc8531_private *priv = phydev->priv;
|
|
struct macsec_flow *flow, *tmp;
|
|
u32 cause, rec;
|
|
|
|
/* Check MACsec PN rollover */
|
|
cause = vsc8584_macsec_phy_read(phydev, MACSEC_EGR,
|
|
MSCC_MS_INTR_CTRL_STATUS);
|
|
cause &= MSCC_MS_INTR_CTRL_STATUS_INTR_CLR_STATUS_M;
|
|
if (!(cause & MACSEC_INTR_CTRL_STATUS_ROLLOVER))
|
|
return;
|
|
|
|
rec = 6 + priv->secy->key_len / sizeof(u32);
|
|
list_for_each_entry_safe(flow, tmp, &priv->macsec_flows, list) {
|
|
u32 val;
|
|
|
|
if (flow->bank != MACSEC_EGR || !flow->has_transformation)
|
|
continue;
|
|
|
|
val = vsc8584_macsec_phy_read(phydev, MACSEC_EGR,
|
|
MSCC_MS_XFORM_REC(flow->index, rec));
|
|
if (val == 0xffffffff) {
|
|
vsc8584_macsec_flow_disable(phydev, flow);
|
|
macsec_pn_wrapped(priv->secy, flow->tx_sa);
|
|
return;
|
|
}
|
|
}
|
|
}
|
|
|
|
void vsc8584_config_macsec_intr(struct phy_device *phydev)
|
|
{
|
|
phy_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED_2);
|
|
phy_write(phydev, MSCC_PHY_EXTENDED_INT, MSCC_PHY_EXTENDED_INT_MS_EGR);
|
|
phy_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
|
|
|
|
vsc8584_macsec_phy_write(phydev, MACSEC_EGR, MSCC_MS_AIC_CTRL, 0xf);
|
|
vsc8584_macsec_phy_write(phydev, MACSEC_EGR, MSCC_MS_INTR_CTRL_STATUS,
|
|
MSCC_MS_INTR_CTRL_STATUS_INTR_ENABLE(MACSEC_INTR_CTRL_STATUS_ROLLOVER));
|
|
}
|