392 lines
9.2 KiB
C
392 lines
9.2 KiB
C
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/*
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* Driver for the MDIO interface of Microsemi network switches.
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*
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* Author: Alexandre Belloni <alexandre.belloni@bootlin.com>
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* Copyright (c) 2017 Microsemi Corporation
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*/
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#include <linux/bitops.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <linux/iopoll.h>
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#include <linux/kernel.h>
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#include <linux/mdio/mdio-mscc-miim.h>
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#include <linux/mfd/ocelot.h>
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#include <linux/module.h>
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#include <linux/of_mdio.h>
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#include <linux/phy.h>
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#include <linux/platform_device.h>
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#include <linux/property.h>
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#include <linux/regmap.h>
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#define MSCC_MIIM_REG_STATUS 0x0
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#define MSCC_MIIM_STATUS_STAT_PENDING BIT(2)
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#define MSCC_MIIM_STATUS_STAT_BUSY BIT(3)
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#define MSCC_MIIM_REG_CMD 0x8
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#define MSCC_MIIM_CMD_OPR_WRITE BIT(1)
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#define MSCC_MIIM_CMD_OPR_READ BIT(2)
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#define MSCC_MIIM_CMD_WRDATA_SHIFT 4
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#define MSCC_MIIM_CMD_REGAD_SHIFT 20
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#define MSCC_MIIM_CMD_PHYAD_SHIFT 25
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#define MSCC_MIIM_CMD_VLD BIT(31)
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#define MSCC_MIIM_REG_DATA 0xC
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#define MSCC_MIIM_DATA_ERROR (BIT(16) | BIT(17))
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#define MSCC_MIIM_REG_CFG 0x10
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#define MSCC_MIIM_CFG_PRESCALE_MASK GENMASK(7, 0)
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#define MSCC_PHY_REG_PHY_CFG 0x0
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#define PHY_CFG_PHY_ENA (BIT(0) | BIT(1) | BIT(2) | BIT(3))
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#define PHY_CFG_PHY_COMMON_RESET BIT(4)
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#define PHY_CFG_PHY_RESET (BIT(5) | BIT(6) | BIT(7) | BIT(8))
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#define MSCC_PHY_REG_PHY_STATUS 0x4
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#define LAN966X_CUPHY_COMMON_CFG 0x0
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#define CUPHY_COMMON_CFG_RESET_N BIT(0)
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struct mscc_miim_info {
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unsigned int phy_reset_offset;
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unsigned int phy_reset_bits;
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};
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struct mscc_miim_dev {
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struct regmap *regs;
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int mii_status_offset;
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bool ignore_read_errors;
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struct regmap *phy_regs;
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const struct mscc_miim_info *info;
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struct clk *clk;
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u32 bus_freq;
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};
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/* When high resolution timers aren't built-in: we can't use usleep_range() as
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* we would sleep way too long. Use udelay() instead.
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*/
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#define mscc_readx_poll_timeout(op, addr, val, cond, delay_us, timeout_us)\
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({ \
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if (!IS_ENABLED(CONFIG_HIGH_RES_TIMERS)) \
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readx_poll_timeout_atomic(op, addr, val, cond, delay_us, \
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timeout_us); \
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readx_poll_timeout(op, addr, val, cond, delay_us, timeout_us); \
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})
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static int mscc_miim_status(struct mii_bus *bus)
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{
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struct mscc_miim_dev *miim = bus->priv;
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int val, ret;
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ret = regmap_read(miim->regs,
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MSCC_MIIM_REG_STATUS + miim->mii_status_offset, &val);
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if (ret < 0) {
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WARN_ONCE(1, "mscc miim status read error %d\n", ret);
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return ret;
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}
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return val;
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}
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static int mscc_miim_wait_ready(struct mii_bus *bus)
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{
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u32 val;
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return mscc_readx_poll_timeout(mscc_miim_status, bus, val,
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!(val & MSCC_MIIM_STATUS_STAT_BUSY), 50,
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10000);
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}
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static int mscc_miim_wait_pending(struct mii_bus *bus)
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{
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u32 val;
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return mscc_readx_poll_timeout(mscc_miim_status, bus, val,
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!(val & MSCC_MIIM_STATUS_STAT_PENDING),
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50, 10000);
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}
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static int mscc_miim_read(struct mii_bus *bus, int mii_id, int regnum)
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{
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struct mscc_miim_dev *miim = bus->priv;
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u32 val;
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int ret;
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if (regnum & MII_ADDR_C45)
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return -EOPNOTSUPP;
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ret = mscc_miim_wait_pending(bus);
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if (ret)
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goto out;
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ret = regmap_write(miim->regs,
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MSCC_MIIM_REG_CMD + miim->mii_status_offset,
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MSCC_MIIM_CMD_VLD |
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(mii_id << MSCC_MIIM_CMD_PHYAD_SHIFT) |
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(regnum << MSCC_MIIM_CMD_REGAD_SHIFT) |
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MSCC_MIIM_CMD_OPR_READ);
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if (ret < 0) {
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WARN_ONCE(1, "mscc miim write cmd reg error %d\n", ret);
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goto out;
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}
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ret = mscc_miim_wait_ready(bus);
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if (ret)
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goto out;
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ret = regmap_read(miim->regs,
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MSCC_MIIM_REG_DATA + miim->mii_status_offset, &val);
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if (ret < 0) {
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WARN_ONCE(1, "mscc miim read data reg error %d\n", ret);
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goto out;
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}
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if (!miim->ignore_read_errors && !!(val & MSCC_MIIM_DATA_ERROR)) {
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ret = -EIO;
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goto out;
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}
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ret = val & 0xFFFF;
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out:
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return ret;
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}
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static int mscc_miim_write(struct mii_bus *bus, int mii_id,
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int regnum, u16 value)
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{
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struct mscc_miim_dev *miim = bus->priv;
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int ret;
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if (regnum & MII_ADDR_C45)
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return -EOPNOTSUPP;
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ret = mscc_miim_wait_pending(bus);
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if (ret < 0)
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goto out;
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ret = regmap_write(miim->regs,
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MSCC_MIIM_REG_CMD + miim->mii_status_offset,
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MSCC_MIIM_CMD_VLD |
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(mii_id << MSCC_MIIM_CMD_PHYAD_SHIFT) |
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(regnum << MSCC_MIIM_CMD_REGAD_SHIFT) |
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(value << MSCC_MIIM_CMD_WRDATA_SHIFT) |
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MSCC_MIIM_CMD_OPR_WRITE);
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if (ret < 0)
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WARN_ONCE(1, "mscc miim write error %d\n", ret);
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out:
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return ret;
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}
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static int mscc_miim_reset(struct mii_bus *bus)
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{
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struct mscc_miim_dev *miim = bus->priv;
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unsigned int offset, bits;
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int ret;
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if (!miim->phy_regs)
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return 0;
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offset = miim->info->phy_reset_offset;
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bits = miim->info->phy_reset_bits;
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ret = regmap_update_bits(miim->phy_regs, offset, bits, 0);
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if (ret < 0) {
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WARN_ONCE(1, "mscc reset set error %d\n", ret);
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return ret;
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}
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ret = regmap_update_bits(miim->phy_regs, offset, bits, bits);
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if (ret < 0) {
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WARN_ONCE(1, "mscc reset clear error %d\n", ret);
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return ret;
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}
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mdelay(500);
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return 0;
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}
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static const struct regmap_config mscc_miim_regmap_config = {
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.reg_bits = 32,
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.val_bits = 32,
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.reg_stride = 4,
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};
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static const struct regmap_config mscc_miim_phy_regmap_config = {
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.reg_bits = 32,
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.val_bits = 32,
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.reg_stride = 4,
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.name = "phy",
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};
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int mscc_miim_setup(struct device *dev, struct mii_bus **pbus, const char *name,
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struct regmap *mii_regmap, int status_offset,
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bool ignore_read_errors)
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{
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struct mscc_miim_dev *miim;
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struct mii_bus *bus;
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bus = devm_mdiobus_alloc_size(dev, sizeof(*miim));
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if (!bus)
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return -ENOMEM;
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bus->name = name;
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bus->read = mscc_miim_read;
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bus->write = mscc_miim_write;
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bus->reset = mscc_miim_reset;
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snprintf(bus->id, MII_BUS_ID_SIZE, "%s-mii", dev_name(dev));
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bus->parent = dev;
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miim = bus->priv;
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*pbus = bus;
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miim->regs = mii_regmap;
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miim->mii_status_offset = status_offset;
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miim->ignore_read_errors = ignore_read_errors;
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*pbus = bus;
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return 0;
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}
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EXPORT_SYMBOL(mscc_miim_setup);
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static int mscc_miim_clk_set(struct mii_bus *bus)
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{
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struct mscc_miim_dev *miim = bus->priv;
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unsigned long rate;
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u32 div;
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/* Keep the current settings */
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if (!miim->bus_freq)
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return 0;
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rate = clk_get_rate(miim->clk);
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div = DIV_ROUND_UP(rate, 2 * miim->bus_freq) - 1;
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if (div == 0 || div & ~MSCC_MIIM_CFG_PRESCALE_MASK) {
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dev_err(&bus->dev, "Incorrect MDIO clock frequency\n");
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return -EINVAL;
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}
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return regmap_update_bits(miim->regs, MSCC_MIIM_REG_CFG,
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MSCC_MIIM_CFG_PRESCALE_MASK, div);
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}
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static int mscc_miim_probe(struct platform_device *pdev)
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{
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struct device_node *np = pdev->dev.of_node;
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struct regmap *mii_regmap, *phy_regmap;
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struct device *dev = &pdev->dev;
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struct mscc_miim_dev *miim;
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struct mii_bus *bus;
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int ret;
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mii_regmap = ocelot_regmap_from_resource(pdev, 0,
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&mscc_miim_regmap_config);
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if (IS_ERR(mii_regmap))
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return dev_err_probe(dev, PTR_ERR(mii_regmap),
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"Unable to create MIIM regmap\n");
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/* This resource is optional */
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phy_regmap = ocelot_regmap_from_resource_optional(pdev, 1,
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&mscc_miim_phy_regmap_config);
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if (IS_ERR(phy_regmap))
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return dev_err_probe(dev, PTR_ERR(phy_regmap),
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"Unable to create phy register regmap\n");
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ret = mscc_miim_setup(dev, &bus, "mscc_miim", mii_regmap, 0, false);
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if (ret < 0) {
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dev_err(dev, "Unable to setup the MDIO bus\n");
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return ret;
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}
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miim = bus->priv;
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miim->phy_regs = phy_regmap;
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miim->info = device_get_match_data(dev);
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if (!miim->info)
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return -EINVAL;
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miim->clk = devm_clk_get_optional(dev, NULL);
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if (IS_ERR(miim->clk))
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return PTR_ERR(miim->clk);
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of_property_read_u32(np, "clock-frequency", &miim->bus_freq);
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if (miim->bus_freq && !miim->clk) {
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dev_err(dev, "cannot use clock-frequency without a clock\n");
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return -EINVAL;
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}
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ret = clk_prepare_enable(miim->clk);
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if (ret)
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return ret;
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ret = mscc_miim_clk_set(bus);
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if (ret)
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goto out_disable_clk;
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ret = of_mdiobus_register(bus, np);
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if (ret < 0) {
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dev_err(dev, "Cannot register MDIO bus (%d)\n", ret);
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goto out_disable_clk;
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}
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platform_set_drvdata(pdev, bus);
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return 0;
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out_disable_clk:
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clk_disable_unprepare(miim->clk);
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return ret;
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}
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static int mscc_miim_remove(struct platform_device *pdev)
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{
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struct mii_bus *bus = platform_get_drvdata(pdev);
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struct mscc_miim_dev *miim = bus->priv;
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clk_disable_unprepare(miim->clk);
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mdiobus_unregister(bus);
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return 0;
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}
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static const struct mscc_miim_info mscc_ocelot_miim_info = {
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.phy_reset_offset = MSCC_PHY_REG_PHY_CFG,
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.phy_reset_bits = PHY_CFG_PHY_ENA | PHY_CFG_PHY_COMMON_RESET |
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PHY_CFG_PHY_RESET,
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};
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static const struct mscc_miim_info microchip_lan966x_miim_info = {
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.phy_reset_offset = LAN966X_CUPHY_COMMON_CFG,
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.phy_reset_bits = CUPHY_COMMON_CFG_RESET_N,
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};
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static const struct of_device_id mscc_miim_match[] = {
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{
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.compatible = "mscc,ocelot-miim",
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.data = &mscc_ocelot_miim_info
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}, {
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.compatible = "microchip,lan966x-miim",
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.data = µchip_lan966x_miim_info
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},
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{ }
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};
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MODULE_DEVICE_TABLE(of, mscc_miim_match);
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static struct platform_driver mscc_miim_driver = {
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.probe = mscc_miim_probe,
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.remove = mscc_miim_remove,
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.driver = {
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.name = "mscc-miim",
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.of_match_table = mscc_miim_match,
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},
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};
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module_platform_driver(mscc_miim_driver);
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MODULE_DESCRIPTION("Microsemi MIIM driver");
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MODULE_AUTHOR("Alexandre Belloni <alexandre.belloni@bootlin.com>");
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MODULE_LICENSE("Dual MIT/GPL");
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