889 lines
23 KiB
C
889 lines
23 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* sdhci_am654.c - SDHCI driver for TI's AM654 SOCs
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*
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* Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com
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*
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*/
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#include <linux/clk.h>
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#include <linux/iopoll.h>
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#include <linux/of.h>
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#include <linux/module.h>
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#include <linux/pm_runtime.h>
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#include <linux/property.h>
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#include <linux/regmap.h>
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#include <linux/sys_soc.h>
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#include "cqhci.h"
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#include "sdhci-cqhci.h"
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#include "sdhci-pltfm.h"
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/* CTL_CFG Registers */
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#define CTL_CFG_2 0x14
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#define CTL_CFG_3 0x18
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#define SLOTTYPE_MASK GENMASK(31, 30)
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#define SLOTTYPE_EMBEDDED BIT(30)
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#define TUNINGFORSDR50_MASK BIT(13)
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/* PHY Registers */
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#define PHY_CTRL1 0x100
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#define PHY_CTRL2 0x104
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#define PHY_CTRL3 0x108
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#define PHY_CTRL4 0x10C
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#define PHY_CTRL5 0x110
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#define PHY_CTRL6 0x114
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#define PHY_STAT1 0x130
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#define PHY_STAT2 0x134
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#define IOMUX_ENABLE_SHIFT 31
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#define IOMUX_ENABLE_MASK BIT(IOMUX_ENABLE_SHIFT)
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#define OTAPDLYENA_SHIFT 20
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#define OTAPDLYENA_MASK BIT(OTAPDLYENA_SHIFT)
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#define OTAPDLYSEL_SHIFT 12
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#define OTAPDLYSEL_MASK GENMASK(15, 12)
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#define STRBSEL_SHIFT 24
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#define STRBSEL_4BIT_MASK GENMASK(27, 24)
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#define STRBSEL_8BIT_MASK GENMASK(31, 24)
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#define SEL50_SHIFT 8
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#define SEL50_MASK BIT(SEL50_SHIFT)
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#define SEL100_SHIFT 9
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#define SEL100_MASK BIT(SEL100_SHIFT)
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#define FREQSEL_SHIFT 8
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#define FREQSEL_MASK GENMASK(10, 8)
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#define CLKBUFSEL_SHIFT 0
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#define CLKBUFSEL_MASK GENMASK(2, 0)
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#define DLL_TRIM_ICP_SHIFT 4
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#define DLL_TRIM_ICP_MASK GENMASK(7, 4)
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#define DR_TY_SHIFT 20
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#define DR_TY_MASK GENMASK(22, 20)
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#define ENDLL_SHIFT 1
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#define ENDLL_MASK BIT(ENDLL_SHIFT)
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#define DLLRDY_SHIFT 0
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#define DLLRDY_MASK BIT(DLLRDY_SHIFT)
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#define PDB_SHIFT 0
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#define PDB_MASK BIT(PDB_SHIFT)
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#define CALDONE_SHIFT 1
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#define CALDONE_MASK BIT(CALDONE_SHIFT)
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#define RETRIM_SHIFT 17
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#define RETRIM_MASK BIT(RETRIM_SHIFT)
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#define SELDLYTXCLK_SHIFT 17
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#define SELDLYTXCLK_MASK BIT(SELDLYTXCLK_SHIFT)
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#define SELDLYRXCLK_SHIFT 16
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#define SELDLYRXCLK_MASK BIT(SELDLYRXCLK_SHIFT)
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#define ITAPDLYSEL_SHIFT 0
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#define ITAPDLYSEL_MASK GENMASK(4, 0)
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#define ITAPDLYENA_SHIFT 8
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#define ITAPDLYENA_MASK BIT(ITAPDLYENA_SHIFT)
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#define ITAPCHGWIN_SHIFT 9
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#define ITAPCHGWIN_MASK BIT(ITAPCHGWIN_SHIFT)
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#define DRIVER_STRENGTH_50_OHM 0x0
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#define DRIVER_STRENGTH_33_OHM 0x1
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#define DRIVER_STRENGTH_66_OHM 0x2
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#define DRIVER_STRENGTH_100_OHM 0x3
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#define DRIVER_STRENGTH_40_OHM 0x4
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#define CLOCK_TOO_SLOW_HZ 50000000
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/* Command Queue Host Controller Interface Base address */
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#define SDHCI_AM654_CQE_BASE_ADDR 0x200
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static struct regmap_config sdhci_am654_regmap_config = {
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.reg_bits = 32,
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.val_bits = 32,
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.reg_stride = 4,
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.fast_io = true,
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};
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struct timing_data {
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const char *otap_binding;
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const char *itap_binding;
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u32 capability;
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};
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static const struct timing_data td[] = {
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[MMC_TIMING_LEGACY] = {"ti,otap-del-sel-legacy",
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"ti,itap-del-sel-legacy",
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0},
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[MMC_TIMING_MMC_HS] = {"ti,otap-del-sel-mmc-hs",
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"ti,itap-del-sel-mmc-hs",
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MMC_CAP_MMC_HIGHSPEED},
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[MMC_TIMING_SD_HS] = {"ti,otap-del-sel-sd-hs",
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"ti,itap-del-sel-sd-hs",
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MMC_CAP_SD_HIGHSPEED},
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[MMC_TIMING_UHS_SDR12] = {"ti,otap-del-sel-sdr12",
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"ti,itap-del-sel-sdr12",
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MMC_CAP_UHS_SDR12},
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[MMC_TIMING_UHS_SDR25] = {"ti,otap-del-sel-sdr25",
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"ti,itap-del-sel-sdr25",
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MMC_CAP_UHS_SDR25},
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[MMC_TIMING_UHS_SDR50] = {"ti,otap-del-sel-sdr50",
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NULL,
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MMC_CAP_UHS_SDR50},
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[MMC_TIMING_UHS_SDR104] = {"ti,otap-del-sel-sdr104",
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NULL,
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MMC_CAP_UHS_SDR104},
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[MMC_TIMING_UHS_DDR50] = {"ti,otap-del-sel-ddr50",
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NULL,
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MMC_CAP_UHS_DDR50},
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[MMC_TIMING_MMC_DDR52] = {"ti,otap-del-sel-ddr52",
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"ti,itap-del-sel-ddr52",
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MMC_CAP_DDR},
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[MMC_TIMING_MMC_HS200] = {"ti,otap-del-sel-hs200",
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NULL,
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MMC_CAP2_HS200},
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[MMC_TIMING_MMC_HS400] = {"ti,otap-del-sel-hs400",
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NULL,
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MMC_CAP2_HS400},
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};
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struct sdhci_am654_data {
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struct regmap *base;
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bool legacy_otapdly;
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int otap_del_sel[ARRAY_SIZE(td)];
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int itap_del_sel[ARRAY_SIZE(td)];
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int clkbuf_sel;
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int trm_icp;
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int drv_strength;
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int strb_sel;
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u32 flags;
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u32 quirks;
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#define SDHCI_AM654_QUIRK_FORCE_CDTEST BIT(0)
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};
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struct sdhci_am654_driver_data {
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const struct sdhci_pltfm_data *pdata;
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u32 flags;
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#define IOMUX_PRESENT (1 << 0)
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#define FREQSEL_2_BIT (1 << 1)
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#define STRBSEL_4_BIT (1 << 2)
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#define DLL_PRESENT (1 << 3)
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#define DLL_CALIB (1 << 4)
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};
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static void sdhci_am654_setup_dll(struct sdhci_host *host, unsigned int clock)
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{
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struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
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struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host);
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int sel50, sel100, freqsel;
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u32 mask, val;
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int ret;
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/* Disable delay chain mode */
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regmap_update_bits(sdhci_am654->base, PHY_CTRL5,
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SELDLYTXCLK_MASK | SELDLYRXCLK_MASK, 0);
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if (sdhci_am654->flags & FREQSEL_2_BIT) {
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switch (clock) {
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case 200000000:
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sel50 = 0;
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sel100 = 0;
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break;
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case 100000000:
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sel50 = 0;
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sel100 = 1;
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break;
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default:
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sel50 = 1;
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sel100 = 0;
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}
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/* Configure PHY DLL frequency */
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mask = SEL50_MASK | SEL100_MASK;
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val = (sel50 << SEL50_SHIFT) | (sel100 << SEL100_SHIFT);
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regmap_update_bits(sdhci_am654->base, PHY_CTRL5, mask, val);
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} else {
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switch (clock) {
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case 200000000:
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freqsel = 0x0;
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break;
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default:
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freqsel = 0x4;
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}
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regmap_update_bits(sdhci_am654->base, PHY_CTRL5, FREQSEL_MASK,
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freqsel << FREQSEL_SHIFT);
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}
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/* Configure DLL TRIM */
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mask = DLL_TRIM_ICP_MASK;
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val = sdhci_am654->trm_icp << DLL_TRIM_ICP_SHIFT;
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/* Configure DLL driver strength */
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mask |= DR_TY_MASK;
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val |= sdhci_am654->drv_strength << DR_TY_SHIFT;
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regmap_update_bits(sdhci_am654->base, PHY_CTRL1, mask, val);
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/* Enable DLL */
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regmap_update_bits(sdhci_am654->base, PHY_CTRL1, ENDLL_MASK,
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0x1 << ENDLL_SHIFT);
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/*
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* Poll for DLL ready. Use a one second timeout.
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* Works in all experiments done so far
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*/
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ret = regmap_read_poll_timeout(sdhci_am654->base, PHY_STAT1, val,
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val & DLLRDY_MASK, 1000, 1000000);
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if (ret) {
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dev_err(mmc_dev(host->mmc), "DLL failed to relock\n");
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return;
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}
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}
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static void sdhci_am654_write_itapdly(struct sdhci_am654_data *sdhci_am654,
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u32 itapdly)
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{
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/* Set ITAPCHGWIN before writing to ITAPDLY */
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regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPCHGWIN_MASK,
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1 << ITAPCHGWIN_SHIFT);
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regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPDLYSEL_MASK,
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itapdly << ITAPDLYSEL_SHIFT);
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regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPCHGWIN_MASK, 0);
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}
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static void sdhci_am654_setup_delay_chain(struct sdhci_am654_data *sdhci_am654,
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unsigned char timing)
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{
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u32 mask, val;
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regmap_update_bits(sdhci_am654->base, PHY_CTRL1, ENDLL_MASK, 0);
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val = 1 << SELDLYTXCLK_SHIFT | 1 << SELDLYRXCLK_SHIFT;
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mask = SELDLYTXCLK_MASK | SELDLYRXCLK_MASK;
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regmap_update_bits(sdhci_am654->base, PHY_CTRL5, mask, val);
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sdhci_am654_write_itapdly(sdhci_am654,
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sdhci_am654->itap_del_sel[timing]);
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}
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static void sdhci_am654_set_clock(struct sdhci_host *host, unsigned int clock)
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{
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struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
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struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host);
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unsigned char timing = host->mmc->ios.timing;
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u32 otap_del_sel;
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u32 otap_del_ena;
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u32 mask, val;
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regmap_update_bits(sdhci_am654->base, PHY_CTRL1, ENDLL_MASK, 0);
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sdhci_set_clock(host, clock);
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/* Setup DLL Output TAP delay */
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if (sdhci_am654->legacy_otapdly)
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otap_del_sel = sdhci_am654->otap_del_sel[0];
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else
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otap_del_sel = sdhci_am654->otap_del_sel[timing];
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otap_del_ena = (timing > MMC_TIMING_UHS_SDR25) ? 1 : 0;
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mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK;
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val = (otap_del_ena << OTAPDLYENA_SHIFT) |
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(otap_del_sel << OTAPDLYSEL_SHIFT);
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/* Write to STRBSEL for HS400 speed mode */
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if (timing == MMC_TIMING_MMC_HS400) {
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if (sdhci_am654->flags & STRBSEL_4_BIT)
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mask |= STRBSEL_4BIT_MASK;
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else
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mask |= STRBSEL_8BIT_MASK;
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val |= sdhci_am654->strb_sel << STRBSEL_SHIFT;
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}
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regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, val);
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if (timing > MMC_TIMING_UHS_SDR25 && clock >= CLOCK_TOO_SLOW_HZ)
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sdhci_am654_setup_dll(host, clock);
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else
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sdhci_am654_setup_delay_chain(sdhci_am654, timing);
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regmap_update_bits(sdhci_am654->base, PHY_CTRL5, CLKBUFSEL_MASK,
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sdhci_am654->clkbuf_sel);
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}
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static void sdhci_j721e_4bit_set_clock(struct sdhci_host *host,
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unsigned int clock)
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{
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struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
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struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host);
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unsigned char timing = host->mmc->ios.timing;
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u32 otap_del_sel;
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u32 mask, val;
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/* Setup DLL Output TAP delay */
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if (sdhci_am654->legacy_otapdly)
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otap_del_sel = sdhci_am654->otap_del_sel[0];
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else
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otap_del_sel = sdhci_am654->otap_del_sel[timing];
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mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK;
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val = (0x1 << OTAPDLYENA_SHIFT) |
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(otap_del_sel << OTAPDLYSEL_SHIFT);
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regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, val);
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regmap_update_bits(sdhci_am654->base, PHY_CTRL5, CLKBUFSEL_MASK,
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sdhci_am654->clkbuf_sel);
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sdhci_set_clock(host, clock);
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}
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static u8 sdhci_am654_write_power_on(struct sdhci_host *host, u8 val, int reg)
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{
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writeb(val, host->ioaddr + reg);
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usleep_range(1000, 10000);
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return readb(host->ioaddr + reg);
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}
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#define MAX_POWER_ON_TIMEOUT 1500000 /* us */
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static void sdhci_am654_write_b(struct sdhci_host *host, u8 val, int reg)
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{
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unsigned char timing = host->mmc->ios.timing;
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u8 pwr;
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int ret;
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if (reg == SDHCI_HOST_CONTROL) {
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switch (timing) {
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/*
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* According to the data manual, HISPD bit
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* should not be set in these speed modes.
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*/
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case MMC_TIMING_SD_HS:
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case MMC_TIMING_MMC_HS:
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val &= ~SDHCI_CTRL_HISPD;
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}
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}
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writeb(val, host->ioaddr + reg);
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if (reg == SDHCI_POWER_CONTROL && (val & SDHCI_POWER_ON)) {
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/*
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* Power on will not happen until the card detect debounce
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* timer expires. Wait at least 1.5 seconds for the power on
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* bit to be set
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*/
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ret = read_poll_timeout(sdhci_am654_write_power_on, pwr,
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pwr & SDHCI_POWER_ON, 0,
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MAX_POWER_ON_TIMEOUT, false, host, val,
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reg);
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if (ret)
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dev_info(mmc_dev(host->mmc), "Power on failed\n");
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}
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}
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static void sdhci_am654_reset(struct sdhci_host *host, u8 mask)
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{
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u8 ctrl;
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struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
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struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host);
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sdhci_and_cqhci_reset(host, mask);
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if (sdhci_am654->quirks & SDHCI_AM654_QUIRK_FORCE_CDTEST) {
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ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
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ctrl |= SDHCI_CTRL_CDTEST_INS | SDHCI_CTRL_CDTEST_EN;
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sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
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}
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}
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static int sdhci_am654_execute_tuning(struct mmc_host *mmc, u32 opcode)
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{
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struct sdhci_host *host = mmc_priv(mmc);
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int err = sdhci_execute_tuning(mmc, opcode);
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if (err)
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return err;
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/*
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* Tuning data remains in the buffer after tuning.
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* Do a command and data reset to get rid of it
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*/
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sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
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return 0;
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}
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static u32 sdhci_am654_cqhci_irq(struct sdhci_host *host, u32 intmask)
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{
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int cmd_error = 0;
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int data_error = 0;
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if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error))
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return intmask;
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cqhci_irq(host->mmc, intmask, cmd_error, data_error);
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return 0;
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}
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#define ITAP_MAX 32
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static int sdhci_am654_platform_execute_tuning(struct sdhci_host *host,
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u32 opcode)
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{
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struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
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struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host);
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int cur_val, prev_val = 1, fail_len = 0, pass_window = 0, pass_len;
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u32 itap;
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/* Enable ITAPDLY */
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regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPDLYENA_MASK,
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1 << ITAPDLYENA_SHIFT);
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for (itap = 0; itap < ITAP_MAX; itap++) {
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sdhci_am654_write_itapdly(sdhci_am654, itap);
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cur_val = !mmc_send_tuning(host->mmc, opcode, NULL);
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if (cur_val && !prev_val)
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pass_window = itap;
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if (!cur_val)
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fail_len++;
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prev_val = cur_val;
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}
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/*
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* Having determined the length of the failing window and start of
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* the passing window calculate the length of the passing window and
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* set the final value halfway through it considering the range as a
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* circular buffer
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*/
|
|
pass_len = ITAP_MAX - fail_len;
|
|
itap = (pass_window + (pass_len >> 1)) % ITAP_MAX;
|
|
sdhci_am654_write_itapdly(sdhci_am654, itap);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct sdhci_ops sdhci_am654_ops = {
|
|
.platform_execute_tuning = sdhci_am654_platform_execute_tuning,
|
|
.get_max_clock = sdhci_pltfm_clk_get_max_clock,
|
|
.get_timeout_clock = sdhci_pltfm_clk_get_max_clock,
|
|
.set_uhs_signaling = sdhci_set_uhs_signaling,
|
|
.set_bus_width = sdhci_set_bus_width,
|
|
.set_power = sdhci_set_power_and_bus_voltage,
|
|
.set_clock = sdhci_am654_set_clock,
|
|
.write_b = sdhci_am654_write_b,
|
|
.irq = sdhci_am654_cqhci_irq,
|
|
.reset = sdhci_and_cqhci_reset,
|
|
};
|
|
|
|
static const struct sdhci_pltfm_data sdhci_am654_pdata = {
|
|
.ops = &sdhci_am654_ops,
|
|
.quirks = SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12,
|
|
.quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
|
|
};
|
|
|
|
static const struct sdhci_am654_driver_data sdhci_am654_sr1_drvdata = {
|
|
.pdata = &sdhci_am654_pdata,
|
|
.flags = IOMUX_PRESENT | FREQSEL_2_BIT | STRBSEL_4_BIT | DLL_PRESENT |
|
|
DLL_CALIB,
|
|
};
|
|
|
|
static const struct sdhci_am654_driver_data sdhci_am654_drvdata = {
|
|
.pdata = &sdhci_am654_pdata,
|
|
.flags = IOMUX_PRESENT | FREQSEL_2_BIT | STRBSEL_4_BIT | DLL_PRESENT,
|
|
};
|
|
|
|
static struct sdhci_ops sdhci_j721e_8bit_ops = {
|
|
.platform_execute_tuning = sdhci_am654_platform_execute_tuning,
|
|
.get_max_clock = sdhci_pltfm_clk_get_max_clock,
|
|
.get_timeout_clock = sdhci_pltfm_clk_get_max_clock,
|
|
.set_uhs_signaling = sdhci_set_uhs_signaling,
|
|
.set_bus_width = sdhci_set_bus_width,
|
|
.set_power = sdhci_set_power_and_bus_voltage,
|
|
.set_clock = sdhci_am654_set_clock,
|
|
.write_b = sdhci_am654_write_b,
|
|
.irq = sdhci_am654_cqhci_irq,
|
|
.reset = sdhci_and_cqhci_reset,
|
|
};
|
|
|
|
static const struct sdhci_pltfm_data sdhci_j721e_8bit_pdata = {
|
|
.ops = &sdhci_j721e_8bit_ops,
|
|
.quirks = SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12,
|
|
.quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
|
|
};
|
|
|
|
static const struct sdhci_am654_driver_data sdhci_j721e_8bit_drvdata = {
|
|
.pdata = &sdhci_j721e_8bit_pdata,
|
|
.flags = DLL_PRESENT | DLL_CALIB,
|
|
};
|
|
|
|
static struct sdhci_ops sdhci_j721e_4bit_ops = {
|
|
.platform_execute_tuning = sdhci_am654_platform_execute_tuning,
|
|
.get_max_clock = sdhci_pltfm_clk_get_max_clock,
|
|
.get_timeout_clock = sdhci_pltfm_clk_get_max_clock,
|
|
.set_uhs_signaling = sdhci_set_uhs_signaling,
|
|
.set_bus_width = sdhci_set_bus_width,
|
|
.set_power = sdhci_set_power_and_bus_voltage,
|
|
.set_clock = sdhci_j721e_4bit_set_clock,
|
|
.write_b = sdhci_am654_write_b,
|
|
.irq = sdhci_am654_cqhci_irq,
|
|
.reset = sdhci_am654_reset,
|
|
};
|
|
|
|
static const struct sdhci_pltfm_data sdhci_j721e_4bit_pdata = {
|
|
.ops = &sdhci_j721e_4bit_ops,
|
|
.quirks = SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12,
|
|
.quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
|
|
};
|
|
|
|
static const struct sdhci_am654_driver_data sdhci_j721e_4bit_drvdata = {
|
|
.pdata = &sdhci_j721e_4bit_pdata,
|
|
.flags = IOMUX_PRESENT,
|
|
};
|
|
|
|
static const struct soc_device_attribute sdhci_am654_devices[] = {
|
|
{ .family = "AM65X",
|
|
.revision = "SR1.0",
|
|
.data = &sdhci_am654_sr1_drvdata
|
|
},
|
|
{/* sentinel */}
|
|
};
|
|
|
|
static void sdhci_am654_dumpregs(struct mmc_host *mmc)
|
|
{
|
|
sdhci_dumpregs(mmc_priv(mmc));
|
|
}
|
|
|
|
static const struct cqhci_host_ops sdhci_am654_cqhci_ops = {
|
|
.enable = sdhci_cqe_enable,
|
|
.disable = sdhci_cqe_disable,
|
|
.dumpregs = sdhci_am654_dumpregs,
|
|
};
|
|
|
|
static int sdhci_am654_cqe_add_host(struct sdhci_host *host)
|
|
{
|
|
struct cqhci_host *cq_host;
|
|
|
|
cq_host = devm_kzalloc(mmc_dev(host->mmc), sizeof(struct cqhci_host),
|
|
GFP_KERNEL);
|
|
if (!cq_host)
|
|
return -ENOMEM;
|
|
|
|
cq_host->mmio = host->ioaddr + SDHCI_AM654_CQE_BASE_ADDR;
|
|
cq_host->quirks |= CQHCI_QUIRK_SHORT_TXFR_DESC_SZ;
|
|
cq_host->caps |= CQHCI_TASK_DESC_SZ_128;
|
|
cq_host->ops = &sdhci_am654_cqhci_ops;
|
|
|
|
host->mmc->caps2 |= MMC_CAP2_CQE;
|
|
|
|
return cqhci_init(cq_host, host->mmc, 1);
|
|
}
|
|
|
|
static int sdhci_am654_get_otap_delay(struct sdhci_host *host,
|
|
struct sdhci_am654_data *sdhci_am654)
|
|
{
|
|
struct device *dev = mmc_dev(host->mmc);
|
|
int i;
|
|
int ret;
|
|
|
|
ret = device_property_read_u32(dev, td[MMC_TIMING_LEGACY].otap_binding,
|
|
&sdhci_am654->otap_del_sel[MMC_TIMING_LEGACY]);
|
|
if (ret) {
|
|
/*
|
|
* ti,otap-del-sel-legacy is mandatory, look for old binding
|
|
* if not found.
|
|
*/
|
|
ret = device_property_read_u32(dev, "ti,otap-del-sel",
|
|
&sdhci_am654->otap_del_sel[0]);
|
|
if (ret) {
|
|
dev_err(dev, "Couldn't find otap-del-sel\n");
|
|
|
|
return ret;
|
|
}
|
|
|
|
dev_info(dev, "Using legacy binding ti,otap-del-sel\n");
|
|
sdhci_am654->legacy_otapdly = true;
|
|
|
|
return 0;
|
|
}
|
|
|
|
for (i = MMC_TIMING_MMC_HS; i <= MMC_TIMING_MMC_HS400; i++) {
|
|
|
|
ret = device_property_read_u32(dev, td[i].otap_binding,
|
|
&sdhci_am654->otap_del_sel[i]);
|
|
if (ret) {
|
|
dev_dbg(dev, "Couldn't find %s\n",
|
|
td[i].otap_binding);
|
|
/*
|
|
* Remove the corresponding capability
|
|
* if an otap-del-sel value is not found
|
|
*/
|
|
if (i <= MMC_TIMING_MMC_DDR52)
|
|
host->mmc->caps &= ~td[i].capability;
|
|
else
|
|
host->mmc->caps2 &= ~td[i].capability;
|
|
}
|
|
|
|
if (td[i].itap_binding)
|
|
device_property_read_u32(dev, td[i].itap_binding,
|
|
&sdhci_am654->itap_del_sel[i]);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int sdhci_am654_init(struct sdhci_host *host)
|
|
{
|
|
struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
|
|
struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host);
|
|
u32 ctl_cfg_2 = 0;
|
|
u32 mask;
|
|
u32 val;
|
|
int ret;
|
|
|
|
/* Reset OTAP to default value */
|
|
mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK;
|
|
regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, 0x0);
|
|
|
|
if (sdhci_am654->flags & DLL_CALIB) {
|
|
regmap_read(sdhci_am654->base, PHY_STAT1, &val);
|
|
if (~val & CALDONE_MASK) {
|
|
/* Calibrate IO lines */
|
|
regmap_update_bits(sdhci_am654->base, PHY_CTRL1,
|
|
PDB_MASK, PDB_MASK);
|
|
ret = regmap_read_poll_timeout(sdhci_am654->base,
|
|
PHY_STAT1, val,
|
|
val & CALDONE_MASK,
|
|
1, 20);
|
|
if (ret)
|
|
return ret;
|
|
}
|
|
}
|
|
|
|
/* Enable pins by setting IO mux to 0 */
|
|
if (sdhci_am654->flags & IOMUX_PRESENT)
|
|
regmap_update_bits(sdhci_am654->base, PHY_CTRL1,
|
|
IOMUX_ENABLE_MASK, 0);
|
|
|
|
/* Set slot type based on SD or eMMC */
|
|
if (host->mmc->caps & MMC_CAP_NONREMOVABLE)
|
|
ctl_cfg_2 = SLOTTYPE_EMBEDDED;
|
|
|
|
regmap_update_bits(sdhci_am654->base, CTL_CFG_2, SLOTTYPE_MASK,
|
|
ctl_cfg_2);
|
|
|
|
/* Enable tuning for SDR50 */
|
|
regmap_update_bits(sdhci_am654->base, CTL_CFG_3, TUNINGFORSDR50_MASK,
|
|
TUNINGFORSDR50_MASK);
|
|
|
|
ret = sdhci_setup_host(host);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = sdhci_am654_cqe_add_host(host);
|
|
if (ret)
|
|
goto err_cleanup_host;
|
|
|
|
ret = sdhci_am654_get_otap_delay(host, sdhci_am654);
|
|
if (ret)
|
|
goto err_cleanup_host;
|
|
|
|
ret = __sdhci_add_host(host);
|
|
if (ret)
|
|
goto err_cleanup_host;
|
|
|
|
return 0;
|
|
|
|
err_cleanup_host:
|
|
sdhci_cleanup_host(host);
|
|
return ret;
|
|
}
|
|
|
|
static int sdhci_am654_get_of_property(struct platform_device *pdev,
|
|
struct sdhci_am654_data *sdhci_am654)
|
|
{
|
|
struct device *dev = &pdev->dev;
|
|
int drv_strength;
|
|
int ret;
|
|
|
|
if (sdhci_am654->flags & DLL_PRESENT) {
|
|
ret = device_property_read_u32(dev, "ti,trm-icp",
|
|
&sdhci_am654->trm_icp);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = device_property_read_u32(dev, "ti,driver-strength-ohm",
|
|
&drv_strength);
|
|
if (ret)
|
|
return ret;
|
|
|
|
switch (drv_strength) {
|
|
case 50:
|
|
sdhci_am654->drv_strength = DRIVER_STRENGTH_50_OHM;
|
|
break;
|
|
case 33:
|
|
sdhci_am654->drv_strength = DRIVER_STRENGTH_33_OHM;
|
|
break;
|
|
case 66:
|
|
sdhci_am654->drv_strength = DRIVER_STRENGTH_66_OHM;
|
|
break;
|
|
case 100:
|
|
sdhci_am654->drv_strength = DRIVER_STRENGTH_100_OHM;
|
|
break;
|
|
case 40:
|
|
sdhci_am654->drv_strength = DRIVER_STRENGTH_40_OHM;
|
|
break;
|
|
default:
|
|
dev_err(dev, "Invalid driver strength\n");
|
|
return -EINVAL;
|
|
}
|
|
}
|
|
|
|
device_property_read_u32(dev, "ti,strobe-sel", &sdhci_am654->strb_sel);
|
|
device_property_read_u32(dev, "ti,clkbuf-sel",
|
|
&sdhci_am654->clkbuf_sel);
|
|
|
|
if (device_property_read_bool(dev, "ti,fails-without-test-cd"))
|
|
sdhci_am654->quirks |= SDHCI_AM654_QUIRK_FORCE_CDTEST;
|
|
|
|
sdhci_get_of_property(pdev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct of_device_id sdhci_am654_of_match[] = {
|
|
{
|
|
.compatible = "ti,am654-sdhci-5.1",
|
|
.data = &sdhci_am654_drvdata,
|
|
},
|
|
{
|
|
.compatible = "ti,j721e-sdhci-8bit",
|
|
.data = &sdhci_j721e_8bit_drvdata,
|
|
},
|
|
{
|
|
.compatible = "ti,j721e-sdhci-4bit",
|
|
.data = &sdhci_j721e_4bit_drvdata,
|
|
},
|
|
{
|
|
.compatible = "ti,am64-sdhci-8bit",
|
|
.data = &sdhci_j721e_8bit_drvdata,
|
|
},
|
|
{
|
|
.compatible = "ti,am64-sdhci-4bit",
|
|
.data = &sdhci_j721e_4bit_drvdata,
|
|
},
|
|
{
|
|
.compatible = "ti,am62-sdhci",
|
|
.data = &sdhci_j721e_4bit_drvdata,
|
|
},
|
|
{ /* sentinel */ }
|
|
};
|
|
MODULE_DEVICE_TABLE(of, sdhci_am654_of_match);
|
|
|
|
static int sdhci_am654_probe(struct platform_device *pdev)
|
|
{
|
|
const struct sdhci_am654_driver_data *drvdata;
|
|
const struct soc_device_attribute *soc;
|
|
struct sdhci_pltfm_host *pltfm_host;
|
|
struct sdhci_am654_data *sdhci_am654;
|
|
const struct of_device_id *match;
|
|
struct sdhci_host *host;
|
|
struct clk *clk_xin;
|
|
struct device *dev = &pdev->dev;
|
|
void __iomem *base;
|
|
int ret;
|
|
|
|
match = of_match_node(sdhci_am654_of_match, pdev->dev.of_node);
|
|
drvdata = match->data;
|
|
|
|
/* Update drvdata based on SoC revision */
|
|
soc = soc_device_match(sdhci_am654_devices);
|
|
if (soc && soc->data)
|
|
drvdata = soc->data;
|
|
|
|
host = sdhci_pltfm_init(pdev, drvdata->pdata, sizeof(*sdhci_am654));
|
|
if (IS_ERR(host))
|
|
return PTR_ERR(host);
|
|
|
|
pltfm_host = sdhci_priv(host);
|
|
sdhci_am654 = sdhci_pltfm_priv(pltfm_host);
|
|
sdhci_am654->flags = drvdata->flags;
|
|
|
|
clk_xin = devm_clk_get(dev, "clk_xin");
|
|
if (IS_ERR(clk_xin)) {
|
|
dev_err(dev, "clk_xin clock not found.\n");
|
|
ret = PTR_ERR(clk_xin);
|
|
goto err_pltfm_free;
|
|
}
|
|
|
|
pltfm_host->clk = clk_xin;
|
|
|
|
/* Clocks are enabled using pm_runtime */
|
|
pm_runtime_enable(dev);
|
|
ret = pm_runtime_resume_and_get(dev);
|
|
if (ret)
|
|
goto pm_runtime_disable;
|
|
|
|
base = devm_platform_ioremap_resource(pdev, 1);
|
|
if (IS_ERR(base)) {
|
|
ret = PTR_ERR(base);
|
|
goto pm_runtime_put;
|
|
}
|
|
|
|
sdhci_am654->base = devm_regmap_init_mmio(dev, base,
|
|
&sdhci_am654_regmap_config);
|
|
if (IS_ERR(sdhci_am654->base)) {
|
|
dev_err(dev, "Failed to initialize regmap\n");
|
|
ret = PTR_ERR(sdhci_am654->base);
|
|
goto pm_runtime_put;
|
|
}
|
|
|
|
ret = sdhci_am654_get_of_property(pdev, sdhci_am654);
|
|
if (ret)
|
|
goto pm_runtime_put;
|
|
|
|
ret = mmc_of_parse(host->mmc);
|
|
if (ret) {
|
|
dev_err(dev, "parsing dt failed (%d)\n", ret);
|
|
goto pm_runtime_put;
|
|
}
|
|
|
|
host->mmc_host_ops.execute_tuning = sdhci_am654_execute_tuning;
|
|
|
|
ret = sdhci_am654_init(host);
|
|
if (ret)
|
|
goto pm_runtime_put;
|
|
|
|
return 0;
|
|
|
|
pm_runtime_put:
|
|
pm_runtime_put_sync(dev);
|
|
pm_runtime_disable:
|
|
pm_runtime_disable(dev);
|
|
err_pltfm_free:
|
|
sdhci_pltfm_free(pdev);
|
|
return ret;
|
|
}
|
|
|
|
static int sdhci_am654_remove(struct platform_device *pdev)
|
|
{
|
|
struct sdhci_host *host = platform_get_drvdata(pdev);
|
|
int ret;
|
|
|
|
sdhci_remove_host(host, true);
|
|
ret = pm_runtime_put_sync(&pdev->dev);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
pm_runtime_disable(&pdev->dev);
|
|
sdhci_pltfm_free(pdev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct platform_driver sdhci_am654_driver = {
|
|
.driver = {
|
|
.name = "sdhci-am654",
|
|
.probe_type = PROBE_PREFER_ASYNCHRONOUS,
|
|
.of_match_table = sdhci_am654_of_match,
|
|
},
|
|
.probe = sdhci_am654_probe,
|
|
.remove = sdhci_am654_remove,
|
|
};
|
|
|
|
module_platform_driver(sdhci_am654_driver);
|
|
|
|
MODULE_DESCRIPTION("Driver for SDHCI Controller on TI's AM654 devices");
|
|
MODULE_AUTHOR("Faiz Abbas <faiz_abbas@ti.com>");
|
|
MODULE_LICENSE("GPL");
|