203 lines
5.7 KiB
C
203 lines
5.7 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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*
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* Copyright (c) 2011, The Linux Foundation. All rights reserved.
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*/
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#include <linux/of.h>
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#include <linux/of_dma.h>
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#include <linux/bitops.h>
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#include <linux/mmc/host.h>
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#include <linux/mmc/card.h>
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#include "mmci.h"
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/* Registers */
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#define DML_CONFIG 0x00
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#define PRODUCER_CRCI_MSK GENMASK(1, 0)
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#define PRODUCER_CRCI_DISABLE 0
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#define PRODUCER_CRCI_X_SEL BIT(0)
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#define PRODUCER_CRCI_Y_SEL BIT(1)
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#define CONSUMER_CRCI_MSK GENMASK(3, 2)
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#define CONSUMER_CRCI_DISABLE 0
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#define CONSUMER_CRCI_X_SEL BIT(2)
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#define CONSUMER_CRCI_Y_SEL BIT(3)
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#define PRODUCER_TRANS_END_EN BIT(4)
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#define BYPASS BIT(16)
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#define DIRECT_MODE BIT(17)
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#define INFINITE_CONS_TRANS BIT(18)
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#define DML_SW_RESET 0x08
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#define DML_PRODUCER_START 0x0c
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#define DML_CONSUMER_START 0x10
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#define DML_PRODUCER_PIPE_LOGICAL_SIZE 0x14
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#define DML_CONSUMER_PIPE_LOGICAL_SIZE 0x18
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#define DML_PIPE_ID 0x1c
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#define PRODUCER_PIPE_ID_SHFT 0
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#define PRODUCER_PIPE_ID_MSK GENMASK(4, 0)
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#define CONSUMER_PIPE_ID_SHFT 16
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#define CONSUMER_PIPE_ID_MSK GENMASK(20, 16)
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#define DML_PRODUCER_BAM_BLOCK_SIZE 0x24
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#define DML_PRODUCER_BAM_TRANS_SIZE 0x28
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/* other definitions */
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#define PRODUCER_PIPE_LOGICAL_SIZE 4096
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#define CONSUMER_PIPE_LOGICAL_SIZE 4096
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#define DML_OFFSET 0x800
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static int qcom_dma_start(struct mmci_host *host, unsigned int *datactrl)
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{
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u32 config;
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void __iomem *base = host->base + DML_OFFSET;
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struct mmc_data *data = host->data;
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int ret = mmci_dmae_start(host, datactrl);
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if (ret)
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return ret;
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if (data->flags & MMC_DATA_READ) {
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/* Read operation: configure DML for producer operation */
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/* Set producer CRCI-x and disable consumer CRCI */
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config = readl_relaxed(base + DML_CONFIG);
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config = (config & ~PRODUCER_CRCI_MSK) | PRODUCER_CRCI_X_SEL;
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config = (config & ~CONSUMER_CRCI_MSK) | CONSUMER_CRCI_DISABLE;
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writel_relaxed(config, base + DML_CONFIG);
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/* Set the Producer BAM block size */
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writel_relaxed(data->blksz, base + DML_PRODUCER_BAM_BLOCK_SIZE);
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/* Set Producer BAM Transaction size */
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writel_relaxed(data->blocks * data->blksz,
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base + DML_PRODUCER_BAM_TRANS_SIZE);
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/* Set Producer Transaction End bit */
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config = readl_relaxed(base + DML_CONFIG);
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config |= PRODUCER_TRANS_END_EN;
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writel_relaxed(config, base + DML_CONFIG);
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/* Trigger producer */
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writel_relaxed(1, base + DML_PRODUCER_START);
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} else {
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/* Write operation: configure DML for consumer operation */
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/* Set consumer CRCI-x and disable producer CRCI*/
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config = readl_relaxed(base + DML_CONFIG);
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config = (config & ~CONSUMER_CRCI_MSK) | CONSUMER_CRCI_X_SEL;
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config = (config & ~PRODUCER_CRCI_MSK) | PRODUCER_CRCI_DISABLE;
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writel_relaxed(config, base + DML_CONFIG);
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/* Clear Producer Transaction End bit */
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config = readl_relaxed(base + DML_CONFIG);
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config &= ~PRODUCER_TRANS_END_EN;
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writel_relaxed(config, base + DML_CONFIG);
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/* Trigger consumer */
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writel_relaxed(1, base + DML_CONSUMER_START);
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}
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/* make sure the dml is configured before dma is triggered */
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wmb();
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return 0;
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}
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static int of_get_dml_pipe_index(struct device_node *np, const char *name)
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{
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int index;
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struct of_phandle_args dma_spec;
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index = of_property_match_string(np, "dma-names", name);
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if (index < 0)
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return -ENODEV;
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if (of_parse_phandle_with_args(np, "dmas", "#dma-cells", index,
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&dma_spec))
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return -ENODEV;
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if (dma_spec.args_count)
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return dma_spec.args[0];
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return -ENODEV;
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}
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/* Initialize the dml hardware connected to SD Card controller */
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static int qcom_dma_setup(struct mmci_host *host)
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{
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u32 config;
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void __iomem *base;
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int consumer_id, producer_id;
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struct device_node *np = host->mmc->parent->of_node;
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if (mmci_dmae_setup(host))
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return -EINVAL;
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consumer_id = of_get_dml_pipe_index(np, "tx");
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producer_id = of_get_dml_pipe_index(np, "rx");
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if (producer_id < 0 || consumer_id < 0) {
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mmci_dmae_release(host);
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return -EINVAL;
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}
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base = host->base + DML_OFFSET;
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/* Reset the DML block */
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writel_relaxed(1, base + DML_SW_RESET);
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/* Disable the producer and consumer CRCI */
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config = (PRODUCER_CRCI_DISABLE | CONSUMER_CRCI_DISABLE);
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/*
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* Disable the bypass mode. Bypass mode will only be used
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* if data transfer is to happen in PIO mode and don't
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* want the BAM interface to connect with SDCC-DML.
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*/
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config &= ~BYPASS;
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/*
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* Disable direct mode as we don't DML to MASTER the AHB bus.
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* BAM connected with DML should MASTER the AHB bus.
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*/
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config &= ~DIRECT_MODE;
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/*
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* Disable infinite mode transfer as we won't be doing any
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* infinite size data transfers. All data transfer will be
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* of finite data size.
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*/
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config &= ~INFINITE_CONS_TRANS;
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writel_relaxed(config, base + DML_CONFIG);
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/*
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* Initialize the logical BAM pipe size for producer
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* and consumer.
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*/
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writel_relaxed(PRODUCER_PIPE_LOGICAL_SIZE,
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base + DML_PRODUCER_PIPE_LOGICAL_SIZE);
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writel_relaxed(CONSUMER_PIPE_LOGICAL_SIZE,
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base + DML_CONSUMER_PIPE_LOGICAL_SIZE);
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/* Initialize Producer/consumer pipe id */
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writel_relaxed(producer_id | (consumer_id << CONSUMER_PIPE_ID_SHFT),
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base + DML_PIPE_ID);
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/* Make sure dml initialization is finished */
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mb();
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return 0;
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}
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static u32 qcom_get_dctrl_cfg(struct mmci_host *host)
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{
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return MCI_DPSM_ENABLE | (host->data->blksz << 4);
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}
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static struct mmci_host_ops qcom_variant_ops = {
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.prep_data = mmci_dmae_prep_data,
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.unprep_data = mmci_dmae_unprep_data,
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.get_datactrl_cfg = qcom_get_dctrl_cfg,
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.get_next_data = mmci_dmae_get_next_data,
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.dma_setup = qcom_dma_setup,
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.dma_release = mmci_dmae_release,
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.dma_start = qcom_dma_start,
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.dma_finalize = mmci_dmae_finalize,
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.dma_error = mmci_dmae_error,
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};
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void qcom_variant_init(struct mmci_host *host)
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{
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host->ops = &qcom_variant_ops;
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}
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