130 lines
2.9 KiB
C
130 lines
2.9 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Allwinner Hantro G2 VPU codec driver
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*
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* Copyright (C) 2021 Jernej Skrabec <jernej.skrabec@gmail.com>
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*/
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#include <linux/clk.h>
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#include "hantro.h"
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static const struct hantro_fmt sunxi_vpu_postproc_fmts[] = {
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{
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.fourcc = V4L2_PIX_FMT_NV12,
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.codec_mode = HANTRO_MODE_NONE,
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.postprocessed = true,
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.frmsize = {
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.min_width = FMT_MIN_WIDTH,
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.max_width = FMT_UHD_WIDTH,
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.step_width = 32,
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.min_height = FMT_MIN_HEIGHT,
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.max_height = FMT_UHD_HEIGHT,
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.step_height = 32,
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},
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},
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{
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.fourcc = V4L2_PIX_FMT_P010,
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.codec_mode = HANTRO_MODE_NONE,
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.postprocessed = true,
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.frmsize = {
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.min_width = FMT_MIN_WIDTH,
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.max_width = FMT_UHD_WIDTH,
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.step_width = 32,
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.min_height = FMT_MIN_HEIGHT,
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.max_height = FMT_UHD_HEIGHT,
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.step_height = 32,
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},
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},
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};
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static const struct hantro_fmt sunxi_vpu_dec_fmts[] = {
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{
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.fourcc = V4L2_PIX_FMT_NV12_4L4,
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.codec_mode = HANTRO_MODE_NONE,
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.match_depth = true,
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.frmsize = {
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.min_width = FMT_MIN_WIDTH,
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.max_width = FMT_UHD_WIDTH,
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.step_width = 32,
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.min_height = FMT_MIN_HEIGHT,
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.max_height = FMT_UHD_HEIGHT,
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.step_height = 32,
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},
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},
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{
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.fourcc = V4L2_PIX_FMT_P010_4L4,
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.codec_mode = HANTRO_MODE_NONE,
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.match_depth = true,
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.frmsize = {
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.min_width = FMT_MIN_WIDTH,
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.max_width = FMT_UHD_WIDTH,
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.step_width = 32,
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.min_height = FMT_MIN_HEIGHT,
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.max_height = FMT_UHD_HEIGHT,
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.step_height = 32,
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},
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},
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{
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.fourcc = V4L2_PIX_FMT_VP9_FRAME,
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.codec_mode = HANTRO_MODE_VP9_DEC,
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.max_depth = 2,
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.frmsize = {
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.min_width = FMT_MIN_WIDTH,
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.max_width = FMT_UHD_WIDTH,
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.step_width = 32,
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.min_height = FMT_MIN_HEIGHT,
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.max_height = FMT_UHD_HEIGHT,
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.step_height = 32,
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},
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},
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};
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static int sunxi_vpu_hw_init(struct hantro_dev *vpu)
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{
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clk_set_rate(vpu->clocks[0].clk, 300000000);
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return 0;
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}
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static void sunxi_vpu_reset(struct hantro_ctx *ctx)
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{
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struct hantro_dev *vpu = ctx->dev;
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reset_control_reset(vpu->resets);
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}
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static const struct hantro_codec_ops sunxi_vpu_codec_ops[] = {
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[HANTRO_MODE_VP9_DEC] = {
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.run = hantro_g2_vp9_dec_run,
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.done = hantro_g2_vp9_dec_done,
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.reset = sunxi_vpu_reset,
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.init = hantro_vp9_dec_init,
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.exit = hantro_vp9_dec_exit,
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},
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};
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static const struct hantro_irq sunxi_irqs[] = {
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{ NULL, hantro_g2_irq },
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};
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static const char * const sunxi_clk_names[] = { "mod", "bus" };
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const struct hantro_variant sunxi_vpu_variant = {
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.dec_fmts = sunxi_vpu_dec_fmts,
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.num_dec_fmts = ARRAY_SIZE(sunxi_vpu_dec_fmts),
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.postproc_fmts = sunxi_vpu_postproc_fmts,
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.num_postproc_fmts = ARRAY_SIZE(sunxi_vpu_postproc_fmts),
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.postproc_ops = &hantro_g2_postproc_ops,
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.codec = HANTRO_VP9_DECODER,
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.codec_ops = sunxi_vpu_codec_ops,
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.init = sunxi_vpu_hw_init,
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.irqs = sunxi_irqs,
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.num_irqs = ARRAY_SIZE(sunxi_irqs),
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.clk_names = sunxi_clk_names,
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.num_clocks = ARRAY_SIZE(sunxi_clk_names),
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.double_buffer = 1,
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.legacy_regs = 1,
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.late_postproc = 1,
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};
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