519 lines
13 KiB
C
519 lines
13 KiB
C
/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
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/* Authors: Cheng Xu <chengyou@linux.alibaba.com> */
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/* Kai Shen <kaishen@linux.alibaba.com> */
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/* Copyright (c) 2020-2022, Alibaba Group. */
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#ifndef __ERDMA_HW_H__
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#define __ERDMA_HW_H__
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#include <linux/kernel.h>
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#include <linux/types.h>
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/* PCIe device related definition. */
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#define PCI_VENDOR_ID_ALIBABA 0x1ded
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#define ERDMA_PCI_WIDTH 64
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#define ERDMA_FUNC_BAR 0
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#define ERDMA_MISX_BAR 2
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#define ERDMA_BAR_MASK (BIT(ERDMA_FUNC_BAR) | BIT(ERDMA_MISX_BAR))
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/* MSI-X related. */
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#define ERDMA_NUM_MSIX_VEC 32U
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#define ERDMA_MSIX_VECTOR_CMDQ 0
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/* PCIe Bar0 Registers. */
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#define ERDMA_REGS_VERSION_REG 0x0
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#define ERDMA_REGS_DEV_CTRL_REG 0x10
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#define ERDMA_REGS_DEV_ST_REG 0x14
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#define ERDMA_REGS_NETDEV_MAC_L_REG 0x18
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#define ERDMA_REGS_NETDEV_MAC_H_REG 0x1C
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#define ERDMA_REGS_CMDQ_SQ_ADDR_L_REG 0x20
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#define ERDMA_REGS_CMDQ_SQ_ADDR_H_REG 0x24
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#define ERDMA_REGS_CMDQ_CQ_ADDR_L_REG 0x28
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#define ERDMA_REGS_CMDQ_CQ_ADDR_H_REG 0x2C
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#define ERDMA_REGS_CMDQ_DEPTH_REG 0x30
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#define ERDMA_REGS_CMDQ_EQ_DEPTH_REG 0x34
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#define ERDMA_REGS_CMDQ_EQ_ADDR_L_REG 0x38
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#define ERDMA_REGS_CMDQ_EQ_ADDR_H_REG 0x3C
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#define ERDMA_REGS_AEQ_ADDR_L_REG 0x40
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#define ERDMA_REGS_AEQ_ADDR_H_REG 0x44
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#define ERDMA_REGS_AEQ_DEPTH_REG 0x48
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#define ERDMA_REGS_GRP_NUM_REG 0x4c
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#define ERDMA_REGS_AEQ_DB_REG 0x50
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#define ERDMA_CMDQ_SQ_DB_HOST_ADDR_REG 0x60
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#define ERDMA_CMDQ_CQ_DB_HOST_ADDR_REG 0x68
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#define ERDMA_CMDQ_EQ_DB_HOST_ADDR_REG 0x70
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#define ERDMA_AEQ_DB_HOST_ADDR_REG 0x78
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#define ERDMA_REGS_STATS_TSO_IN_PKTS_REG 0x80
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#define ERDMA_REGS_STATS_TSO_OUT_PKTS_REG 0x88
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#define ERDMA_REGS_STATS_TSO_OUT_BYTES_REG 0x90
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#define ERDMA_REGS_STATS_TX_DROP_PKTS_REG 0x98
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#define ERDMA_REGS_STATS_TX_BPS_METER_DROP_PKTS_REG 0xa0
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#define ERDMA_REGS_STATS_TX_PPS_METER_DROP_PKTS_REG 0xa8
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#define ERDMA_REGS_STATS_RX_PKTS_REG 0xc0
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#define ERDMA_REGS_STATS_RX_BYTES_REG 0xc8
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#define ERDMA_REGS_STATS_RX_DROP_PKTS_REG 0xd0
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#define ERDMA_REGS_STATS_RX_BPS_METER_DROP_PKTS_REG 0xd8
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#define ERDMA_REGS_STATS_RX_PPS_METER_DROP_PKTS_REG 0xe0
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#define ERDMA_REGS_CEQ_DB_BASE_REG 0x100
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#define ERDMA_CMDQ_SQDB_REG 0x200
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#define ERDMA_CMDQ_CQDB_REG 0x300
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/* DEV_CTRL_REG details. */
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#define ERDMA_REG_DEV_CTRL_RESET_MASK 0x00000001
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#define ERDMA_REG_DEV_CTRL_INIT_MASK 0x00000002
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/* DEV_ST_REG details. */
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#define ERDMA_REG_DEV_ST_RESET_DONE_MASK 0x00000001U
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#define ERDMA_REG_DEV_ST_INIT_DONE_MASK 0x00000002U
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/* eRDMA PCIe DBs definition. */
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#define ERDMA_BAR_DB_SPACE_BASE 4096
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#define ERDMA_BAR_SQDB_SPACE_OFFSET ERDMA_BAR_DB_SPACE_BASE
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#define ERDMA_BAR_SQDB_SPACE_SIZE (384 * 1024)
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#define ERDMA_BAR_RQDB_SPACE_OFFSET \
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(ERDMA_BAR_SQDB_SPACE_OFFSET + ERDMA_BAR_SQDB_SPACE_SIZE)
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#define ERDMA_BAR_RQDB_SPACE_SIZE (96 * 1024)
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#define ERDMA_BAR_CQDB_SPACE_OFFSET \
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(ERDMA_BAR_RQDB_SPACE_OFFSET + ERDMA_BAR_RQDB_SPACE_SIZE)
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/* Doorbell page resources related. */
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/*
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* Max # of parallelly issued directSQE is 3072 per device,
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* hardware organizes this into 24 group, per group has 128 credits.
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*/
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#define ERDMA_DWQE_MAX_GRP_CNT 24
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#define ERDMA_DWQE_NUM_PER_GRP 128
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#define ERDMA_DWQE_TYPE0_CNT 64
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#define ERDMA_DWQE_TYPE1_CNT 496
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/* type1 DB contains 2 DBs, takes 256Byte. */
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#define ERDMA_DWQE_TYPE1_CNT_PER_PAGE 16
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#define ERDMA_SDB_SHARED_PAGE_INDEX 95
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/* Doorbell related. */
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#define ERDMA_DB_SIZE 8
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#define ERDMA_CQDB_IDX_MASK GENMASK_ULL(63, 56)
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#define ERDMA_CQDB_CQN_MASK GENMASK_ULL(55, 32)
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#define ERDMA_CQDB_ARM_MASK BIT_ULL(31)
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#define ERDMA_CQDB_SOL_MASK BIT_ULL(30)
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#define ERDMA_CQDB_CMDSN_MASK GENMASK_ULL(29, 28)
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#define ERDMA_CQDB_CI_MASK GENMASK_ULL(23, 0)
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#define ERDMA_EQDB_ARM_MASK BIT(31)
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#define ERDMA_EQDB_CI_MASK GENMASK_ULL(23, 0)
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#define ERDMA_PAGE_SIZE_SUPPORT 0x7FFFF000
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/* Hardware page size definition */
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#define ERDMA_HW_PAGE_SHIFT 12
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#define ERDMA_HW_PAGE_SIZE 4096
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/* WQE related. */
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#define EQE_SIZE 16
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#define EQE_SHIFT 4
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#define RQE_SIZE 32
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#define RQE_SHIFT 5
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#define CQE_SIZE 32
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#define CQE_SHIFT 5
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#define SQEBB_SIZE 32
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#define SQEBB_SHIFT 5
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#define SQEBB_MASK (~(SQEBB_SIZE - 1))
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#define SQEBB_ALIGN(size) ((size + SQEBB_SIZE - 1) & SQEBB_MASK)
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#define SQEBB_COUNT(size) (SQEBB_ALIGN(size) >> SQEBB_SHIFT)
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#define ERDMA_MAX_SQE_SIZE 128
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#define ERDMA_MAX_WQEBB_PER_SQE 4
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/* CMDQ related. */
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#define ERDMA_CMDQ_MAX_OUTSTANDING 128
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#define ERDMA_CMDQ_SQE_SIZE 64
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/* cmdq sub module definition. */
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enum CMDQ_WQE_SUB_MOD {
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CMDQ_SUBMOD_RDMA = 0,
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CMDQ_SUBMOD_COMMON = 1
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};
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enum CMDQ_RDMA_OPCODE {
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CMDQ_OPCODE_QUERY_DEVICE = 0,
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CMDQ_OPCODE_CREATE_QP = 1,
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CMDQ_OPCODE_DESTROY_QP = 2,
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CMDQ_OPCODE_MODIFY_QP = 3,
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CMDQ_OPCODE_CREATE_CQ = 4,
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CMDQ_OPCODE_DESTROY_CQ = 5,
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CMDQ_OPCODE_REG_MR = 8,
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CMDQ_OPCODE_DEREG_MR = 9
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};
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enum CMDQ_COMMON_OPCODE {
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CMDQ_OPCODE_CREATE_EQ = 0,
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CMDQ_OPCODE_DESTROY_EQ = 1,
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CMDQ_OPCODE_QUERY_FW_INFO = 2,
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CMDQ_OPCODE_CONF_MTU = 3,
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};
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/* cmdq-SQE HDR */
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#define ERDMA_CMD_HDR_WQEBB_CNT_MASK GENMASK_ULL(54, 52)
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#define ERDMA_CMD_HDR_CONTEXT_COOKIE_MASK GENMASK_ULL(47, 32)
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#define ERDMA_CMD_HDR_SUB_MOD_MASK GENMASK_ULL(25, 24)
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#define ERDMA_CMD_HDR_OPCODE_MASK GENMASK_ULL(23, 16)
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#define ERDMA_CMD_HDR_WQEBB_INDEX_MASK GENMASK_ULL(15, 0)
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struct erdma_cmdq_destroy_cq_req {
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u64 hdr;
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u32 cqn;
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};
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#define ERDMA_EQ_TYPE_AEQ 0
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#define ERDMA_EQ_TYPE_CEQ 1
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struct erdma_cmdq_create_eq_req {
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u64 hdr;
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u64 qbuf_addr;
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u8 vector_idx;
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u8 eqn;
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u8 depth;
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u8 qtype;
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u32 db_dma_addr_l;
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u32 db_dma_addr_h;
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};
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struct erdma_cmdq_destroy_eq_req {
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u64 hdr;
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u64 rsvd0;
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u8 vector_idx;
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u8 eqn;
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u8 rsvd1;
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u8 qtype;
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};
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struct erdma_cmdq_config_mtu_req {
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u64 hdr;
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u32 mtu;
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};
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/* create_cq cfg0 */
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#define ERDMA_CMD_CREATE_CQ_DEPTH_MASK GENMASK(31, 24)
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#define ERDMA_CMD_CREATE_CQ_PAGESIZE_MASK GENMASK(23, 20)
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#define ERDMA_CMD_CREATE_CQ_CQN_MASK GENMASK(19, 0)
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/* create_cq cfg1 */
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#define ERDMA_CMD_CREATE_CQ_MTT_CNT_MASK GENMASK(31, 16)
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#define ERDMA_CMD_CREATE_CQ_MTT_TYPE_MASK BIT(15)
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#define ERDMA_CMD_CREATE_CQ_EQN_MASK GENMASK(9, 0)
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struct erdma_cmdq_create_cq_req {
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u64 hdr;
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u32 cfg0;
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u32 qbuf_addr_l;
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u32 qbuf_addr_h;
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u32 cfg1;
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u64 cq_db_info_addr;
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u32 first_page_offset;
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};
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/* regmr/deregmr cfg0 */
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#define ERDMA_CMD_MR_VALID_MASK BIT(31)
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#define ERDMA_CMD_MR_KEY_MASK GENMASK(27, 20)
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#define ERDMA_CMD_MR_MPT_IDX_MASK GENMASK(19, 0)
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/* regmr cfg1 */
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#define ERDMA_CMD_REGMR_PD_MASK GENMASK(31, 12)
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#define ERDMA_CMD_REGMR_TYPE_MASK GENMASK(7, 6)
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#define ERDMA_CMD_REGMR_RIGHT_MASK GENMASK(5, 2)
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#define ERDMA_CMD_REGMR_ACC_MODE_MASK GENMASK(1, 0)
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/* regmr cfg2 */
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#define ERDMA_CMD_REGMR_PAGESIZE_MASK GENMASK(31, 27)
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#define ERDMA_CMD_REGMR_MTT_TYPE_MASK GENMASK(21, 20)
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#define ERDMA_CMD_REGMR_MTT_CNT_MASK GENMASK(19, 0)
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struct erdma_cmdq_reg_mr_req {
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u64 hdr;
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u32 cfg0;
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u32 cfg1;
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u64 start_va;
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u32 size;
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u32 cfg2;
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u64 phy_addr[4];
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};
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struct erdma_cmdq_dereg_mr_req {
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u64 hdr;
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u32 cfg;
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};
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/* modify qp cfg */
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#define ERDMA_CMD_MODIFY_QP_STATE_MASK GENMASK(31, 24)
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#define ERDMA_CMD_MODIFY_QP_CC_MASK GENMASK(23, 20)
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#define ERDMA_CMD_MODIFY_QP_QPN_MASK GENMASK(19, 0)
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struct erdma_cmdq_modify_qp_req {
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u64 hdr;
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u32 cfg;
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u32 cookie;
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__be32 dip;
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__be32 sip;
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__be16 sport;
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__be16 dport;
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u32 send_nxt;
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u32 recv_nxt;
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};
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/* create qp cfg0 */
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#define ERDMA_CMD_CREATE_QP_SQ_DEPTH_MASK GENMASK(31, 20)
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#define ERDMA_CMD_CREATE_QP_QPN_MASK GENMASK(19, 0)
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/* create qp cfg1 */
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#define ERDMA_CMD_CREATE_QP_RQ_DEPTH_MASK GENMASK(31, 20)
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#define ERDMA_CMD_CREATE_QP_PD_MASK GENMASK(19, 0)
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/* create qp cqn_mtt_cfg */
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#define ERDMA_CMD_CREATE_QP_PAGE_SIZE_MASK GENMASK(31, 28)
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#define ERDMA_CMD_CREATE_QP_CQN_MASK GENMASK(23, 0)
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/* create qp mtt_cfg */
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#define ERDMA_CMD_CREATE_QP_PAGE_OFFSET_MASK GENMASK(31, 12)
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#define ERDMA_CMD_CREATE_QP_MTT_CNT_MASK GENMASK(11, 1)
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#define ERDMA_CMD_CREATE_QP_MTT_TYPE_MASK BIT(0)
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#define ERDMA_CMDQ_CREATE_QP_RESP_COOKIE_MASK GENMASK_ULL(31, 0)
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struct erdma_cmdq_create_qp_req {
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u64 hdr;
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u32 cfg0;
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u32 cfg1;
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u32 sq_cqn_mtt_cfg;
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u32 rq_cqn_mtt_cfg;
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u64 sq_buf_addr;
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u64 rq_buf_addr;
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u32 sq_mtt_cfg;
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u32 rq_mtt_cfg;
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u64 sq_db_info_dma_addr;
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u64 rq_db_info_dma_addr;
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};
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struct erdma_cmdq_destroy_qp_req {
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u64 hdr;
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u32 qpn;
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};
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/* cap qword 0 definition */
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#define ERDMA_CMD_DEV_CAP_MAX_CQE_MASK GENMASK_ULL(47, 40)
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#define ERDMA_CMD_DEV_CAP_MAX_RECV_WR_MASK GENMASK_ULL(23, 16)
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#define ERDMA_CMD_DEV_CAP_MAX_MR_SIZE_MASK GENMASK_ULL(7, 0)
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/* cap qword 1 definition */
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#define ERDMA_CMD_DEV_CAP_DMA_LOCAL_KEY_MASK GENMASK_ULL(63, 32)
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#define ERDMA_CMD_DEV_CAP_DEFAULT_CC_MASK GENMASK_ULL(31, 28)
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#define ERDMA_CMD_DEV_CAP_QBLOCK_MASK GENMASK_ULL(27, 16)
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#define ERDMA_CMD_DEV_CAP_MAX_MW_MASK GENMASK_ULL(7, 0)
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#define ERDMA_NQP_PER_QBLOCK 1024
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#define ERDMA_CMD_INFO0_FW_VER_MASK GENMASK_ULL(31, 0)
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/* CQE hdr */
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#define ERDMA_CQE_HDR_OWNER_MASK BIT(31)
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#define ERDMA_CQE_HDR_OPCODE_MASK GENMASK(23, 16)
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#define ERDMA_CQE_HDR_QTYPE_MASK GENMASK(15, 8)
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#define ERDMA_CQE_HDR_SYNDROME_MASK GENMASK(7, 0)
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#define ERDMA_CQE_QTYPE_SQ 0
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#define ERDMA_CQE_QTYPE_RQ 1
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#define ERDMA_CQE_QTYPE_CMDQ 2
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struct erdma_cqe {
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__be32 hdr;
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__be32 qe_idx;
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__be32 qpn;
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union {
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__le32 imm_data;
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__be32 inv_rkey;
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};
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__be32 size;
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__be32 rsvd[3];
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};
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struct erdma_sge {
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__aligned_le64 laddr;
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__le32 length;
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__le32 lkey;
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};
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/* Receive Queue Element */
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struct erdma_rqe {
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__le16 qe_idx;
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__le16 rsvd0;
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__le32 qpn;
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__le32 rsvd1;
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__le32 rsvd2;
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__le64 to;
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__le32 length;
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__le32 stag;
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};
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/* SQE */
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#define ERDMA_SQE_HDR_SGL_LEN_MASK GENMASK_ULL(63, 56)
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#define ERDMA_SQE_HDR_WQEBB_CNT_MASK GENMASK_ULL(54, 52)
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#define ERDMA_SQE_HDR_QPN_MASK GENMASK_ULL(51, 32)
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#define ERDMA_SQE_HDR_OPCODE_MASK GENMASK_ULL(31, 27)
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#define ERDMA_SQE_HDR_DWQE_MASK BIT_ULL(26)
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#define ERDMA_SQE_HDR_INLINE_MASK BIT_ULL(25)
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#define ERDMA_SQE_HDR_FENCE_MASK BIT_ULL(24)
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#define ERDMA_SQE_HDR_SE_MASK BIT_ULL(23)
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#define ERDMA_SQE_HDR_CE_MASK BIT_ULL(22)
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#define ERDMA_SQE_HDR_WQEBB_INDEX_MASK GENMASK_ULL(15, 0)
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/* REG MR attrs */
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#define ERDMA_SQE_MR_MODE_MASK GENMASK(1, 0)
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#define ERDMA_SQE_MR_ACCESS_MASK GENMASK(5, 2)
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#define ERDMA_SQE_MR_MTT_TYPE_MASK GENMASK(7, 6)
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#define ERDMA_SQE_MR_MTT_CNT_MASK GENMASK(31, 12)
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struct erdma_write_sqe {
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__le64 hdr;
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__be32 imm_data;
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__le32 length;
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__le32 sink_stag;
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__le32 sink_to_l;
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__le32 sink_to_h;
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__le32 rsvd;
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struct erdma_sge sgl[0];
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};
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struct erdma_send_sqe {
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__le64 hdr;
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union {
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__be32 imm_data;
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__le32 invalid_stag;
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};
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__le32 length;
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struct erdma_sge sgl[0];
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};
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struct erdma_readreq_sqe {
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__le64 hdr;
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__le32 invalid_stag;
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__le32 length;
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__le32 sink_stag;
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__le32 sink_to_l;
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__le32 sink_to_h;
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__le32 rsvd;
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};
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struct erdma_reg_mr_sqe {
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__le64 hdr;
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__le64 addr;
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__le32 length;
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__le32 stag;
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__le32 attrs;
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__le32 rsvd;
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};
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/* EQ related. */
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#define ERDMA_DEFAULT_EQ_DEPTH 4096
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/* ceqe */
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#define ERDMA_CEQE_HDR_DB_MASK BIT_ULL(63)
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#define ERDMA_CEQE_HDR_PI_MASK GENMASK_ULL(55, 32)
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#define ERDMA_CEQE_HDR_O_MASK BIT_ULL(31)
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#define ERDMA_CEQE_HDR_CQN_MASK GENMASK_ULL(19, 0)
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/* aeqe */
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#define ERDMA_AEQE_HDR_O_MASK BIT(31)
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#define ERDMA_AEQE_HDR_TYPE_MASK GENMASK(23, 16)
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#define ERDMA_AEQE_HDR_SUBTYPE_MASK GENMASK(7, 0)
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#define ERDMA_AE_TYPE_QP_FATAL_EVENT 0
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#define ERDMA_AE_TYPE_QP_ERQ_ERR_EVENT 1
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#define ERDMA_AE_TYPE_ACC_ERR_EVENT 2
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#define ERDMA_AE_TYPE_CQ_ERR 3
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#define ERDMA_AE_TYPE_OTHER_ERROR 4
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struct erdma_aeqe {
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__le32 hdr;
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__le32 event_data0;
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__le32 event_data1;
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__le32 rsvd;
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};
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enum erdma_opcode {
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ERDMA_OP_WRITE = 0,
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ERDMA_OP_READ = 1,
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ERDMA_OP_SEND = 2,
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ERDMA_OP_SEND_WITH_IMM = 3,
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ERDMA_OP_RECEIVE = 4,
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ERDMA_OP_RECV_IMM = 5,
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ERDMA_OP_RECV_INV = 6,
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ERDMA_OP_RSVD0 = 7,
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ERDMA_OP_RSVD1 = 8,
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ERDMA_OP_WRITE_WITH_IMM = 9,
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ERDMA_OP_RSVD2 = 10,
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ERDMA_OP_RSVD3 = 11,
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ERDMA_OP_RSP_SEND_IMM = 12,
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ERDMA_OP_SEND_WITH_INV = 13,
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ERDMA_OP_REG_MR = 14,
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ERDMA_OP_LOCAL_INV = 15,
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ERDMA_OP_READ_WITH_INV = 16,
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ERDMA_NUM_OPCODES = 17,
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ERDMA_OP_INVALID = ERDMA_NUM_OPCODES + 1
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};
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enum erdma_wc_status {
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ERDMA_WC_SUCCESS = 0,
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ERDMA_WC_GENERAL_ERR = 1,
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ERDMA_WC_RECV_WQE_FORMAT_ERR = 2,
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ERDMA_WC_RECV_STAG_INVALID_ERR = 3,
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ERDMA_WC_RECV_ADDR_VIOLATION_ERR = 4,
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ERDMA_WC_RECV_RIGHT_VIOLATION_ERR = 5,
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ERDMA_WC_RECV_PDID_ERR = 6,
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ERDMA_WC_RECV_WARRPING_ERR = 7,
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ERDMA_WC_SEND_WQE_FORMAT_ERR = 8,
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ERDMA_WC_SEND_WQE_ORD_EXCEED = 9,
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ERDMA_WC_SEND_STAG_INVALID_ERR = 10,
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ERDMA_WC_SEND_ADDR_VIOLATION_ERR = 11,
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ERDMA_WC_SEND_RIGHT_VIOLATION_ERR = 12,
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ERDMA_WC_SEND_PDID_ERR = 13,
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ERDMA_WC_SEND_WARRPING_ERR = 14,
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ERDMA_WC_FLUSH_ERR = 15,
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ERDMA_WC_RETRY_EXC_ERR = 16,
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ERDMA_NUM_WC_STATUS
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};
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enum erdma_vendor_err {
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ERDMA_WC_VENDOR_NO_ERR = 0,
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ERDMA_WC_VENDOR_INVALID_RQE = 1,
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ERDMA_WC_VENDOR_RQE_INVALID_STAG = 2,
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ERDMA_WC_VENDOR_RQE_ADDR_VIOLATION = 3,
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ERDMA_WC_VENDOR_RQE_ACCESS_RIGHT_ERR = 4,
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ERDMA_WC_VENDOR_RQE_INVALID_PD = 5,
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ERDMA_WC_VENDOR_RQE_WRAP_ERR = 6,
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ERDMA_WC_VENDOR_INVALID_SQE = 0x20,
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ERDMA_WC_VENDOR_ZERO_ORD = 0x21,
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ERDMA_WC_VENDOR_SQE_INVALID_STAG = 0x30,
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ERDMA_WC_VENDOR_SQE_ADDR_VIOLATION = 0x31,
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ERDMA_WC_VENDOR_SQE_ACCESS_ERR = 0x32,
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ERDMA_WC_VENDOR_SQE_INVALID_PD = 0x33,
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ERDMA_WC_VENDOR_SQE_WARP_ERR = 0x34
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};
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#endif
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