354 lines
8.8 KiB
C
354 lines
8.8 KiB
C
// SPDX-License-Identifier: GPL-2.0
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// Copyright (c) 2019 Nuvoton Technology corporation.
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#include <linux/clk.h>
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#include <linux/device.h>
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#include <linux/mfd/syscon.h>
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#include <linux/io.h>
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#include <linux/iio/iio.h>
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#include <linux/interrupt.h>
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#include <linux/kernel.h>
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#include <linux/mod_devicetable.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/property.h>
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#include <linux/regmap.h>
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#include <linux/regulator/consumer.h>
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#include <linux/spinlock.h>
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#include <linux/uaccess.h>
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#include <linux/reset.h>
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struct npcm_adc_info {
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u32 data_mask;
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u32 internal_vref;
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u32 res_bits;
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};
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struct npcm_adc {
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bool int_status;
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u32 adc_sample_hz;
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struct device *dev;
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void __iomem *regs;
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struct clk *adc_clk;
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wait_queue_head_t wq;
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struct regulator *vref;
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struct reset_control *reset;
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/*
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* Lock to protect the device state during a potential concurrent
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* read access from userspace. Reading a raw value requires a sequence
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* of register writes, then a wait for a event and finally a register
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* read, during which userspace could issue another read request.
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* This lock protects a read access from ocurring before another one
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* has finished.
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*/
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struct mutex lock;
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const struct npcm_adc_info *data;
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};
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/* ADC registers */
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#define NPCM_ADCCON 0x00
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#define NPCM_ADCDATA 0x04
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/* ADCCON Register Bits */
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#define NPCM_ADCCON_ADC_INT_EN BIT(21)
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#define NPCM_ADCCON_REFSEL BIT(19)
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#define NPCM_ADCCON_ADC_INT_ST BIT(18)
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#define NPCM_ADCCON_ADC_EN BIT(17)
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#define NPCM_ADCCON_ADC_RST BIT(16)
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#define NPCM_ADCCON_ADC_CONV BIT(13)
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#define NPCM_ADCCON_CH_MASK GENMASK(27, 24)
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#define NPCM_ADCCON_CH(x) ((x) << 24)
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#define NPCM_ADCCON_DIV_SHIFT 1
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#define NPCM_ADCCON_DIV_MASK GENMASK(8, 1)
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#define NPCM_ADC_ENABLE (NPCM_ADCCON_ADC_EN | NPCM_ADCCON_ADC_INT_EN)
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/* ADC General Definition */
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static const struct npcm_adc_info npxm7xx_adc_info = {
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.data_mask = GENMASK(9, 0),
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.internal_vref = 2048,
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.res_bits = 10,
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};
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static const struct npcm_adc_info npxm8xx_adc_info = {
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.data_mask = GENMASK(11, 0),
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.internal_vref = 1229,
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.res_bits = 12,
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};
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#define NPCM_ADC_CHAN(ch) { \
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.type = IIO_VOLTAGE, \
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.indexed = 1, \
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.channel = ch, \
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.info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
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.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \
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BIT(IIO_CHAN_INFO_SAMP_FREQ), \
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}
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static const struct iio_chan_spec npcm_adc_iio_channels[] = {
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NPCM_ADC_CHAN(0),
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NPCM_ADC_CHAN(1),
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NPCM_ADC_CHAN(2),
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NPCM_ADC_CHAN(3),
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NPCM_ADC_CHAN(4),
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NPCM_ADC_CHAN(5),
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NPCM_ADC_CHAN(6),
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NPCM_ADC_CHAN(7),
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};
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static irqreturn_t npcm_adc_isr(int irq, void *data)
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{
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u32 regtemp;
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struct iio_dev *indio_dev = data;
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struct npcm_adc *info = iio_priv(indio_dev);
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regtemp = ioread32(info->regs + NPCM_ADCCON);
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if (regtemp & NPCM_ADCCON_ADC_INT_ST) {
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iowrite32(regtemp, info->regs + NPCM_ADCCON);
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wake_up_interruptible(&info->wq);
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info->int_status = true;
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}
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return IRQ_HANDLED;
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}
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static int npcm_adc_read(struct npcm_adc *info, int *val, u8 channel)
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{
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int ret;
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u32 regtemp;
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/* Select ADC channel */
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regtemp = ioread32(info->regs + NPCM_ADCCON);
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regtemp &= ~NPCM_ADCCON_CH_MASK;
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info->int_status = false;
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iowrite32(regtemp | NPCM_ADCCON_CH(channel) |
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NPCM_ADCCON_ADC_CONV, info->regs + NPCM_ADCCON);
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ret = wait_event_interruptible_timeout(info->wq, info->int_status,
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msecs_to_jiffies(10));
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if (ret == 0) {
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regtemp = ioread32(info->regs + NPCM_ADCCON);
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if (regtemp & NPCM_ADCCON_ADC_CONV) {
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/* if conversion failed - reset ADC module */
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reset_control_assert(info->reset);
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msleep(100);
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reset_control_deassert(info->reset);
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msleep(100);
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/* Enable ADC and start conversion module */
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iowrite32(NPCM_ADC_ENABLE | NPCM_ADCCON_ADC_CONV,
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info->regs + NPCM_ADCCON);
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dev_err(info->dev, "RESET ADC Complete\n");
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}
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return -ETIMEDOUT;
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}
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if (ret < 0)
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return ret;
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*val = ioread32(info->regs + NPCM_ADCDATA);
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*val &= info->data->data_mask;
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return 0;
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}
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static int npcm_adc_read_raw(struct iio_dev *indio_dev,
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struct iio_chan_spec const *chan, int *val,
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int *val2, long mask)
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{
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int ret;
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int vref_uv;
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struct npcm_adc *info = iio_priv(indio_dev);
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switch (mask) {
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case IIO_CHAN_INFO_RAW:
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mutex_lock(&info->lock);
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ret = npcm_adc_read(info, val, chan->channel);
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mutex_unlock(&info->lock);
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if (ret) {
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dev_err(info->dev, "NPCM ADC read failed\n");
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return ret;
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}
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return IIO_VAL_INT;
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case IIO_CHAN_INFO_SCALE:
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if (!IS_ERR(info->vref)) {
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vref_uv = regulator_get_voltage(info->vref);
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*val = vref_uv / 1000;
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} else {
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*val = info->data->internal_vref;
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}
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*val2 = info->data->res_bits;
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return IIO_VAL_FRACTIONAL_LOG2;
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case IIO_CHAN_INFO_SAMP_FREQ:
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*val = info->adc_sample_hz;
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return IIO_VAL_INT;
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default:
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return -EINVAL;
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}
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return 0;
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}
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static const struct iio_info npcm_adc_iio_info = {
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.read_raw = &npcm_adc_read_raw,
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};
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static const struct of_device_id npcm_adc_match[] = {
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{ .compatible = "nuvoton,npcm750-adc", .data = &npxm7xx_adc_info},
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{ .compatible = "nuvoton,npcm845-adc", .data = &npxm8xx_adc_info},
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{ /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, npcm_adc_match);
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static int npcm_adc_probe(struct platform_device *pdev)
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{
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int ret;
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int irq;
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u32 div;
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u32 reg_con;
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struct npcm_adc *info;
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struct iio_dev *indio_dev;
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struct device *dev = &pdev->dev;
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indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*info));
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if (!indio_dev)
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return -ENOMEM;
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info = iio_priv(indio_dev);
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info->data = device_get_match_data(dev);
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if (!info->data)
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return -EINVAL;
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mutex_init(&info->lock);
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info->dev = &pdev->dev;
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info->regs = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(info->regs))
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return PTR_ERR(info->regs);
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info->reset = devm_reset_control_get(&pdev->dev, NULL);
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if (IS_ERR(info->reset))
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return PTR_ERR(info->reset);
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info->adc_clk = devm_clk_get(&pdev->dev, NULL);
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if (IS_ERR(info->adc_clk)) {
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dev_warn(&pdev->dev, "ADC clock failed: can't read clk\n");
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return PTR_ERR(info->adc_clk);
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}
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/* calculate ADC clock sample rate */
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reg_con = ioread32(info->regs + NPCM_ADCCON);
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div = reg_con & NPCM_ADCCON_DIV_MASK;
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div = div >> NPCM_ADCCON_DIV_SHIFT;
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info->adc_sample_hz = clk_get_rate(info->adc_clk) / ((div + 1) * 2);
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irq = platform_get_irq(pdev, 0);
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if (irq <= 0) {
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ret = -EINVAL;
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goto err_disable_clk;
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}
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ret = devm_request_irq(&pdev->dev, irq, npcm_adc_isr, 0,
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"NPCM_ADC", indio_dev);
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if (ret < 0) {
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dev_err(dev, "failed requesting interrupt\n");
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goto err_disable_clk;
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}
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reg_con = ioread32(info->regs + NPCM_ADCCON);
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info->vref = devm_regulator_get_optional(&pdev->dev, "vref");
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if (!IS_ERR(info->vref)) {
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ret = regulator_enable(info->vref);
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if (ret) {
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dev_err(&pdev->dev, "Can't enable ADC reference voltage\n");
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goto err_disable_clk;
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}
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iowrite32(reg_con & ~NPCM_ADCCON_REFSEL,
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info->regs + NPCM_ADCCON);
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} else {
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/*
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* Any error which is not ENODEV indicates the regulator
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* has been specified and so is a failure case.
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*/
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if (PTR_ERR(info->vref) != -ENODEV) {
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ret = PTR_ERR(info->vref);
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goto err_disable_clk;
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}
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/* Use internal reference */
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iowrite32(reg_con | NPCM_ADCCON_REFSEL,
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info->regs + NPCM_ADCCON);
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}
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init_waitqueue_head(&info->wq);
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reg_con = ioread32(info->regs + NPCM_ADCCON);
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reg_con |= NPCM_ADC_ENABLE;
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/* Enable the ADC Module */
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iowrite32(reg_con, info->regs + NPCM_ADCCON);
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/* Start ADC conversion */
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iowrite32(reg_con | NPCM_ADCCON_ADC_CONV, info->regs + NPCM_ADCCON);
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platform_set_drvdata(pdev, indio_dev);
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indio_dev->name = dev_name(&pdev->dev);
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indio_dev->info = &npcm_adc_iio_info;
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indio_dev->modes = INDIO_DIRECT_MODE;
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indio_dev->channels = npcm_adc_iio_channels;
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indio_dev->num_channels = ARRAY_SIZE(npcm_adc_iio_channels);
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ret = iio_device_register(indio_dev);
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if (ret) {
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dev_err(&pdev->dev, "Couldn't register the device.\n");
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goto err_iio_register;
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}
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pr_info("NPCM ADC driver probed\n");
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return 0;
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err_iio_register:
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iowrite32(reg_con & ~NPCM_ADCCON_ADC_EN, info->regs + NPCM_ADCCON);
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if (!IS_ERR(info->vref))
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regulator_disable(info->vref);
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err_disable_clk:
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clk_disable_unprepare(info->adc_clk);
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return ret;
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}
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static int npcm_adc_remove(struct platform_device *pdev)
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{
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struct iio_dev *indio_dev = platform_get_drvdata(pdev);
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struct npcm_adc *info = iio_priv(indio_dev);
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u32 regtemp;
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iio_device_unregister(indio_dev);
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regtemp = ioread32(info->regs + NPCM_ADCCON);
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iowrite32(regtemp & ~NPCM_ADCCON_ADC_EN, info->regs + NPCM_ADCCON);
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if (!IS_ERR(info->vref))
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regulator_disable(info->vref);
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clk_disable_unprepare(info->adc_clk);
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return 0;
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}
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static struct platform_driver npcm_adc_driver = {
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.probe = npcm_adc_probe,
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.remove = npcm_adc_remove,
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.driver = {
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.name = "npcm_adc",
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.of_match_table = npcm_adc_match,
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},
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};
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module_platform_driver(npcm_adc_driver);
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MODULE_DESCRIPTION("Nuvoton NPCM ADC Driver");
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MODULE_AUTHOR("Tomer Maimon <tomer.maimon@nuvoton.com>");
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MODULE_LICENSE("GPL v2");
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