843 lines
23 KiB
C
843 lines
23 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Copyright (C) 2012-2014 Mentor Graphics Inc.
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* Copyright (C) 2005-2009 Freescale Semiconductor, Inc.
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*/
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#include <linux/export.h>
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#include <linux/module.h>
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#include <linux/types.h>
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#include <linux/errno.h>
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/err.h>
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#include <linux/platform_device.h>
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#include <linux/videodev2.h>
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#include <uapi/linux/v4l2-mediabus.h>
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/clkdev.h>
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#include "ipu-prv.h"
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struct ipu_csi {
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void __iomem *base;
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int id;
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u32 module;
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struct clk *clk_ipu; /* IPU bus clock */
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spinlock_t lock;
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bool inuse;
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struct ipu_soc *ipu;
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};
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/* CSI Register Offsets */
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#define CSI_SENS_CONF 0x0000
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#define CSI_SENS_FRM_SIZE 0x0004
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#define CSI_ACT_FRM_SIZE 0x0008
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#define CSI_OUT_FRM_CTRL 0x000c
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#define CSI_TST_CTRL 0x0010
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#define CSI_CCIR_CODE_1 0x0014
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#define CSI_CCIR_CODE_2 0x0018
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#define CSI_CCIR_CODE_3 0x001c
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#define CSI_MIPI_DI 0x0020
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#define CSI_SKIP 0x0024
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#define CSI_CPD_CTRL 0x0028
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#define CSI_CPD_RC(n) (0x002c + ((n)*4))
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#define CSI_CPD_RS(n) (0x004c + ((n)*4))
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#define CSI_CPD_GRC(n) (0x005c + ((n)*4))
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#define CSI_CPD_GRS(n) (0x007c + ((n)*4))
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#define CSI_CPD_GBC(n) (0x008c + ((n)*4))
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#define CSI_CPD_GBS(n) (0x00Ac + ((n)*4))
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#define CSI_CPD_BC(n) (0x00Bc + ((n)*4))
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#define CSI_CPD_BS(n) (0x00Dc + ((n)*4))
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#define CSI_CPD_OFFSET1 0x00ec
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#define CSI_CPD_OFFSET2 0x00f0
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/* CSI Register Fields */
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#define CSI_SENS_CONF_DATA_FMT_SHIFT 8
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#define CSI_SENS_CONF_DATA_FMT_MASK 0x00000700
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#define CSI_SENS_CONF_DATA_FMT_RGB_YUV444 0L
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#define CSI_SENS_CONF_DATA_FMT_YUV422_YUYV 1L
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#define CSI_SENS_CONF_DATA_FMT_YUV422_UYVY 2L
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#define CSI_SENS_CONF_DATA_FMT_BAYER 3L
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#define CSI_SENS_CONF_DATA_FMT_RGB565 4L
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#define CSI_SENS_CONF_DATA_FMT_RGB555 5L
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#define CSI_SENS_CONF_DATA_FMT_RGB444 6L
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#define CSI_SENS_CONF_DATA_FMT_JPEG 7L
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#define CSI_SENS_CONF_VSYNC_POL_SHIFT 0
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#define CSI_SENS_CONF_HSYNC_POL_SHIFT 1
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#define CSI_SENS_CONF_DATA_POL_SHIFT 2
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#define CSI_SENS_CONF_PIX_CLK_POL_SHIFT 3
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#define CSI_SENS_CONF_SENS_PRTCL_MASK 0x00000070
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#define CSI_SENS_CONF_SENS_PRTCL_SHIFT 4
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#define CSI_SENS_CONF_PACK_TIGHT_SHIFT 7
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#define CSI_SENS_CONF_DATA_WIDTH_SHIFT 11
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#define CSI_SENS_CONF_EXT_VSYNC_SHIFT 15
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#define CSI_SENS_CONF_DIVRATIO_SHIFT 16
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#define CSI_SENS_CONF_DIVRATIO_MASK 0x00ff0000
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#define CSI_SENS_CONF_DATA_DEST_SHIFT 24
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#define CSI_SENS_CONF_DATA_DEST_MASK 0x07000000
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#define CSI_SENS_CONF_JPEG8_EN_SHIFT 27
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#define CSI_SENS_CONF_JPEG_EN_SHIFT 28
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#define CSI_SENS_CONF_FORCE_EOF_SHIFT 29
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#define CSI_SENS_CONF_DATA_EN_POL_SHIFT 31
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#define CSI_DATA_DEST_IC 2
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#define CSI_DATA_DEST_IDMAC 4
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#define CSI_CCIR_ERR_DET_EN 0x01000000
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#define CSI_HORI_DOWNSIZE_EN 0x80000000
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#define CSI_VERT_DOWNSIZE_EN 0x40000000
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#define CSI_TEST_GEN_MODE_EN 0x01000000
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#define CSI_HSC_MASK 0x1fff0000
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#define CSI_HSC_SHIFT 16
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#define CSI_VSC_MASK 0x00000fff
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#define CSI_VSC_SHIFT 0
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#define CSI_TEST_GEN_R_MASK 0x000000ff
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#define CSI_TEST_GEN_R_SHIFT 0
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#define CSI_TEST_GEN_G_MASK 0x0000ff00
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#define CSI_TEST_GEN_G_SHIFT 8
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#define CSI_TEST_GEN_B_MASK 0x00ff0000
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#define CSI_TEST_GEN_B_SHIFT 16
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#define CSI_MAX_RATIO_SKIP_SMFC_MASK 0x00000007
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#define CSI_MAX_RATIO_SKIP_SMFC_SHIFT 0
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#define CSI_SKIP_SMFC_MASK 0x000000f8
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#define CSI_SKIP_SMFC_SHIFT 3
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#define CSI_ID_2_SKIP_MASK 0x00000300
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#define CSI_ID_2_SKIP_SHIFT 8
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#define CSI_COLOR_FIRST_ROW_MASK 0x00000002
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#define CSI_COLOR_FIRST_COMP_MASK 0x00000001
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/* MIPI CSI-2 data types */
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#define MIPI_DT_YUV420 0x18 /* YYY.../UYVY.... */
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#define MIPI_DT_YUV420_LEGACY 0x1a /* UYY.../VYY... */
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#define MIPI_DT_YUV422 0x1e /* UYVY... */
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#define MIPI_DT_RGB444 0x20
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#define MIPI_DT_RGB555 0x21
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#define MIPI_DT_RGB565 0x22
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#define MIPI_DT_RGB666 0x23
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#define MIPI_DT_RGB888 0x24
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#define MIPI_DT_RAW6 0x28
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#define MIPI_DT_RAW7 0x29
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#define MIPI_DT_RAW8 0x2a
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#define MIPI_DT_RAW10 0x2b
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#define MIPI_DT_RAW12 0x2c
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#define MIPI_DT_RAW14 0x2d
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/*
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* Bitfield of CSI bus signal polarities and modes.
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*/
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struct ipu_csi_bus_config {
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unsigned data_width:4;
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unsigned clk_mode:3;
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unsigned ext_vsync:1;
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unsigned vsync_pol:1;
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unsigned hsync_pol:1;
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unsigned pixclk_pol:1;
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unsigned data_pol:1;
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unsigned sens_clksrc:1;
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unsigned pack_tight:1;
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unsigned force_eof:1;
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unsigned data_en_pol:1;
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unsigned data_fmt;
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unsigned mipi_dt;
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};
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/*
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* Enumeration of CSI data bus widths.
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*/
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enum ipu_csi_data_width {
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IPU_CSI_DATA_WIDTH_4 = 0,
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IPU_CSI_DATA_WIDTH_8 = 1,
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IPU_CSI_DATA_WIDTH_10 = 3,
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IPU_CSI_DATA_WIDTH_12 = 5,
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IPU_CSI_DATA_WIDTH_16 = 9,
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};
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/*
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* Enumeration of CSI clock modes.
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*/
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enum ipu_csi_clk_mode {
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IPU_CSI_CLK_MODE_GATED_CLK,
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IPU_CSI_CLK_MODE_NONGATED_CLK,
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IPU_CSI_CLK_MODE_CCIR656_PROGRESSIVE,
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IPU_CSI_CLK_MODE_CCIR656_INTERLACED,
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IPU_CSI_CLK_MODE_CCIR1120_PROGRESSIVE_DDR,
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IPU_CSI_CLK_MODE_CCIR1120_PROGRESSIVE_SDR,
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IPU_CSI_CLK_MODE_CCIR1120_INTERLACED_DDR,
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IPU_CSI_CLK_MODE_CCIR1120_INTERLACED_SDR,
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};
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static inline u32 ipu_csi_read(struct ipu_csi *csi, unsigned offset)
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{
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return readl(csi->base + offset);
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}
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static inline void ipu_csi_write(struct ipu_csi *csi, u32 value,
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unsigned offset)
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{
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writel(value, csi->base + offset);
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}
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/*
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* Set mclk division ratio for generating test mode mclk. Only used
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* for test generator.
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*/
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static int ipu_csi_set_testgen_mclk(struct ipu_csi *csi, u32 pixel_clk,
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u32 ipu_clk)
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{
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u32 temp;
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int div_ratio;
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div_ratio = (ipu_clk / pixel_clk) - 1;
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if (div_ratio > 0xFF || div_ratio < 0) {
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dev_err(csi->ipu->dev,
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"value of pixel_clk extends normal range\n");
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return -EINVAL;
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}
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temp = ipu_csi_read(csi, CSI_SENS_CONF);
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temp &= ~CSI_SENS_CONF_DIVRATIO_MASK;
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ipu_csi_write(csi, temp | (div_ratio << CSI_SENS_CONF_DIVRATIO_SHIFT),
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CSI_SENS_CONF);
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return 0;
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}
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/*
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* Find the CSI data format and data width for the given V4L2 media
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* bus pixel format code.
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*/
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static int mbus_code_to_bus_cfg(struct ipu_csi_bus_config *cfg, u32 mbus_code,
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enum v4l2_mbus_type mbus_type)
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{
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switch (mbus_code) {
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case MEDIA_BUS_FMT_BGR565_2X8_BE:
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case MEDIA_BUS_FMT_BGR565_2X8_LE:
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case MEDIA_BUS_FMT_RGB565_2X8_BE:
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case MEDIA_BUS_FMT_RGB565_2X8_LE:
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if (mbus_type == V4L2_MBUS_CSI2_DPHY)
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cfg->data_fmt = CSI_SENS_CONF_DATA_FMT_RGB565;
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else
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cfg->data_fmt = CSI_SENS_CONF_DATA_FMT_BAYER;
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cfg->mipi_dt = MIPI_DT_RGB565;
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cfg->data_width = IPU_CSI_DATA_WIDTH_8;
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break;
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case MEDIA_BUS_FMT_RGB444_2X8_PADHI_BE:
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case MEDIA_BUS_FMT_RGB444_2X8_PADHI_LE:
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cfg->data_fmt = CSI_SENS_CONF_DATA_FMT_RGB444;
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cfg->mipi_dt = MIPI_DT_RGB444;
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cfg->data_width = IPU_CSI_DATA_WIDTH_8;
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break;
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case MEDIA_BUS_FMT_RGB555_2X8_PADHI_BE:
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case MEDIA_BUS_FMT_RGB555_2X8_PADHI_LE:
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cfg->data_fmt = CSI_SENS_CONF_DATA_FMT_RGB555;
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cfg->mipi_dt = MIPI_DT_RGB555;
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cfg->data_width = IPU_CSI_DATA_WIDTH_8;
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break;
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case MEDIA_BUS_FMT_RGB888_1X24:
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case MEDIA_BUS_FMT_BGR888_1X24:
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cfg->data_fmt = CSI_SENS_CONF_DATA_FMT_RGB_YUV444;
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cfg->mipi_dt = MIPI_DT_RGB888;
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cfg->data_width = IPU_CSI_DATA_WIDTH_8;
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break;
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case MEDIA_BUS_FMT_UYVY8_2X8:
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cfg->data_fmt = CSI_SENS_CONF_DATA_FMT_YUV422_UYVY;
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cfg->mipi_dt = MIPI_DT_YUV422;
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cfg->data_width = IPU_CSI_DATA_WIDTH_8;
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break;
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case MEDIA_BUS_FMT_YUYV8_2X8:
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cfg->data_fmt = CSI_SENS_CONF_DATA_FMT_YUV422_YUYV;
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cfg->mipi_dt = MIPI_DT_YUV422;
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cfg->data_width = IPU_CSI_DATA_WIDTH_8;
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break;
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case MEDIA_BUS_FMT_UYVY8_1X16:
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if (mbus_type == V4L2_MBUS_BT656) {
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cfg->data_fmt = CSI_SENS_CONF_DATA_FMT_YUV422_UYVY;
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cfg->data_width = IPU_CSI_DATA_WIDTH_8;
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} else {
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cfg->data_fmt = CSI_SENS_CONF_DATA_FMT_BAYER;
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cfg->data_width = IPU_CSI_DATA_WIDTH_16;
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}
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cfg->mipi_dt = MIPI_DT_YUV422;
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break;
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case MEDIA_BUS_FMT_YUYV8_1X16:
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if (mbus_type == V4L2_MBUS_BT656) {
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cfg->data_fmt = CSI_SENS_CONF_DATA_FMT_YUV422_YUYV;
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cfg->data_width = IPU_CSI_DATA_WIDTH_8;
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} else {
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cfg->data_fmt = CSI_SENS_CONF_DATA_FMT_BAYER;
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cfg->data_width = IPU_CSI_DATA_WIDTH_16;
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}
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cfg->mipi_dt = MIPI_DT_YUV422;
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break;
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case MEDIA_BUS_FMT_SBGGR8_1X8:
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case MEDIA_BUS_FMT_SGBRG8_1X8:
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case MEDIA_BUS_FMT_SGRBG8_1X8:
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case MEDIA_BUS_FMT_SRGGB8_1X8:
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case MEDIA_BUS_FMT_Y8_1X8:
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cfg->data_fmt = CSI_SENS_CONF_DATA_FMT_BAYER;
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cfg->mipi_dt = MIPI_DT_RAW8;
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cfg->data_width = IPU_CSI_DATA_WIDTH_8;
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break;
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case MEDIA_BUS_FMT_SBGGR10_DPCM8_1X8:
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case MEDIA_BUS_FMT_SGBRG10_DPCM8_1X8:
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case MEDIA_BUS_FMT_SGRBG10_DPCM8_1X8:
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case MEDIA_BUS_FMT_SRGGB10_DPCM8_1X8:
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case MEDIA_BUS_FMT_SBGGR10_2X8_PADHI_BE:
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case MEDIA_BUS_FMT_SBGGR10_2X8_PADHI_LE:
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case MEDIA_BUS_FMT_SBGGR10_2X8_PADLO_BE:
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case MEDIA_BUS_FMT_SBGGR10_2X8_PADLO_LE:
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cfg->data_fmt = CSI_SENS_CONF_DATA_FMT_BAYER;
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cfg->mipi_dt = MIPI_DT_RAW10;
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cfg->data_width = IPU_CSI_DATA_WIDTH_8;
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break;
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case MEDIA_BUS_FMT_SBGGR10_1X10:
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case MEDIA_BUS_FMT_SGBRG10_1X10:
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case MEDIA_BUS_FMT_SGRBG10_1X10:
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case MEDIA_BUS_FMT_SRGGB10_1X10:
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case MEDIA_BUS_FMT_Y10_1X10:
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cfg->data_fmt = CSI_SENS_CONF_DATA_FMT_BAYER;
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cfg->mipi_dt = MIPI_DT_RAW10;
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cfg->data_width = IPU_CSI_DATA_WIDTH_10;
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break;
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case MEDIA_BUS_FMT_SBGGR12_1X12:
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case MEDIA_BUS_FMT_SGBRG12_1X12:
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case MEDIA_BUS_FMT_SGRBG12_1X12:
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case MEDIA_BUS_FMT_SRGGB12_1X12:
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case MEDIA_BUS_FMT_Y12_1X12:
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cfg->data_fmt = CSI_SENS_CONF_DATA_FMT_BAYER;
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cfg->mipi_dt = MIPI_DT_RAW12;
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cfg->data_width = IPU_CSI_DATA_WIDTH_12;
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break;
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case MEDIA_BUS_FMT_JPEG_1X8:
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/* TODO */
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cfg->data_fmt = CSI_SENS_CONF_DATA_FMT_JPEG;
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cfg->mipi_dt = MIPI_DT_RAW8;
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cfg->data_width = IPU_CSI_DATA_WIDTH_8;
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break;
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default:
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return -EINVAL;
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}
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return 0;
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}
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/* translate alternate field mode based on given standard */
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static inline enum v4l2_field
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ipu_csi_translate_field(enum v4l2_field field, v4l2_std_id std)
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{
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return (field != V4L2_FIELD_ALTERNATE) ? field :
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((std & V4L2_STD_525_60) ?
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V4L2_FIELD_SEQ_BT : V4L2_FIELD_SEQ_TB);
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}
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/*
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* Fill a CSI bus config struct from mbus_config and mbus_framefmt.
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*/
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static int fill_csi_bus_cfg(struct ipu_csi_bus_config *csicfg,
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const struct v4l2_mbus_config *mbus_cfg,
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const struct v4l2_mbus_framefmt *mbus_fmt)
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{
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int ret, is_bt1120;
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memset(csicfg, 0, sizeof(*csicfg));
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ret = mbus_code_to_bus_cfg(csicfg, mbus_fmt->code, mbus_cfg->type);
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if (ret < 0)
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return ret;
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switch (mbus_cfg->type) {
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case V4L2_MBUS_PARALLEL:
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csicfg->ext_vsync = 1;
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csicfg->vsync_pol = (mbus_cfg->bus.parallel.flags &
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V4L2_MBUS_VSYNC_ACTIVE_LOW) ? 1 : 0;
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csicfg->hsync_pol = (mbus_cfg->bus.parallel.flags &
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V4L2_MBUS_HSYNC_ACTIVE_LOW) ? 1 : 0;
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csicfg->pixclk_pol = (mbus_cfg->bus.parallel.flags &
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V4L2_MBUS_PCLK_SAMPLE_FALLING) ? 1 : 0;
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csicfg->clk_mode = IPU_CSI_CLK_MODE_GATED_CLK;
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break;
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case V4L2_MBUS_BT656:
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csicfg->ext_vsync = 0;
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/* UYVY10_1X20 etc. should be supported as well */
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is_bt1120 = mbus_fmt->code == MEDIA_BUS_FMT_UYVY8_1X16 ||
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mbus_fmt->code == MEDIA_BUS_FMT_YUYV8_1X16;
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if (V4L2_FIELD_HAS_BOTH(mbus_fmt->field) ||
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mbus_fmt->field == V4L2_FIELD_ALTERNATE)
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csicfg->clk_mode = is_bt1120 ?
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IPU_CSI_CLK_MODE_CCIR1120_INTERLACED_SDR :
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IPU_CSI_CLK_MODE_CCIR656_INTERLACED;
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else
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csicfg->clk_mode = is_bt1120 ?
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IPU_CSI_CLK_MODE_CCIR1120_PROGRESSIVE_SDR :
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IPU_CSI_CLK_MODE_CCIR656_PROGRESSIVE;
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break;
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case V4L2_MBUS_CSI2_DPHY:
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/*
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* MIPI CSI-2 requires non gated clock mode, all other
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* parameters are not applicable for MIPI CSI-2 bus.
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*/
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csicfg->clk_mode = IPU_CSI_CLK_MODE_NONGATED_CLK;
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break;
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default:
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/* will never get here, keep compiler quiet */
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break;
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}
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return 0;
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}
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static int
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ipu_csi_set_bt_interlaced_codes(struct ipu_csi *csi,
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const struct v4l2_mbus_framefmt *infmt,
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|
const struct v4l2_mbus_framefmt *outfmt,
|
|
v4l2_std_id std)
|
|
{
|
|
enum v4l2_field infield, outfield;
|
|
bool swap_fields;
|
|
|
|
/* get translated field type of input and output */
|
|
infield = ipu_csi_translate_field(infmt->field, std);
|
|
outfield = ipu_csi_translate_field(outfmt->field, std);
|
|
|
|
/*
|
|
* Write the H-V-F codes the CSI will match against the
|
|
* incoming data for start/end of active and blanking
|
|
* field intervals. If input and output field types are
|
|
* sequential but not the same (one is SEQ_BT and the other
|
|
* is SEQ_TB), swap the F-bit so that the CSI will capture
|
|
* field 1 lines before field 0 lines.
|
|
*/
|
|
swap_fields = (V4L2_FIELD_IS_SEQUENTIAL(infield) &&
|
|
V4L2_FIELD_IS_SEQUENTIAL(outfield) &&
|
|
infield != outfield);
|
|
|
|
if (!swap_fields) {
|
|
/*
|
|
* Field0BlankEnd = 110, Field0BlankStart = 010
|
|
* Field0ActiveEnd = 100, Field0ActiveStart = 000
|
|
* Field1BlankEnd = 111, Field1BlankStart = 011
|
|
* Field1ActiveEnd = 101, Field1ActiveStart = 001
|
|
*/
|
|
ipu_csi_write(csi, 0x40596 | CSI_CCIR_ERR_DET_EN,
|
|
CSI_CCIR_CODE_1);
|
|
ipu_csi_write(csi, 0xD07DF, CSI_CCIR_CODE_2);
|
|
} else {
|
|
dev_dbg(csi->ipu->dev, "capture field swap\n");
|
|
|
|
/* same as above but with F-bit inverted */
|
|
ipu_csi_write(csi, 0xD07DF | CSI_CCIR_ERR_DET_EN,
|
|
CSI_CCIR_CODE_1);
|
|
ipu_csi_write(csi, 0x40596, CSI_CCIR_CODE_2);
|
|
}
|
|
|
|
ipu_csi_write(csi, 0xFF0000, CSI_CCIR_CODE_3);
|
|
|
|
return 0;
|
|
}
|
|
|
|
|
|
int ipu_csi_init_interface(struct ipu_csi *csi,
|
|
const struct v4l2_mbus_config *mbus_cfg,
|
|
const struct v4l2_mbus_framefmt *infmt,
|
|
const struct v4l2_mbus_framefmt *outfmt)
|
|
{
|
|
struct ipu_csi_bus_config cfg;
|
|
unsigned long flags;
|
|
u32 width, height, data = 0;
|
|
v4l2_std_id std;
|
|
int ret;
|
|
|
|
ret = fill_csi_bus_cfg(&cfg, mbus_cfg, infmt);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
/* set default sensor frame width and height */
|
|
width = infmt->width;
|
|
height = infmt->height;
|
|
if (infmt->field == V4L2_FIELD_ALTERNATE)
|
|
height *= 2;
|
|
|
|
/* Set the CSI_SENS_CONF register remaining fields */
|
|
data |= cfg.data_width << CSI_SENS_CONF_DATA_WIDTH_SHIFT |
|
|
cfg.data_fmt << CSI_SENS_CONF_DATA_FMT_SHIFT |
|
|
cfg.data_pol << CSI_SENS_CONF_DATA_POL_SHIFT |
|
|
cfg.vsync_pol << CSI_SENS_CONF_VSYNC_POL_SHIFT |
|
|
cfg.hsync_pol << CSI_SENS_CONF_HSYNC_POL_SHIFT |
|
|
cfg.pixclk_pol << CSI_SENS_CONF_PIX_CLK_POL_SHIFT |
|
|
cfg.ext_vsync << CSI_SENS_CONF_EXT_VSYNC_SHIFT |
|
|
cfg.clk_mode << CSI_SENS_CONF_SENS_PRTCL_SHIFT |
|
|
cfg.pack_tight << CSI_SENS_CONF_PACK_TIGHT_SHIFT |
|
|
cfg.force_eof << CSI_SENS_CONF_FORCE_EOF_SHIFT |
|
|
cfg.data_en_pol << CSI_SENS_CONF_DATA_EN_POL_SHIFT;
|
|
|
|
spin_lock_irqsave(&csi->lock, flags);
|
|
|
|
ipu_csi_write(csi, data, CSI_SENS_CONF);
|
|
|
|
/* Set CCIR registers */
|
|
|
|
switch (cfg.clk_mode) {
|
|
case IPU_CSI_CLK_MODE_CCIR656_PROGRESSIVE:
|
|
ipu_csi_write(csi, 0x40030, CSI_CCIR_CODE_1);
|
|
ipu_csi_write(csi, 0xFF0000, CSI_CCIR_CODE_3);
|
|
break;
|
|
case IPU_CSI_CLK_MODE_CCIR656_INTERLACED:
|
|
if (width == 720 && height == 480) {
|
|
std = V4L2_STD_NTSC;
|
|
height = 525;
|
|
} else if (width == 720 && height == 576) {
|
|
std = V4L2_STD_PAL;
|
|
height = 625;
|
|
} else {
|
|
dev_err(csi->ipu->dev,
|
|
"Unsupported interlaced video mode\n");
|
|
ret = -EINVAL;
|
|
goto out_unlock;
|
|
}
|
|
|
|
ret = ipu_csi_set_bt_interlaced_codes(csi, infmt, outfmt, std);
|
|
if (ret)
|
|
goto out_unlock;
|
|
break;
|
|
case IPU_CSI_CLK_MODE_CCIR1120_PROGRESSIVE_DDR:
|
|
case IPU_CSI_CLK_MODE_CCIR1120_PROGRESSIVE_SDR:
|
|
case IPU_CSI_CLK_MODE_CCIR1120_INTERLACED_DDR:
|
|
case IPU_CSI_CLK_MODE_CCIR1120_INTERLACED_SDR:
|
|
ipu_csi_write(csi, 0x40030 | CSI_CCIR_ERR_DET_EN,
|
|
CSI_CCIR_CODE_1);
|
|
ipu_csi_write(csi, 0xFF0000, CSI_CCIR_CODE_3);
|
|
break;
|
|
case IPU_CSI_CLK_MODE_GATED_CLK:
|
|
case IPU_CSI_CLK_MODE_NONGATED_CLK:
|
|
ipu_csi_write(csi, 0, CSI_CCIR_CODE_1);
|
|
break;
|
|
}
|
|
|
|
/* Setup sensor frame size */
|
|
ipu_csi_write(csi, (width - 1) | ((height - 1) << 16),
|
|
CSI_SENS_FRM_SIZE);
|
|
|
|
dev_dbg(csi->ipu->dev, "CSI_SENS_CONF = 0x%08X\n",
|
|
ipu_csi_read(csi, CSI_SENS_CONF));
|
|
dev_dbg(csi->ipu->dev, "CSI_ACT_FRM_SIZE = 0x%08X\n",
|
|
ipu_csi_read(csi, CSI_ACT_FRM_SIZE));
|
|
|
|
out_unlock:
|
|
spin_unlock_irqrestore(&csi->lock, flags);
|
|
|
|
return ret;
|
|
}
|
|
EXPORT_SYMBOL_GPL(ipu_csi_init_interface);
|
|
|
|
bool ipu_csi_is_interlaced(struct ipu_csi *csi)
|
|
{
|
|
unsigned long flags;
|
|
u32 sensor_protocol;
|
|
|
|
spin_lock_irqsave(&csi->lock, flags);
|
|
sensor_protocol =
|
|
(ipu_csi_read(csi, CSI_SENS_CONF) &
|
|
CSI_SENS_CONF_SENS_PRTCL_MASK) >>
|
|
CSI_SENS_CONF_SENS_PRTCL_SHIFT;
|
|
spin_unlock_irqrestore(&csi->lock, flags);
|
|
|
|
switch (sensor_protocol) {
|
|
case IPU_CSI_CLK_MODE_GATED_CLK:
|
|
case IPU_CSI_CLK_MODE_NONGATED_CLK:
|
|
case IPU_CSI_CLK_MODE_CCIR656_PROGRESSIVE:
|
|
case IPU_CSI_CLK_MODE_CCIR1120_PROGRESSIVE_DDR:
|
|
case IPU_CSI_CLK_MODE_CCIR1120_PROGRESSIVE_SDR:
|
|
return false;
|
|
case IPU_CSI_CLK_MODE_CCIR656_INTERLACED:
|
|
case IPU_CSI_CLK_MODE_CCIR1120_INTERLACED_DDR:
|
|
case IPU_CSI_CLK_MODE_CCIR1120_INTERLACED_SDR:
|
|
return true;
|
|
default:
|
|
dev_err(csi->ipu->dev,
|
|
"CSI %d sensor protocol unsupported\n", csi->id);
|
|
return false;
|
|
}
|
|
}
|
|
EXPORT_SYMBOL_GPL(ipu_csi_is_interlaced);
|
|
|
|
void ipu_csi_get_window(struct ipu_csi *csi, struct v4l2_rect *w)
|
|
{
|
|
unsigned long flags;
|
|
u32 reg;
|
|
|
|
spin_lock_irqsave(&csi->lock, flags);
|
|
|
|
reg = ipu_csi_read(csi, CSI_ACT_FRM_SIZE);
|
|
w->width = (reg & 0xFFFF) + 1;
|
|
w->height = (reg >> 16 & 0xFFFF) + 1;
|
|
|
|
reg = ipu_csi_read(csi, CSI_OUT_FRM_CTRL);
|
|
w->left = (reg & CSI_HSC_MASK) >> CSI_HSC_SHIFT;
|
|
w->top = (reg & CSI_VSC_MASK) >> CSI_VSC_SHIFT;
|
|
|
|
spin_unlock_irqrestore(&csi->lock, flags);
|
|
}
|
|
EXPORT_SYMBOL_GPL(ipu_csi_get_window);
|
|
|
|
void ipu_csi_set_window(struct ipu_csi *csi, struct v4l2_rect *w)
|
|
{
|
|
unsigned long flags;
|
|
u32 reg;
|
|
|
|
spin_lock_irqsave(&csi->lock, flags);
|
|
|
|
ipu_csi_write(csi, (w->width - 1) | ((w->height - 1) << 16),
|
|
CSI_ACT_FRM_SIZE);
|
|
|
|
reg = ipu_csi_read(csi, CSI_OUT_FRM_CTRL);
|
|
reg &= ~(CSI_HSC_MASK | CSI_VSC_MASK);
|
|
reg |= ((w->top << CSI_VSC_SHIFT) | (w->left << CSI_HSC_SHIFT));
|
|
ipu_csi_write(csi, reg, CSI_OUT_FRM_CTRL);
|
|
|
|
spin_unlock_irqrestore(&csi->lock, flags);
|
|
}
|
|
EXPORT_SYMBOL_GPL(ipu_csi_set_window);
|
|
|
|
void ipu_csi_set_downsize(struct ipu_csi *csi, bool horiz, bool vert)
|
|
{
|
|
unsigned long flags;
|
|
u32 reg;
|
|
|
|
spin_lock_irqsave(&csi->lock, flags);
|
|
|
|
reg = ipu_csi_read(csi, CSI_OUT_FRM_CTRL);
|
|
reg &= ~(CSI_HORI_DOWNSIZE_EN | CSI_VERT_DOWNSIZE_EN);
|
|
reg |= (horiz ? CSI_HORI_DOWNSIZE_EN : 0) |
|
|
(vert ? CSI_VERT_DOWNSIZE_EN : 0);
|
|
ipu_csi_write(csi, reg, CSI_OUT_FRM_CTRL);
|
|
|
|
spin_unlock_irqrestore(&csi->lock, flags);
|
|
}
|
|
EXPORT_SYMBOL_GPL(ipu_csi_set_downsize);
|
|
|
|
void ipu_csi_set_test_generator(struct ipu_csi *csi, bool active,
|
|
u32 r_value, u32 g_value, u32 b_value,
|
|
u32 pix_clk)
|
|
{
|
|
unsigned long flags;
|
|
u32 ipu_clk = clk_get_rate(csi->clk_ipu);
|
|
u32 temp;
|
|
|
|
spin_lock_irqsave(&csi->lock, flags);
|
|
|
|
temp = ipu_csi_read(csi, CSI_TST_CTRL);
|
|
|
|
if (!active) {
|
|
temp &= ~CSI_TEST_GEN_MODE_EN;
|
|
ipu_csi_write(csi, temp, CSI_TST_CTRL);
|
|
} else {
|
|
/* Set sensb_mclk div_ratio */
|
|
ipu_csi_set_testgen_mclk(csi, pix_clk, ipu_clk);
|
|
|
|
temp &= ~(CSI_TEST_GEN_R_MASK | CSI_TEST_GEN_G_MASK |
|
|
CSI_TEST_GEN_B_MASK);
|
|
temp |= CSI_TEST_GEN_MODE_EN;
|
|
temp |= (r_value << CSI_TEST_GEN_R_SHIFT) |
|
|
(g_value << CSI_TEST_GEN_G_SHIFT) |
|
|
(b_value << CSI_TEST_GEN_B_SHIFT);
|
|
ipu_csi_write(csi, temp, CSI_TST_CTRL);
|
|
}
|
|
|
|
spin_unlock_irqrestore(&csi->lock, flags);
|
|
}
|
|
EXPORT_SYMBOL_GPL(ipu_csi_set_test_generator);
|
|
|
|
int ipu_csi_set_mipi_datatype(struct ipu_csi *csi, u32 vc,
|
|
struct v4l2_mbus_framefmt *mbus_fmt)
|
|
{
|
|
struct ipu_csi_bus_config cfg;
|
|
unsigned long flags;
|
|
u32 temp;
|
|
int ret;
|
|
|
|
if (vc > 3)
|
|
return -EINVAL;
|
|
|
|
ret = mbus_code_to_bus_cfg(&cfg, mbus_fmt->code, V4L2_MBUS_CSI2_DPHY);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
spin_lock_irqsave(&csi->lock, flags);
|
|
|
|
temp = ipu_csi_read(csi, CSI_MIPI_DI);
|
|
temp &= ~(0xff << (vc * 8));
|
|
temp |= (cfg.mipi_dt << (vc * 8));
|
|
ipu_csi_write(csi, temp, CSI_MIPI_DI);
|
|
|
|
spin_unlock_irqrestore(&csi->lock, flags);
|
|
|
|
return 0;
|
|
}
|
|
EXPORT_SYMBOL_GPL(ipu_csi_set_mipi_datatype);
|
|
|
|
int ipu_csi_set_skip_smfc(struct ipu_csi *csi, u32 skip,
|
|
u32 max_ratio, u32 id)
|
|
{
|
|
unsigned long flags;
|
|
u32 temp;
|
|
|
|
if (max_ratio > 5 || id > 3)
|
|
return -EINVAL;
|
|
|
|
spin_lock_irqsave(&csi->lock, flags);
|
|
|
|
temp = ipu_csi_read(csi, CSI_SKIP);
|
|
temp &= ~(CSI_MAX_RATIO_SKIP_SMFC_MASK | CSI_ID_2_SKIP_MASK |
|
|
CSI_SKIP_SMFC_MASK);
|
|
temp |= (max_ratio << CSI_MAX_RATIO_SKIP_SMFC_SHIFT) |
|
|
(id << CSI_ID_2_SKIP_SHIFT) |
|
|
(skip << CSI_SKIP_SMFC_SHIFT);
|
|
ipu_csi_write(csi, temp, CSI_SKIP);
|
|
|
|
spin_unlock_irqrestore(&csi->lock, flags);
|
|
|
|
return 0;
|
|
}
|
|
EXPORT_SYMBOL_GPL(ipu_csi_set_skip_smfc);
|
|
|
|
int ipu_csi_set_dest(struct ipu_csi *csi, enum ipu_csi_dest csi_dest)
|
|
{
|
|
unsigned long flags;
|
|
u32 csi_sens_conf, dest;
|
|
|
|
if (csi_dest == IPU_CSI_DEST_IDMAC)
|
|
dest = CSI_DATA_DEST_IDMAC;
|
|
else
|
|
dest = CSI_DATA_DEST_IC; /* IC or VDIC */
|
|
|
|
spin_lock_irqsave(&csi->lock, flags);
|
|
|
|
csi_sens_conf = ipu_csi_read(csi, CSI_SENS_CONF);
|
|
csi_sens_conf &= ~CSI_SENS_CONF_DATA_DEST_MASK;
|
|
csi_sens_conf |= (dest << CSI_SENS_CONF_DATA_DEST_SHIFT);
|
|
ipu_csi_write(csi, csi_sens_conf, CSI_SENS_CONF);
|
|
|
|
spin_unlock_irqrestore(&csi->lock, flags);
|
|
|
|
return 0;
|
|
}
|
|
EXPORT_SYMBOL_GPL(ipu_csi_set_dest);
|
|
|
|
int ipu_csi_enable(struct ipu_csi *csi)
|
|
{
|
|
ipu_module_enable(csi->ipu, csi->module);
|
|
|
|
return 0;
|
|
}
|
|
EXPORT_SYMBOL_GPL(ipu_csi_enable);
|
|
|
|
int ipu_csi_disable(struct ipu_csi *csi)
|
|
{
|
|
ipu_module_disable(csi->ipu, csi->module);
|
|
|
|
return 0;
|
|
}
|
|
EXPORT_SYMBOL_GPL(ipu_csi_disable);
|
|
|
|
struct ipu_csi *ipu_csi_get(struct ipu_soc *ipu, int id)
|
|
{
|
|
unsigned long flags;
|
|
struct ipu_csi *csi, *ret;
|
|
|
|
if (id > 1)
|
|
return ERR_PTR(-EINVAL);
|
|
|
|
csi = ipu->csi_priv[id];
|
|
ret = csi;
|
|
|
|
spin_lock_irqsave(&csi->lock, flags);
|
|
|
|
if (csi->inuse) {
|
|
ret = ERR_PTR(-EBUSY);
|
|
goto unlock;
|
|
}
|
|
|
|
csi->inuse = true;
|
|
unlock:
|
|
spin_unlock_irqrestore(&csi->lock, flags);
|
|
return ret;
|
|
}
|
|
EXPORT_SYMBOL_GPL(ipu_csi_get);
|
|
|
|
void ipu_csi_put(struct ipu_csi *csi)
|
|
{
|
|
unsigned long flags;
|
|
|
|
spin_lock_irqsave(&csi->lock, flags);
|
|
csi->inuse = false;
|
|
spin_unlock_irqrestore(&csi->lock, flags);
|
|
}
|
|
EXPORT_SYMBOL_GPL(ipu_csi_put);
|
|
|
|
int ipu_csi_init(struct ipu_soc *ipu, struct device *dev, int id,
|
|
unsigned long base, u32 module, struct clk *clk_ipu)
|
|
{
|
|
struct ipu_csi *csi;
|
|
|
|
if (id > 1)
|
|
return -ENODEV;
|
|
|
|
csi = devm_kzalloc(dev, sizeof(*csi), GFP_KERNEL);
|
|
if (!csi)
|
|
return -ENOMEM;
|
|
|
|
ipu->csi_priv[id] = csi;
|
|
|
|
spin_lock_init(&csi->lock);
|
|
csi->module = module;
|
|
csi->id = id;
|
|
csi->clk_ipu = clk_ipu;
|
|
csi->base = devm_ioremap(dev, base, PAGE_SIZE);
|
|
if (!csi->base)
|
|
return -ENOMEM;
|
|
|
|
dev_dbg(dev, "CSI%d base: 0x%08lx remapped to %p\n",
|
|
id, base, csi->base);
|
|
csi->ipu = ipu;
|
|
|
|
return 0;
|
|
}
|
|
|
|
void ipu_csi_exit(struct ipu_soc *ipu, int id)
|
|
{
|
|
}
|
|
|
|
void ipu_csi_dump(struct ipu_csi *csi)
|
|
{
|
|
dev_dbg(csi->ipu->dev, "CSI_SENS_CONF: %08x\n",
|
|
ipu_csi_read(csi, CSI_SENS_CONF));
|
|
dev_dbg(csi->ipu->dev, "CSI_SENS_FRM_SIZE: %08x\n",
|
|
ipu_csi_read(csi, CSI_SENS_FRM_SIZE));
|
|
dev_dbg(csi->ipu->dev, "CSI_ACT_FRM_SIZE: %08x\n",
|
|
ipu_csi_read(csi, CSI_ACT_FRM_SIZE));
|
|
dev_dbg(csi->ipu->dev, "CSI_OUT_FRM_CTRL: %08x\n",
|
|
ipu_csi_read(csi, CSI_OUT_FRM_CTRL));
|
|
dev_dbg(csi->ipu->dev, "CSI_TST_CTRL: %08x\n",
|
|
ipu_csi_read(csi, CSI_TST_CTRL));
|
|
dev_dbg(csi->ipu->dev, "CSI_CCIR_CODE_1: %08x\n",
|
|
ipu_csi_read(csi, CSI_CCIR_CODE_1));
|
|
dev_dbg(csi->ipu->dev, "CSI_CCIR_CODE_2: %08x\n",
|
|
ipu_csi_read(csi, CSI_CCIR_CODE_2));
|
|
dev_dbg(csi->ipu->dev, "CSI_CCIR_CODE_3: %08x\n",
|
|
ipu_csi_read(csi, CSI_CCIR_CODE_3));
|
|
dev_dbg(csi->ipu->dev, "CSI_MIPI_DI: %08x\n",
|
|
ipu_csi_read(csi, CSI_MIPI_DI));
|
|
dev_dbg(csi->ipu->dev, "CSI_SKIP: %08x\n",
|
|
ipu_csi_read(csi, CSI_SKIP));
|
|
}
|
|
EXPORT_SYMBOL_GPL(ipu_csi_dump);
|