738 lines
21 KiB
C
738 lines
21 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (c) 2018 Jernej Skrabec <jernej.skrabec@siol.net>
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*/
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#include <linux/delay.h>
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#include <linux/of_address.h>
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#include <linux/of_platform.h>
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#include "sun8i_dw_hdmi.h"
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/*
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* Address can be actually any value. Here is set to same value as
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* it is set in BSP driver.
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*/
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#define I2C_ADDR 0x69
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static const struct dw_hdmi_mpll_config sun50i_h6_mpll_cfg[] = {
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{
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30666000, {
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{ 0x00b3, 0x0000 },
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{ 0x2153, 0x0000 },
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{ 0x40f3, 0x0000 },
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},
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}, {
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36800000, {
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{ 0x00b3, 0x0000 },
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{ 0x2153, 0x0000 },
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{ 0x40a2, 0x0001 },
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},
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}, {
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46000000, {
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{ 0x00b3, 0x0000 },
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{ 0x2142, 0x0001 },
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{ 0x40a2, 0x0001 },
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},
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}, {
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61333000, {
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{ 0x0072, 0x0001 },
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{ 0x2142, 0x0001 },
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{ 0x40a2, 0x0001 },
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},
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}, {
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73600000, {
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{ 0x0072, 0x0001 },
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{ 0x2142, 0x0001 },
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{ 0x4061, 0x0002 },
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},
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}, {
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92000000, {
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{ 0x0072, 0x0001 },
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{ 0x2145, 0x0002 },
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{ 0x4061, 0x0002 },
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},
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}, {
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122666000, {
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{ 0x0051, 0x0002 },
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{ 0x2145, 0x0002 },
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{ 0x4061, 0x0002 },
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},
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}, {
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147200000, {
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{ 0x0051, 0x0002 },
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{ 0x2145, 0x0002 },
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{ 0x4064, 0x0003 },
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},
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}, {
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184000000, {
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{ 0x0051, 0x0002 },
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{ 0x214c, 0x0003 },
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{ 0x4064, 0x0003 },
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},
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}, {
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226666000, {
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{ 0x0040, 0x0003 },
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{ 0x214c, 0x0003 },
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{ 0x4064, 0x0003 },
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},
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}, {
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272000000, {
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{ 0x0040, 0x0003 },
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{ 0x214c, 0x0003 },
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{ 0x5a64, 0x0003 },
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},
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}, {
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340000000, {
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{ 0x0040, 0x0003 },
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{ 0x3b4c, 0x0003 },
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{ 0x5a64, 0x0003 },
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},
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}, {
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594000000, {
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{ 0x1a40, 0x0003 },
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{ 0x3b4c, 0x0003 },
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{ 0x5a64, 0x0003 },
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},
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}, {
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~0UL, {
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{ 0x0000, 0x0000 },
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{ 0x0000, 0x0000 },
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{ 0x0000, 0x0000 },
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},
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}
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};
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static const struct dw_hdmi_curr_ctrl sun50i_h6_cur_ctr[] = {
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/* pixelclk bpp8 bpp10 bpp12 */
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{ 27000000, { 0x0012, 0x0000, 0x0000 }, },
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{ 74250000, { 0x0013, 0x001a, 0x001b }, },
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{ 148500000, { 0x0019, 0x0033, 0x0034 }, },
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{ 297000000, { 0x0019, 0x001b, 0x001b }, },
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{ 594000000, { 0x0010, 0x001b, 0x001b }, },
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{ ~0UL, { 0x0000, 0x0000, 0x0000 }, }
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};
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static const struct dw_hdmi_phy_config sun50i_h6_phy_config[] = {
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/*pixelclk symbol term vlev*/
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{ 27000000, 0x8009, 0x0007, 0x02b0 },
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{ 74250000, 0x8009, 0x0006, 0x022d },
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{ 148500000, 0x8029, 0x0006, 0x0270 },
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{ 297000000, 0x8039, 0x0005, 0x01ab },
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{ 594000000, 0x8029, 0x0000, 0x008a },
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{ ~0UL, 0x0000, 0x0000, 0x0000}
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};
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static void sun8i_hdmi_phy_set_polarity(struct sun8i_hdmi_phy *phy,
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const struct drm_display_mode *mode)
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{
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u32 val = 0;
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if (mode->flags & DRM_MODE_FLAG_NHSYNC)
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val |= SUN8I_HDMI_PHY_DBG_CTRL_POL_NHSYNC;
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if (mode->flags & DRM_MODE_FLAG_NVSYNC)
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val |= SUN8I_HDMI_PHY_DBG_CTRL_POL_NVSYNC;
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regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_DBG_CTRL_REG,
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SUN8I_HDMI_PHY_DBG_CTRL_POL_MASK, val);
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};
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static int sun8i_a83t_hdmi_phy_config(struct dw_hdmi *hdmi, void *data,
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const struct drm_display_info *display,
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const struct drm_display_mode *mode)
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{
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unsigned int clk_rate = mode->crtc_clock * 1000;
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struct sun8i_hdmi_phy *phy = data;
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sun8i_hdmi_phy_set_polarity(phy, mode);
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regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_REXT_CTRL_REG,
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SUN8I_HDMI_PHY_REXT_CTRL_REXT_EN,
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SUN8I_HDMI_PHY_REXT_CTRL_REXT_EN);
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/* power down */
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dw_hdmi_phy_gen2_txpwron(hdmi, 0);
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dw_hdmi_phy_gen2_pddq(hdmi, 1);
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dw_hdmi_phy_gen2_reset(hdmi);
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dw_hdmi_phy_gen2_pddq(hdmi, 0);
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dw_hdmi_phy_i2c_set_addr(hdmi, I2C_ADDR);
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/*
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* Values are taken from BSP HDMI driver. Although AW didn't
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* release any documentation, explanation of this values can
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* be found in i.MX 6Dual/6Quad Reference Manual.
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*/
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if (clk_rate <= 27000000) {
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dw_hdmi_phy_i2c_write(hdmi, 0x01e0, 0x06);
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dw_hdmi_phy_i2c_write(hdmi, 0x0000, 0x15);
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dw_hdmi_phy_i2c_write(hdmi, 0x08da, 0x10);
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dw_hdmi_phy_i2c_write(hdmi, 0x0007, 0x19);
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dw_hdmi_phy_i2c_write(hdmi, 0x0318, 0x0e);
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dw_hdmi_phy_i2c_write(hdmi, 0x8009, 0x09);
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} else if (clk_rate <= 74250000) {
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dw_hdmi_phy_i2c_write(hdmi, 0x0540, 0x06);
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dw_hdmi_phy_i2c_write(hdmi, 0x0005, 0x15);
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dw_hdmi_phy_i2c_write(hdmi, 0x0000, 0x10);
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dw_hdmi_phy_i2c_write(hdmi, 0x0007, 0x19);
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dw_hdmi_phy_i2c_write(hdmi, 0x02b5, 0x0e);
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dw_hdmi_phy_i2c_write(hdmi, 0x8009, 0x09);
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} else if (clk_rate <= 148500000) {
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dw_hdmi_phy_i2c_write(hdmi, 0x04a0, 0x06);
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dw_hdmi_phy_i2c_write(hdmi, 0x000a, 0x15);
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dw_hdmi_phy_i2c_write(hdmi, 0x0000, 0x10);
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dw_hdmi_phy_i2c_write(hdmi, 0x0002, 0x19);
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dw_hdmi_phy_i2c_write(hdmi, 0x0021, 0x0e);
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dw_hdmi_phy_i2c_write(hdmi, 0x8029, 0x09);
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} else {
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dw_hdmi_phy_i2c_write(hdmi, 0x0000, 0x06);
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dw_hdmi_phy_i2c_write(hdmi, 0x000f, 0x15);
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dw_hdmi_phy_i2c_write(hdmi, 0x0000, 0x10);
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dw_hdmi_phy_i2c_write(hdmi, 0x0002, 0x19);
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dw_hdmi_phy_i2c_write(hdmi, 0x0000, 0x0e);
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dw_hdmi_phy_i2c_write(hdmi, 0x802b, 0x09);
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}
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dw_hdmi_phy_i2c_write(hdmi, 0x0000, 0x1e);
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dw_hdmi_phy_i2c_write(hdmi, 0x0000, 0x13);
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dw_hdmi_phy_i2c_write(hdmi, 0x0000, 0x17);
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dw_hdmi_phy_gen2_txpwron(hdmi, 1);
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return 0;
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}
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static void sun8i_a83t_hdmi_phy_disable(struct dw_hdmi *hdmi, void *data)
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{
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struct sun8i_hdmi_phy *phy = data;
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dw_hdmi_phy_gen2_txpwron(hdmi, 0);
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dw_hdmi_phy_gen2_pddq(hdmi, 1);
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regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_REXT_CTRL_REG,
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SUN8I_HDMI_PHY_REXT_CTRL_REXT_EN, 0);
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}
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static const struct dw_hdmi_phy_ops sun8i_a83t_hdmi_phy_ops = {
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.init = sun8i_a83t_hdmi_phy_config,
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.disable = sun8i_a83t_hdmi_phy_disable,
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.read_hpd = dw_hdmi_phy_read_hpd,
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.update_hpd = dw_hdmi_phy_update_hpd,
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.setup_hpd = dw_hdmi_phy_setup_hpd,
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};
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static int sun8i_h3_hdmi_phy_config(struct dw_hdmi *hdmi, void *data,
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const struct drm_display_info *display,
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const struct drm_display_mode *mode)
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{
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unsigned int clk_rate = mode->crtc_clock * 1000;
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struct sun8i_hdmi_phy *phy = data;
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u32 pll_cfg1_init;
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u32 pll_cfg2_init;
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u32 ana_cfg1_end;
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u32 ana_cfg2_init;
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u32 ana_cfg3_init;
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u32 b_offset = 0;
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u32 val;
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if (phy->variant->has_phy_clk)
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clk_set_rate(phy->clk_phy, clk_rate);
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sun8i_hdmi_phy_set_polarity(phy, mode);
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/* bandwidth / frequency independent settings */
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pll_cfg1_init = SUN8I_HDMI_PHY_PLL_CFG1_LDO2_EN |
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SUN8I_HDMI_PHY_PLL_CFG1_LDO1_EN |
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SUN8I_HDMI_PHY_PLL_CFG1_LDO_VSET(7) |
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SUN8I_HDMI_PHY_PLL_CFG1_UNKNOWN(1) |
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SUN8I_HDMI_PHY_PLL_CFG1_PLLDBEN |
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SUN8I_HDMI_PHY_PLL_CFG1_CS |
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SUN8I_HDMI_PHY_PLL_CFG1_CP_S(2) |
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SUN8I_HDMI_PHY_PLL_CFG1_CNT_INT(63) |
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SUN8I_HDMI_PHY_PLL_CFG1_BWS;
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pll_cfg2_init = SUN8I_HDMI_PHY_PLL_CFG2_SV_H |
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SUN8I_HDMI_PHY_PLL_CFG2_VCOGAIN_EN |
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SUN8I_HDMI_PHY_PLL_CFG2_SDIV2;
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ana_cfg1_end = SUN8I_HDMI_PHY_ANA_CFG1_REG_SVBH(1) |
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SUN8I_HDMI_PHY_ANA_CFG1_AMP_OPT |
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SUN8I_HDMI_PHY_ANA_CFG1_EMP_OPT |
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SUN8I_HDMI_PHY_ANA_CFG1_AMPCK_OPT |
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SUN8I_HDMI_PHY_ANA_CFG1_EMPCK_OPT |
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SUN8I_HDMI_PHY_ANA_CFG1_ENRCAL |
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SUN8I_HDMI_PHY_ANA_CFG1_ENCALOG |
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SUN8I_HDMI_PHY_ANA_CFG1_REG_SCKTMDS |
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SUN8I_HDMI_PHY_ANA_CFG1_TMDSCLK_EN |
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SUN8I_HDMI_PHY_ANA_CFG1_TXEN_MASK |
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SUN8I_HDMI_PHY_ANA_CFG1_TXEN_ALL |
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SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDSCLK |
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SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDS2 |
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SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDS1 |
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SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDS0 |
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SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDS2 |
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SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDS1 |
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SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDS0 |
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SUN8I_HDMI_PHY_ANA_CFG1_CKEN |
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SUN8I_HDMI_PHY_ANA_CFG1_LDOEN |
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SUN8I_HDMI_PHY_ANA_CFG1_ENVBS |
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SUN8I_HDMI_PHY_ANA_CFG1_ENBI;
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ana_cfg2_init = SUN8I_HDMI_PHY_ANA_CFG2_M_EN |
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SUN8I_HDMI_PHY_ANA_CFG2_REG_DENCK |
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SUN8I_HDMI_PHY_ANA_CFG2_REG_DEN |
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SUN8I_HDMI_PHY_ANA_CFG2_REG_CKSS(1) |
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SUN8I_HDMI_PHY_ANA_CFG2_REG_CSMPS(1);
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ana_cfg3_init = SUN8I_HDMI_PHY_ANA_CFG3_REG_WIRE(0x3e0) |
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SUN8I_HDMI_PHY_ANA_CFG3_SDAEN |
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SUN8I_HDMI_PHY_ANA_CFG3_SCLEN;
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/* bandwidth / frequency dependent settings */
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if (clk_rate <= 27000000) {
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pll_cfg1_init |= SUN8I_HDMI_PHY_PLL_CFG1_HV_IS_33 |
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SUN8I_HDMI_PHY_PLL_CFG1_CNT_INT(32);
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pll_cfg2_init |= SUN8I_HDMI_PHY_PLL_CFG2_VCO_S(4) |
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SUN8I_HDMI_PHY_PLL_CFG2_S(4);
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ana_cfg1_end |= SUN8I_HDMI_PHY_ANA_CFG1_REG_CALSW;
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ana_cfg2_init |= SUN8I_HDMI_PHY_ANA_CFG2_REG_SLV(4) |
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SUN8I_HDMI_PHY_ANA_CFG2_REG_RESDI(phy->rcal);
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ana_cfg3_init |= SUN8I_HDMI_PHY_ANA_CFG3_REG_AMPCK(3) |
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SUN8I_HDMI_PHY_ANA_CFG3_REG_AMP(5);
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} else if (clk_rate <= 74250000) {
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pll_cfg1_init |= SUN8I_HDMI_PHY_PLL_CFG1_HV_IS_33 |
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SUN8I_HDMI_PHY_PLL_CFG1_CNT_INT(32);
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pll_cfg2_init |= SUN8I_HDMI_PHY_PLL_CFG2_VCO_S(4) |
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SUN8I_HDMI_PHY_PLL_CFG2_S(5);
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ana_cfg1_end |= SUN8I_HDMI_PHY_ANA_CFG1_REG_CALSW;
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ana_cfg2_init |= SUN8I_HDMI_PHY_ANA_CFG2_REG_SLV(4) |
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SUN8I_HDMI_PHY_ANA_CFG2_REG_RESDI(phy->rcal);
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ana_cfg3_init |= SUN8I_HDMI_PHY_ANA_CFG3_REG_AMPCK(5) |
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SUN8I_HDMI_PHY_ANA_CFG3_REG_AMP(7);
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} else if (clk_rate <= 148500000) {
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pll_cfg1_init |= SUN8I_HDMI_PHY_PLL_CFG1_HV_IS_33 |
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SUN8I_HDMI_PHY_PLL_CFG1_CNT_INT(32);
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pll_cfg2_init |= SUN8I_HDMI_PHY_PLL_CFG2_VCO_S(4) |
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SUN8I_HDMI_PHY_PLL_CFG2_S(6);
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ana_cfg2_init |= SUN8I_HDMI_PHY_ANA_CFG2_REG_BIGSWCK |
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SUN8I_HDMI_PHY_ANA_CFG2_REG_BIGSW |
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SUN8I_HDMI_PHY_ANA_CFG2_REG_SLV(2);
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ana_cfg3_init |= SUN8I_HDMI_PHY_ANA_CFG3_REG_AMPCK(7) |
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SUN8I_HDMI_PHY_ANA_CFG3_REG_AMP(9);
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} else {
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b_offset = 2;
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pll_cfg1_init |= SUN8I_HDMI_PHY_PLL_CFG1_CNT_INT(63);
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pll_cfg2_init |= SUN8I_HDMI_PHY_PLL_CFG2_VCO_S(6) |
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SUN8I_HDMI_PHY_PLL_CFG2_S(7);
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ana_cfg2_init |= SUN8I_HDMI_PHY_ANA_CFG2_REG_BIGSWCK |
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SUN8I_HDMI_PHY_ANA_CFG2_REG_BIGSW |
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SUN8I_HDMI_PHY_ANA_CFG2_REG_SLV(4);
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ana_cfg3_init |= SUN8I_HDMI_PHY_ANA_CFG3_REG_AMPCK(9) |
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SUN8I_HDMI_PHY_ANA_CFG3_REG_AMP(13) |
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SUN8I_HDMI_PHY_ANA_CFG3_REG_EMP(3);
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}
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regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_ANA_CFG1_REG,
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SUN8I_HDMI_PHY_ANA_CFG1_TXEN_MASK, 0);
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/*
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* NOTE: We have to be careful not to overwrite PHY parent
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* clock selection bit and clock divider.
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*/
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regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_PLL_CFG1_REG,
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(u32)~SUN8I_HDMI_PHY_PLL_CFG1_CKIN_SEL_MSK,
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pll_cfg1_init);
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regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_PLL_CFG2_REG,
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(u32)~SUN8I_HDMI_PHY_PLL_CFG2_PREDIV_MSK,
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pll_cfg2_init);
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usleep_range(10000, 15000);
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regmap_write(phy->regs, SUN8I_HDMI_PHY_PLL_CFG3_REG,
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SUN8I_HDMI_PHY_PLL_CFG3_SOUT_DIV2);
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regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_PLL_CFG1_REG,
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SUN8I_HDMI_PHY_PLL_CFG1_PLLEN,
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SUN8I_HDMI_PHY_PLL_CFG1_PLLEN);
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msleep(100);
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/* get B value */
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regmap_read(phy->regs, SUN8I_HDMI_PHY_ANA_STS_REG, &val);
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val = (val & SUN8I_HDMI_PHY_ANA_STS_B_OUT_MSK) >>
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SUN8I_HDMI_PHY_ANA_STS_B_OUT_SHIFT;
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val = min(val + b_offset, (u32)0x3f);
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regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_PLL_CFG1_REG,
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SUN8I_HDMI_PHY_PLL_CFG1_REG_OD1 |
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SUN8I_HDMI_PHY_PLL_CFG1_REG_OD,
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SUN8I_HDMI_PHY_PLL_CFG1_REG_OD1 |
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SUN8I_HDMI_PHY_PLL_CFG1_REG_OD);
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regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_PLL_CFG1_REG,
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SUN8I_HDMI_PHY_PLL_CFG1_B_IN_MSK,
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val << SUN8I_HDMI_PHY_PLL_CFG1_B_IN_SHIFT);
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msleep(100);
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regmap_write(phy->regs, SUN8I_HDMI_PHY_ANA_CFG1_REG, ana_cfg1_end);
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regmap_write(phy->regs, SUN8I_HDMI_PHY_ANA_CFG2_REG, ana_cfg2_init);
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regmap_write(phy->regs, SUN8I_HDMI_PHY_ANA_CFG3_REG, ana_cfg3_init);
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return 0;
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}
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|
|
static void sun8i_h3_hdmi_phy_disable(struct dw_hdmi *hdmi, void *data)
|
|
{
|
|
struct sun8i_hdmi_phy *phy = data;
|
|
|
|
regmap_write(phy->regs, SUN8I_HDMI_PHY_ANA_CFG1_REG,
|
|
SUN8I_HDMI_PHY_ANA_CFG1_LDOEN |
|
|
SUN8I_HDMI_PHY_ANA_CFG1_ENVBS |
|
|
SUN8I_HDMI_PHY_ANA_CFG1_ENBI);
|
|
regmap_write(phy->regs, SUN8I_HDMI_PHY_PLL_CFG1_REG, 0);
|
|
}
|
|
|
|
static const struct dw_hdmi_phy_ops sun8i_h3_hdmi_phy_ops = {
|
|
.init = sun8i_h3_hdmi_phy_config,
|
|
.disable = sun8i_h3_hdmi_phy_disable,
|
|
.read_hpd = dw_hdmi_phy_read_hpd,
|
|
.update_hpd = dw_hdmi_phy_update_hpd,
|
|
.setup_hpd = dw_hdmi_phy_setup_hpd,
|
|
};
|
|
|
|
static void sun8i_hdmi_phy_unlock(struct sun8i_hdmi_phy *phy)
|
|
{
|
|
/* enable read access to HDMI controller */
|
|
regmap_write(phy->regs, SUN8I_HDMI_PHY_READ_EN_REG,
|
|
SUN8I_HDMI_PHY_READ_EN_MAGIC);
|
|
|
|
/* unscramble register offsets */
|
|
regmap_write(phy->regs, SUN8I_HDMI_PHY_UNSCRAMBLE_REG,
|
|
SUN8I_HDMI_PHY_UNSCRAMBLE_MAGIC);
|
|
}
|
|
|
|
static void sun50i_hdmi_phy_init_h6(struct sun8i_hdmi_phy *phy)
|
|
{
|
|
regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_REXT_CTRL_REG,
|
|
SUN8I_HDMI_PHY_REXT_CTRL_REXT_EN,
|
|
SUN8I_HDMI_PHY_REXT_CTRL_REXT_EN);
|
|
|
|
regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_REXT_CTRL_REG,
|
|
0xffff0000, 0x80c00000);
|
|
}
|
|
|
|
static void sun8i_hdmi_phy_init_a83t(struct sun8i_hdmi_phy *phy)
|
|
{
|
|
sun8i_hdmi_phy_unlock(phy);
|
|
|
|
regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_DBG_CTRL_REG,
|
|
SUN8I_HDMI_PHY_DBG_CTRL_PX_LOCK,
|
|
SUN8I_HDMI_PHY_DBG_CTRL_PX_LOCK);
|
|
|
|
/*
|
|
* Set PHY I2C address. It must match to the address set by
|
|
* dw_hdmi_phy_set_slave_addr().
|
|
*/
|
|
regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_DBG_CTRL_REG,
|
|
SUN8I_HDMI_PHY_DBG_CTRL_ADDR_MASK,
|
|
SUN8I_HDMI_PHY_DBG_CTRL_ADDR(I2C_ADDR));
|
|
}
|
|
|
|
static void sun8i_hdmi_phy_init_h3(struct sun8i_hdmi_phy *phy)
|
|
{
|
|
unsigned int val;
|
|
|
|
sun8i_hdmi_phy_unlock(phy);
|
|
|
|
regmap_write(phy->regs, SUN8I_HDMI_PHY_ANA_CFG1_REG, 0);
|
|
regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_ANA_CFG1_REG,
|
|
SUN8I_HDMI_PHY_ANA_CFG1_ENBI,
|
|
SUN8I_HDMI_PHY_ANA_CFG1_ENBI);
|
|
udelay(5);
|
|
regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_ANA_CFG1_REG,
|
|
SUN8I_HDMI_PHY_ANA_CFG1_TMDSCLK_EN,
|
|
SUN8I_HDMI_PHY_ANA_CFG1_TMDSCLK_EN);
|
|
regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_ANA_CFG1_REG,
|
|
SUN8I_HDMI_PHY_ANA_CFG1_ENVBS,
|
|
SUN8I_HDMI_PHY_ANA_CFG1_ENVBS);
|
|
usleep_range(10, 20);
|
|
regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_ANA_CFG1_REG,
|
|
SUN8I_HDMI_PHY_ANA_CFG1_LDOEN,
|
|
SUN8I_HDMI_PHY_ANA_CFG1_LDOEN);
|
|
udelay(5);
|
|
regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_ANA_CFG1_REG,
|
|
SUN8I_HDMI_PHY_ANA_CFG1_CKEN,
|
|
SUN8I_HDMI_PHY_ANA_CFG1_CKEN);
|
|
usleep_range(40, 100);
|
|
regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_ANA_CFG1_REG,
|
|
SUN8I_HDMI_PHY_ANA_CFG1_ENRCAL,
|
|
SUN8I_HDMI_PHY_ANA_CFG1_ENRCAL);
|
|
usleep_range(100, 200);
|
|
regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_ANA_CFG1_REG,
|
|
SUN8I_HDMI_PHY_ANA_CFG1_ENCALOG,
|
|
SUN8I_HDMI_PHY_ANA_CFG1_ENCALOG);
|
|
regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_ANA_CFG1_REG,
|
|
SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDS0 |
|
|
SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDS1 |
|
|
SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDS2,
|
|
SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDS0 |
|
|
SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDS1 |
|
|
SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDS2);
|
|
|
|
/* wait for calibration to finish */
|
|
regmap_read_poll_timeout(phy->regs, SUN8I_HDMI_PHY_ANA_STS_REG, val,
|
|
(val & SUN8I_HDMI_PHY_ANA_STS_RCALEND2D),
|
|
100, 2000);
|
|
|
|
regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_ANA_CFG1_REG,
|
|
SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDSCLK,
|
|
SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDSCLK);
|
|
regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_ANA_CFG1_REG,
|
|
SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDS0 |
|
|
SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDS1 |
|
|
SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDS2 |
|
|
SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDSCLK,
|
|
SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDS0 |
|
|
SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDS1 |
|
|
SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDS2 |
|
|
SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDSCLK);
|
|
|
|
/* enable DDC communication */
|
|
regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_ANA_CFG3_REG,
|
|
SUN8I_HDMI_PHY_ANA_CFG3_SCLEN |
|
|
SUN8I_HDMI_PHY_ANA_CFG3_SDAEN,
|
|
SUN8I_HDMI_PHY_ANA_CFG3_SCLEN |
|
|
SUN8I_HDMI_PHY_ANA_CFG3_SDAEN);
|
|
|
|
/* reset PHY PLL clock parent */
|
|
regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_PLL_CFG1_REG,
|
|
SUN8I_HDMI_PHY_PLL_CFG1_CKIN_SEL_MSK, 0);
|
|
|
|
/* set HW control of CEC pins */
|
|
regmap_write(phy->regs, SUN8I_HDMI_PHY_CEC_REG, 0);
|
|
|
|
/* read calibration data */
|
|
regmap_read(phy->regs, SUN8I_HDMI_PHY_ANA_STS_REG, &val);
|
|
phy->rcal = (val & SUN8I_HDMI_PHY_ANA_STS_RCAL_MASK) >> 2;
|
|
}
|
|
|
|
int sun8i_hdmi_phy_init(struct sun8i_hdmi_phy *phy)
|
|
{
|
|
int ret;
|
|
|
|
ret = reset_control_deassert(phy->rst_phy);
|
|
if (ret) {
|
|
dev_err(phy->dev, "Cannot deassert phy reset control: %d\n", ret);
|
|
return ret;
|
|
}
|
|
|
|
ret = clk_prepare_enable(phy->clk_bus);
|
|
if (ret) {
|
|
dev_err(phy->dev, "Cannot enable bus clock: %d\n", ret);
|
|
goto err_assert_rst_phy;
|
|
}
|
|
|
|
ret = clk_prepare_enable(phy->clk_mod);
|
|
if (ret) {
|
|
dev_err(phy->dev, "Cannot enable mod clock: %d\n", ret);
|
|
goto err_disable_clk_bus;
|
|
}
|
|
|
|
if (phy->variant->has_phy_clk) {
|
|
ret = sun8i_phy_clk_create(phy, phy->dev,
|
|
phy->variant->has_second_pll);
|
|
if (ret) {
|
|
dev_err(phy->dev, "Couldn't create the PHY clock\n");
|
|
goto err_disable_clk_mod;
|
|
}
|
|
|
|
clk_prepare_enable(phy->clk_phy);
|
|
}
|
|
|
|
phy->variant->phy_init(phy);
|
|
|
|
return 0;
|
|
|
|
err_disable_clk_mod:
|
|
clk_disable_unprepare(phy->clk_mod);
|
|
err_disable_clk_bus:
|
|
clk_disable_unprepare(phy->clk_bus);
|
|
err_assert_rst_phy:
|
|
reset_control_assert(phy->rst_phy);
|
|
|
|
return ret;
|
|
}
|
|
|
|
void sun8i_hdmi_phy_deinit(struct sun8i_hdmi_phy *phy)
|
|
{
|
|
clk_disable_unprepare(phy->clk_mod);
|
|
clk_disable_unprepare(phy->clk_bus);
|
|
clk_disable_unprepare(phy->clk_phy);
|
|
|
|
reset_control_assert(phy->rst_phy);
|
|
}
|
|
|
|
void sun8i_hdmi_phy_set_ops(struct sun8i_hdmi_phy *phy,
|
|
struct dw_hdmi_plat_data *plat_data)
|
|
{
|
|
const struct sun8i_hdmi_phy_variant *variant = phy->variant;
|
|
|
|
if (variant->phy_ops) {
|
|
plat_data->phy_ops = variant->phy_ops;
|
|
plat_data->phy_name = "sun8i_dw_hdmi_phy";
|
|
plat_data->phy_data = phy;
|
|
} else {
|
|
plat_data->mpll_cfg = variant->mpll_cfg;
|
|
plat_data->cur_ctr = variant->cur_ctr;
|
|
plat_data->phy_config = variant->phy_cfg;
|
|
}
|
|
}
|
|
|
|
static const struct regmap_config sun8i_hdmi_phy_regmap_config = {
|
|
.reg_bits = 32,
|
|
.val_bits = 32,
|
|
.reg_stride = 4,
|
|
.max_register = SUN8I_HDMI_PHY_CEC_REG,
|
|
.name = "phy"
|
|
};
|
|
|
|
static const struct sun8i_hdmi_phy_variant sun8i_a83t_hdmi_phy = {
|
|
.phy_ops = &sun8i_a83t_hdmi_phy_ops,
|
|
.phy_init = &sun8i_hdmi_phy_init_a83t,
|
|
};
|
|
|
|
static const struct sun8i_hdmi_phy_variant sun8i_h3_hdmi_phy = {
|
|
.has_phy_clk = true,
|
|
.phy_ops = &sun8i_h3_hdmi_phy_ops,
|
|
.phy_init = &sun8i_hdmi_phy_init_h3,
|
|
};
|
|
|
|
static const struct sun8i_hdmi_phy_variant sun8i_r40_hdmi_phy = {
|
|
.has_phy_clk = true,
|
|
.has_second_pll = true,
|
|
.phy_ops = &sun8i_h3_hdmi_phy_ops,
|
|
.phy_init = &sun8i_hdmi_phy_init_h3,
|
|
};
|
|
|
|
static const struct sun8i_hdmi_phy_variant sun50i_a64_hdmi_phy = {
|
|
.has_phy_clk = true,
|
|
.phy_ops = &sun8i_h3_hdmi_phy_ops,
|
|
.phy_init = &sun8i_hdmi_phy_init_h3,
|
|
};
|
|
|
|
static const struct sun8i_hdmi_phy_variant sun50i_h6_hdmi_phy = {
|
|
.cur_ctr = sun50i_h6_cur_ctr,
|
|
.mpll_cfg = sun50i_h6_mpll_cfg,
|
|
.phy_cfg = sun50i_h6_phy_config,
|
|
.phy_init = &sun50i_hdmi_phy_init_h6,
|
|
};
|
|
|
|
static const struct of_device_id sun8i_hdmi_phy_of_table[] = {
|
|
{
|
|
.compatible = "allwinner,sun8i-a83t-hdmi-phy",
|
|
.data = &sun8i_a83t_hdmi_phy,
|
|
},
|
|
{
|
|
.compatible = "allwinner,sun8i-h3-hdmi-phy",
|
|
.data = &sun8i_h3_hdmi_phy,
|
|
},
|
|
{
|
|
.compatible = "allwinner,sun8i-r40-hdmi-phy",
|
|
.data = &sun8i_r40_hdmi_phy,
|
|
},
|
|
{
|
|
.compatible = "allwinner,sun50i-a64-hdmi-phy",
|
|
.data = &sun50i_a64_hdmi_phy,
|
|
},
|
|
{
|
|
.compatible = "allwinner,sun50i-h6-hdmi-phy",
|
|
.data = &sun50i_h6_hdmi_phy,
|
|
},
|
|
{ /* sentinel */ }
|
|
};
|
|
|
|
int sun8i_hdmi_phy_get(struct sun8i_dw_hdmi *hdmi, struct device_node *node)
|
|
{
|
|
struct platform_device *pdev = of_find_device_by_node(node);
|
|
struct sun8i_hdmi_phy *phy;
|
|
|
|
if (!pdev)
|
|
return -EPROBE_DEFER;
|
|
|
|
phy = platform_get_drvdata(pdev);
|
|
if (!phy) {
|
|
put_device(&pdev->dev);
|
|
return -EPROBE_DEFER;
|
|
}
|
|
|
|
hdmi->phy = phy;
|
|
|
|
put_device(&pdev->dev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int sun8i_hdmi_phy_probe(struct platform_device *pdev)
|
|
{
|
|
struct device *dev = &pdev->dev;
|
|
struct sun8i_hdmi_phy *phy;
|
|
void __iomem *regs;
|
|
|
|
phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
|
|
if (!phy)
|
|
return -ENOMEM;
|
|
|
|
phy->variant = of_device_get_match_data(dev);
|
|
phy->dev = dev;
|
|
|
|
regs = devm_platform_ioremap_resource(pdev, 0);
|
|
if (IS_ERR(regs))
|
|
return dev_err_probe(dev, PTR_ERR(regs),
|
|
"Couldn't map the HDMI PHY registers\n");
|
|
|
|
phy->regs = devm_regmap_init_mmio(dev, regs,
|
|
&sun8i_hdmi_phy_regmap_config);
|
|
if (IS_ERR(phy->regs))
|
|
return dev_err_probe(dev, PTR_ERR(phy->regs),
|
|
"Couldn't create the HDMI PHY regmap\n");
|
|
|
|
phy->clk_bus = devm_clk_get(dev, "bus");
|
|
if (IS_ERR(phy->clk_bus))
|
|
return dev_err_probe(dev, PTR_ERR(phy->clk_bus),
|
|
"Could not get bus clock\n");
|
|
|
|
phy->clk_mod = devm_clk_get(dev, "mod");
|
|
if (IS_ERR(phy->clk_mod))
|
|
return dev_err_probe(dev, PTR_ERR(phy->clk_mod),
|
|
"Could not get mod clock\n");
|
|
|
|
if (phy->variant->has_phy_clk) {
|
|
phy->clk_pll0 = devm_clk_get(dev, "pll-0");
|
|
if (IS_ERR(phy->clk_pll0))
|
|
return dev_err_probe(dev, PTR_ERR(phy->clk_pll0),
|
|
"Could not get pll-0 clock\n");
|
|
|
|
if (phy->variant->has_second_pll) {
|
|
phy->clk_pll1 = devm_clk_get(dev, "pll-1");
|
|
if (IS_ERR(phy->clk_pll1))
|
|
return dev_err_probe(dev, PTR_ERR(phy->clk_pll1),
|
|
"Could not get pll-1 clock\n");
|
|
}
|
|
}
|
|
|
|
phy->rst_phy = devm_reset_control_get_shared(dev, "phy");
|
|
if (IS_ERR(phy->rst_phy))
|
|
return dev_err_probe(dev, PTR_ERR(phy->rst_phy),
|
|
"Could not get phy reset control\n");
|
|
|
|
platform_set_drvdata(pdev, phy);
|
|
|
|
return 0;
|
|
}
|
|
|
|
struct platform_driver sun8i_hdmi_phy_driver = {
|
|
.probe = sun8i_hdmi_phy_probe,
|
|
.driver = {
|
|
.name = "sun8i-hdmi-phy",
|
|
.of_match_table = sun8i_hdmi_phy_of_table,
|
|
},
|
|
};
|