638 lines
18 KiB
C
638 lines
18 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Driver for panels based on Sitronix ST7703 controller, souch as:
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*
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* - Rocktech jh057n00900 5.5" MIPI-DSI panel
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*
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* Copyright (C) Purism SPC 2019
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*/
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#include <linux/debugfs.h>
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#include <linux/delay.h>
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#include <linux/gpio/consumer.h>
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#include <linux/media-bus-format.h>
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#include <linux/mod_devicetable.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/regulator/consumer.h>
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#include <video/display_timing.h>
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#include <video/mipi_display.h>
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#include <drm/drm_mipi_dsi.h>
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#include <drm/drm_modes.h>
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#include <drm/drm_panel.h>
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#define DRV_NAME "panel-sitronix-st7703"
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/* Manufacturer specific Commands send via DSI */
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#define ST7703_CMD_ALL_PIXEL_OFF 0x22
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#define ST7703_CMD_ALL_PIXEL_ON 0x23
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#define ST7703_CMD_SETDISP 0xB2
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#define ST7703_CMD_SETRGBIF 0xB3
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#define ST7703_CMD_SETCYC 0xB4
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#define ST7703_CMD_SETBGP 0xB5
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#define ST7703_CMD_SETVCOM 0xB6
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#define ST7703_CMD_SETOTP 0xB7
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#define ST7703_CMD_SETPOWER_EXT 0xB8
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#define ST7703_CMD_SETEXTC 0xB9
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#define ST7703_CMD_SETMIPI 0xBA
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#define ST7703_CMD_SETVDC 0xBC
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#define ST7703_CMD_UNKNOWN_BF 0xBF
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#define ST7703_CMD_SETSCR 0xC0
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#define ST7703_CMD_SETPOWER 0xC1
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#define ST7703_CMD_SETPANEL 0xCC
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#define ST7703_CMD_UNKNOWN_C6 0xC6
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#define ST7703_CMD_SETGAMMA 0xE0
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#define ST7703_CMD_SETEQ 0xE3
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#define ST7703_CMD_SETGIP1 0xE9
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#define ST7703_CMD_SETGIP2 0xEA
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struct st7703 {
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struct device *dev;
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struct drm_panel panel;
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struct gpio_desc *reset_gpio;
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struct regulator *vcc;
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struct regulator *iovcc;
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bool prepared;
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struct dentry *debugfs;
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const struct st7703_panel_desc *desc;
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};
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struct st7703_panel_desc {
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const struct drm_display_mode *mode;
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unsigned int lanes;
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unsigned long mode_flags;
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enum mipi_dsi_pixel_format format;
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int (*init_sequence)(struct st7703 *ctx);
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};
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static inline struct st7703 *panel_to_st7703(struct drm_panel *panel)
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{
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return container_of(panel, struct st7703, panel);
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}
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#define dsi_generic_write_seq(dsi, seq...) do { \
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static const u8 d[] = { seq }; \
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int ret; \
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ret = mipi_dsi_generic_write(dsi, d, ARRAY_SIZE(d)); \
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if (ret < 0) \
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return ret; \
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} while (0)
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static int jh057n_init_sequence(struct st7703 *ctx)
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{
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struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
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/*
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* Init sequence was supplied by the panel vendor. Most of the commands
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* resemble the ST7703 but the number of parameters often don't match
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* so it's likely a clone.
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*/
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dsi_generic_write_seq(dsi, ST7703_CMD_SETEXTC,
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0xF1, 0x12, 0x83);
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dsi_generic_write_seq(dsi, ST7703_CMD_SETRGBIF,
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0x10, 0x10, 0x05, 0x05, 0x03, 0xFF, 0x00, 0x00,
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0x00, 0x00);
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dsi_generic_write_seq(dsi, ST7703_CMD_SETSCR,
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0x73, 0x73, 0x50, 0x50, 0x00, 0x00, 0x08, 0x70,
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0x00);
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dsi_generic_write_seq(dsi, ST7703_CMD_SETVDC, 0x4E);
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dsi_generic_write_seq(dsi, ST7703_CMD_SETPANEL, 0x0B);
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dsi_generic_write_seq(dsi, ST7703_CMD_SETCYC, 0x80);
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dsi_generic_write_seq(dsi, ST7703_CMD_SETDISP, 0xF0, 0x12, 0x30);
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dsi_generic_write_seq(dsi, ST7703_CMD_SETEQ,
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0x07, 0x07, 0x0B, 0x0B, 0x03, 0x0B, 0x00, 0x00,
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0x00, 0x00, 0xFF, 0x00, 0xC0, 0x10);
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dsi_generic_write_seq(dsi, ST7703_CMD_SETBGP, 0x08, 0x08);
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msleep(20);
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dsi_generic_write_seq(dsi, ST7703_CMD_SETVCOM, 0x3F, 0x3F);
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dsi_generic_write_seq(dsi, ST7703_CMD_UNKNOWN_BF, 0x02, 0x11, 0x00);
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dsi_generic_write_seq(dsi, ST7703_CMD_SETGIP1,
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0x82, 0x10, 0x06, 0x05, 0x9E, 0x0A, 0xA5, 0x12,
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0x31, 0x23, 0x37, 0x83, 0x04, 0xBC, 0x27, 0x38,
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0x0C, 0x00, 0x03, 0x00, 0x00, 0x00, 0x0C, 0x00,
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0x03, 0x00, 0x00, 0x00, 0x75, 0x75, 0x31, 0x88,
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0x88, 0x88, 0x88, 0x88, 0x88, 0x13, 0x88, 0x64,
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0x64, 0x20, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88,
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0x02, 0x88, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00);
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dsi_generic_write_seq(dsi, ST7703_CMD_SETGIP2,
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0x02, 0x21, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x02, 0x46, 0x02, 0x88,
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0x88, 0x88, 0x88, 0x88, 0x88, 0x64, 0x88, 0x13,
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0x57, 0x13, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88,
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0x75, 0x88, 0x23, 0x14, 0x00, 0x00, 0x02, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x0A,
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0xA5, 0x00, 0x00, 0x00, 0x00);
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dsi_generic_write_seq(dsi, ST7703_CMD_SETGAMMA,
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0x00, 0x09, 0x0E, 0x29, 0x2D, 0x3C, 0x41, 0x37,
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0x07, 0x0B, 0x0D, 0x10, 0x11, 0x0F, 0x10, 0x11,
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0x18, 0x00, 0x09, 0x0E, 0x29, 0x2D, 0x3C, 0x41,
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0x37, 0x07, 0x0B, 0x0D, 0x10, 0x11, 0x0F, 0x10,
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0x11, 0x18);
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return 0;
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}
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static const struct drm_display_mode jh057n00900_mode = {
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.hdisplay = 720,
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.hsync_start = 720 + 90,
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.hsync_end = 720 + 90 + 20,
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.htotal = 720 + 90 + 20 + 20,
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.vdisplay = 1440,
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.vsync_start = 1440 + 20,
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.vsync_end = 1440 + 20 + 4,
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.vtotal = 1440 + 20 + 4 + 12,
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.clock = 75276,
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.flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
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.width_mm = 65,
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.height_mm = 130,
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};
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static const struct st7703_panel_desc jh057n00900_panel_desc = {
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.mode = &jh057n00900_mode,
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.lanes = 4,
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.mode_flags = MIPI_DSI_MODE_VIDEO |
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MIPI_DSI_MODE_VIDEO_BURST | MIPI_DSI_MODE_VIDEO_SYNC_PULSE,
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.format = MIPI_DSI_FMT_RGB888,
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.init_sequence = jh057n_init_sequence,
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};
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#define dsi_dcs_write_seq(dsi, cmd, seq...) do { \
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static const u8 d[] = { seq }; \
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int ret; \
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ret = mipi_dsi_dcs_write(dsi, cmd, d, ARRAY_SIZE(d)); \
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if (ret < 0) \
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return ret; \
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} while (0)
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static int xbd599_init_sequence(struct st7703 *ctx)
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{
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struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
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/*
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* Init sequence was supplied by the panel vendor.
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*/
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/* Magic sequence to unlock user commands below. */
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dsi_dcs_write_seq(dsi, ST7703_CMD_SETEXTC, 0xF1, 0x12, 0x83);
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dsi_dcs_write_seq(dsi, ST7703_CMD_SETMIPI,
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0x33, /* VC_main = 0, Lane_Number = 3 (4 lanes) */
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0x81, /* DSI_LDO_SEL = 1.7V, RTERM = 90 Ohm */
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0x05, /* IHSRX = x6 (Low High Speed driving ability) */
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0xF9, /* TX_CLK_SEL = fDSICLK/16 */
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0x0E, /* HFP_OSC (min. HFP number in DSI mode) */
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0x0E, /* HBP_OSC (min. HBP number in DSI mode) */
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/* The rest is undocumented in ST7703 datasheet */
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0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x44, 0x25, 0x00, 0x91, 0x0a, 0x00, 0x00, 0x02,
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0x4F, 0x11, 0x00, 0x00, 0x37);
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dsi_dcs_write_seq(dsi, ST7703_CMD_SETPOWER_EXT,
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0x25, /* PCCS = 2, ECP_DC_DIV = 1/4 HSYNC */
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0x22, /* DT = 15ms XDK_ECP = x2 */
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0x20, /* PFM_DC_DIV = /1 */
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0x03 /* ECP_SYNC_EN = 1, VGX_SYNC_EN = 1 */);
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/* RGB I/F porch timing */
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dsi_dcs_write_seq(dsi, ST7703_CMD_SETRGBIF,
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0x10, /* VBP_RGB_GEN */
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0x10, /* VFP_RGB_GEN */
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0x05, /* DE_BP_RGB_GEN */
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0x05, /* DE_FP_RGB_GEN */
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/* The rest is undocumented in ST7703 datasheet */
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0x03, 0xFF,
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0x00, 0x00,
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0x00, 0x00);
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/* Source driving settings. */
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dsi_dcs_write_seq(dsi, ST7703_CMD_SETSCR,
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0x73, /* N_POPON */
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0x73, /* N_NOPON */
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0x50, /* I_POPON */
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0x50, /* I_NOPON */
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0x00, /* SCR[31,24] */
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0xC0, /* SCR[23,16] */
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0x08, /* SCR[15,8] */
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0x70, /* SCR[7,0] */
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0x00 /* Undocumented */);
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/* NVDDD_SEL = -1.8V, VDDD_SEL = out of range (possibly 1.9V?) */
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dsi_dcs_write_seq(dsi, ST7703_CMD_SETVDC, 0x4E);
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/*
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* SS_PANEL = 1 (reverse scan), GS_PANEL = 0 (normal scan)
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* REV_PANEL = 1 (normally black panel), BGR_PANEL = 1 (BGR)
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*/
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dsi_dcs_write_seq(dsi, ST7703_CMD_SETPANEL, 0x0B);
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/* Zig-Zag Type C column inversion. */
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dsi_dcs_write_seq(dsi, ST7703_CMD_SETCYC, 0x80);
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/* Set display resolution. */
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dsi_dcs_write_seq(dsi, ST7703_CMD_SETDISP,
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0xF0, /* NL = 240 */
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0x12, /* RES_V_LSB = 0, BLK_CON = VSSD,
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* RESO_SEL = 720RGB
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*/
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0xF0 /* WHITE_GND_EN = 1 (GND),
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* WHITE_FRAME_SEL = 7 frames,
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* ISC = 0 frames
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*/);
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dsi_dcs_write_seq(dsi, ST7703_CMD_SETEQ,
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0x00, /* PNOEQ */
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0x00, /* NNOEQ */
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0x0B, /* PEQGND */
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0x0B, /* NEQGND */
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0x10, /* PEQVCI */
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0x10, /* NEQVCI */
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0x00, /* PEQVCI1 */
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0x00, /* NEQVCI1 */
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0x00, /* reserved */
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0x00, /* reserved */
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0xFF, /* reserved */
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0x00, /* reserved */
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0xC0, /* ESD_DET_DATA_WHITE = 1, ESD_WHITE_EN = 1 */
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0x10 /* SLPIN_OPTION = 1 (no need vsync after sleep-in)
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* VEDIO_NO_CHECK_EN = 0
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* ESD_WHITE_GND_EN = 0
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* ESD_DET_TIME_SEL = 0 frames
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*/);
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/* Undocumented command. */
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dsi_dcs_write_seq(dsi, ST7703_CMD_UNKNOWN_C6, 0x01, 0x00, 0xFF, 0xFF, 0x00);
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dsi_dcs_write_seq(dsi, ST7703_CMD_SETPOWER,
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0x74, /* VBTHS, VBTLS: VGH = 17V, VBL = -11V */
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0x00, /* FBOFF_VGH = 0, FBOFF_VGL = 0 */
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0x32, /* VRP */
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0x32, /* VRN */
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0x77, /* reserved */
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0xF1, /* APS = 1 (small),
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* VGL_DET_EN = 1, VGH_DET_EN = 1,
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* VGL_TURBO = 1, VGH_TURBO = 1
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*/
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0xFF, /* VGH1_L_DIV, VGL1_L_DIV (1.5MHz) */
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0xFF, /* VGH1_R_DIV, VGL1_R_DIV (1.5MHz) */
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0xCC, /* VGH2_L_DIV, VGL2_L_DIV (2.6MHz) */
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0xCC, /* VGH2_R_DIV, VGL2_R_DIV (2.6MHz) */
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0x77, /* VGH3_L_DIV, VGL3_L_DIV (4.5MHz) */
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0x77 /* VGH3_R_DIV, VGL3_R_DIV (4.5MHz) */);
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/* Reference voltage. */
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dsi_dcs_write_seq(dsi, ST7703_CMD_SETBGP,
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0x07, /* VREF_SEL = 4.2V */
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0x07 /* NVREF_SEL = 4.2V */);
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msleep(20);
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dsi_dcs_write_seq(dsi, ST7703_CMD_SETVCOM,
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0x2C, /* VCOMDC_F = -0.67V */
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0x2C /* VCOMDC_B = -0.67V */);
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/* Undocumented command. */
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dsi_dcs_write_seq(dsi, ST7703_CMD_UNKNOWN_BF, 0x02, 0x11, 0x00);
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/* This command is to set forward GIP timing. */
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dsi_dcs_write_seq(dsi, ST7703_CMD_SETGIP1,
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0x82, 0x10, 0x06, 0x05, 0xA2, 0x0A, 0xA5, 0x12,
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0x31, 0x23, 0x37, 0x83, 0x04, 0xBC, 0x27, 0x38,
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0x0C, 0x00, 0x03, 0x00, 0x00, 0x00, 0x0C, 0x00,
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0x03, 0x00, 0x00, 0x00, 0x75, 0x75, 0x31, 0x88,
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0x88, 0x88, 0x88, 0x88, 0x88, 0x13, 0x88, 0x64,
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0x64, 0x20, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88,
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0x02, 0x88, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00);
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/* This command is to set backward GIP timing. */
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dsi_dcs_write_seq(dsi, ST7703_CMD_SETGIP2,
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0x02, 0x21, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x02, 0x46, 0x02, 0x88,
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0x88, 0x88, 0x88, 0x88, 0x88, 0x64, 0x88, 0x13,
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0x57, 0x13, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88,
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0x75, 0x88, 0x23, 0x14, 0x00, 0x00, 0x02, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x0A,
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0xA5, 0x00, 0x00, 0x00, 0x00);
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/* Adjust the gamma characteristics of the panel. */
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dsi_dcs_write_seq(dsi, ST7703_CMD_SETGAMMA,
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0x00, 0x09, 0x0D, 0x23, 0x27, 0x3C, 0x41, 0x35,
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0x07, 0x0D, 0x0E, 0x12, 0x13, 0x10, 0x12, 0x12,
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0x18, 0x00, 0x09, 0x0D, 0x23, 0x27, 0x3C, 0x41,
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0x35, 0x07, 0x0D, 0x0E, 0x12, 0x13, 0x10, 0x12,
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0x12, 0x18);
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return 0;
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}
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static const struct drm_display_mode xbd599_mode = {
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.hdisplay = 720,
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.hsync_start = 720 + 40,
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.hsync_end = 720 + 40 + 40,
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.htotal = 720 + 40 + 40 + 40,
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.vdisplay = 1440,
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.vsync_start = 1440 + 18,
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.vsync_end = 1440 + 18 + 10,
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.vtotal = 1440 + 18 + 10 + 17,
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.clock = 69000,
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.flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
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.width_mm = 68,
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.height_mm = 136,
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};
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static const struct st7703_panel_desc xbd599_desc = {
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.mode = &xbd599_mode,
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.lanes = 4,
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.mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE,
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.format = MIPI_DSI_FMT_RGB888,
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.init_sequence = xbd599_init_sequence,
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};
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static int st7703_enable(struct drm_panel *panel)
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{
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struct st7703 *ctx = panel_to_st7703(panel);
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struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
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int ret;
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ret = ctx->desc->init_sequence(ctx);
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if (ret < 0) {
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dev_err(ctx->dev, "Panel init sequence failed: %d\n", ret);
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return ret;
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}
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msleep(20);
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ret = mipi_dsi_dcs_exit_sleep_mode(dsi);
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if (ret < 0) {
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dev_err(ctx->dev, "Failed to exit sleep mode: %d\n", ret);
|
|
return ret;
|
|
}
|
|
|
|
/* Panel is operational 120 msec after reset */
|
|
msleep(60);
|
|
|
|
ret = mipi_dsi_dcs_set_display_on(dsi);
|
|
if (ret)
|
|
return ret;
|
|
|
|
dev_dbg(ctx->dev, "Panel init sequence done\n");
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int st7703_disable(struct drm_panel *panel)
|
|
{
|
|
struct st7703 *ctx = panel_to_st7703(panel);
|
|
struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
|
|
int ret;
|
|
|
|
ret = mipi_dsi_dcs_set_display_off(dsi);
|
|
if (ret < 0)
|
|
dev_err(ctx->dev, "Failed to turn off the display: %d\n", ret);
|
|
|
|
ret = mipi_dsi_dcs_enter_sleep_mode(dsi);
|
|
if (ret < 0)
|
|
dev_err(ctx->dev, "Failed to enter sleep mode: %d\n", ret);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int st7703_unprepare(struct drm_panel *panel)
|
|
{
|
|
struct st7703 *ctx = panel_to_st7703(panel);
|
|
|
|
if (!ctx->prepared)
|
|
return 0;
|
|
|
|
gpiod_set_value_cansleep(ctx->reset_gpio, 1);
|
|
regulator_disable(ctx->iovcc);
|
|
regulator_disable(ctx->vcc);
|
|
ctx->prepared = false;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int st7703_prepare(struct drm_panel *panel)
|
|
{
|
|
struct st7703 *ctx = panel_to_st7703(panel);
|
|
int ret;
|
|
|
|
if (ctx->prepared)
|
|
return 0;
|
|
|
|
dev_dbg(ctx->dev, "Resetting the panel\n");
|
|
ret = regulator_enable(ctx->vcc);
|
|
if (ret < 0) {
|
|
dev_err(ctx->dev, "Failed to enable vcc supply: %d\n", ret);
|
|
return ret;
|
|
}
|
|
ret = regulator_enable(ctx->iovcc);
|
|
if (ret < 0) {
|
|
dev_err(ctx->dev, "Failed to enable iovcc supply: %d\n", ret);
|
|
goto disable_vcc;
|
|
}
|
|
|
|
gpiod_set_value_cansleep(ctx->reset_gpio, 1);
|
|
usleep_range(20, 40);
|
|
gpiod_set_value_cansleep(ctx->reset_gpio, 0);
|
|
msleep(20);
|
|
|
|
ctx->prepared = true;
|
|
|
|
return 0;
|
|
|
|
disable_vcc:
|
|
regulator_disable(ctx->vcc);
|
|
return ret;
|
|
}
|
|
|
|
static const u32 mantix_bus_formats[] = {
|
|
MEDIA_BUS_FMT_RGB888_1X24,
|
|
};
|
|
|
|
static int st7703_get_modes(struct drm_panel *panel,
|
|
struct drm_connector *connector)
|
|
{
|
|
struct st7703 *ctx = panel_to_st7703(panel);
|
|
struct drm_display_mode *mode;
|
|
|
|
mode = drm_mode_duplicate(connector->dev, ctx->desc->mode);
|
|
if (!mode) {
|
|
dev_err(ctx->dev, "Failed to add mode %ux%u@%u\n",
|
|
ctx->desc->mode->hdisplay, ctx->desc->mode->vdisplay,
|
|
drm_mode_vrefresh(ctx->desc->mode));
|
|
return -ENOMEM;
|
|
}
|
|
|
|
drm_mode_set_name(mode);
|
|
|
|
mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
|
|
connector->display_info.width_mm = mode->width_mm;
|
|
connector->display_info.height_mm = mode->height_mm;
|
|
drm_mode_probed_add(connector, mode);
|
|
|
|
drm_display_info_set_bus_formats(&connector->display_info,
|
|
mantix_bus_formats,
|
|
ARRAY_SIZE(mantix_bus_formats));
|
|
|
|
return 1;
|
|
}
|
|
|
|
static const struct drm_panel_funcs st7703_drm_funcs = {
|
|
.disable = st7703_disable,
|
|
.unprepare = st7703_unprepare,
|
|
.prepare = st7703_prepare,
|
|
.enable = st7703_enable,
|
|
.get_modes = st7703_get_modes,
|
|
};
|
|
|
|
static int allpixelson_set(void *data, u64 val)
|
|
{
|
|
struct st7703 *ctx = data;
|
|
struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
|
|
|
|
dev_dbg(ctx->dev, "Setting all pixels on\n");
|
|
dsi_generic_write_seq(dsi, ST7703_CMD_ALL_PIXEL_ON);
|
|
msleep(val * 1000);
|
|
/* Reset the panel to get video back */
|
|
drm_panel_disable(&ctx->panel);
|
|
drm_panel_unprepare(&ctx->panel);
|
|
drm_panel_prepare(&ctx->panel);
|
|
drm_panel_enable(&ctx->panel);
|
|
|
|
return 0;
|
|
}
|
|
|
|
DEFINE_SIMPLE_ATTRIBUTE(allpixelson_fops, NULL,
|
|
allpixelson_set, "%llu\n");
|
|
|
|
static void st7703_debugfs_init(struct st7703 *ctx)
|
|
{
|
|
ctx->debugfs = debugfs_create_dir(DRV_NAME, NULL);
|
|
|
|
debugfs_create_file("allpixelson", 0600, ctx->debugfs, ctx,
|
|
&allpixelson_fops);
|
|
}
|
|
|
|
static void st7703_debugfs_remove(struct st7703 *ctx)
|
|
{
|
|
debugfs_remove_recursive(ctx->debugfs);
|
|
ctx->debugfs = NULL;
|
|
}
|
|
|
|
static int st7703_probe(struct mipi_dsi_device *dsi)
|
|
{
|
|
struct device *dev = &dsi->dev;
|
|
struct st7703 *ctx;
|
|
int ret;
|
|
|
|
ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
|
|
if (!ctx)
|
|
return -ENOMEM;
|
|
|
|
ctx->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
|
|
if (IS_ERR(ctx->reset_gpio))
|
|
return dev_err_probe(dev, PTR_ERR(ctx->reset_gpio), "Failed to get reset gpio\n");
|
|
|
|
mipi_dsi_set_drvdata(dsi, ctx);
|
|
|
|
ctx->dev = dev;
|
|
ctx->desc = of_device_get_match_data(dev);
|
|
|
|
dsi->mode_flags = ctx->desc->mode_flags;
|
|
dsi->format = ctx->desc->format;
|
|
dsi->lanes = ctx->desc->lanes;
|
|
|
|
ctx->vcc = devm_regulator_get(dev, "vcc");
|
|
if (IS_ERR(ctx->vcc))
|
|
return dev_err_probe(dev, PTR_ERR(ctx->vcc), "Failed to request vcc regulator\n");
|
|
|
|
ctx->iovcc = devm_regulator_get(dev, "iovcc");
|
|
if (IS_ERR(ctx->iovcc))
|
|
return dev_err_probe(dev, PTR_ERR(ctx->iovcc),
|
|
"Failed to request iovcc regulator\n");
|
|
|
|
drm_panel_init(&ctx->panel, dev, &st7703_drm_funcs,
|
|
DRM_MODE_CONNECTOR_DSI);
|
|
|
|
ret = drm_panel_of_backlight(&ctx->panel);
|
|
if (ret)
|
|
return ret;
|
|
|
|
drm_panel_add(&ctx->panel);
|
|
|
|
ret = mipi_dsi_attach(dsi);
|
|
if (ret < 0) {
|
|
dev_err(dev, "mipi_dsi_attach failed (%d). Is host ready?\n", ret);
|
|
drm_panel_remove(&ctx->panel);
|
|
return ret;
|
|
}
|
|
|
|
dev_info(dev, "%ux%u@%u %ubpp dsi %udl - ready\n",
|
|
ctx->desc->mode->hdisplay, ctx->desc->mode->vdisplay,
|
|
drm_mode_vrefresh(ctx->desc->mode),
|
|
mipi_dsi_pixel_format_to_bpp(dsi->format), dsi->lanes);
|
|
|
|
st7703_debugfs_init(ctx);
|
|
return 0;
|
|
}
|
|
|
|
static void st7703_shutdown(struct mipi_dsi_device *dsi)
|
|
{
|
|
struct st7703 *ctx = mipi_dsi_get_drvdata(dsi);
|
|
int ret;
|
|
|
|
ret = drm_panel_unprepare(&ctx->panel);
|
|
if (ret < 0)
|
|
dev_err(&dsi->dev, "Failed to unprepare panel: %d\n", ret);
|
|
|
|
ret = drm_panel_disable(&ctx->panel);
|
|
if (ret < 0)
|
|
dev_err(&dsi->dev, "Failed to disable panel: %d\n", ret);
|
|
}
|
|
|
|
static void st7703_remove(struct mipi_dsi_device *dsi)
|
|
{
|
|
struct st7703 *ctx = mipi_dsi_get_drvdata(dsi);
|
|
int ret;
|
|
|
|
st7703_shutdown(dsi);
|
|
|
|
ret = mipi_dsi_detach(dsi);
|
|
if (ret < 0)
|
|
dev_err(&dsi->dev, "Failed to detach from DSI host: %d\n", ret);
|
|
|
|
drm_panel_remove(&ctx->panel);
|
|
|
|
st7703_debugfs_remove(ctx);
|
|
}
|
|
|
|
static const struct of_device_id st7703_of_match[] = {
|
|
{ .compatible = "rocktech,jh057n00900", .data = &jh057n00900_panel_desc },
|
|
{ .compatible = "xingbangda,xbd599", .data = &xbd599_desc },
|
|
{ /* sentinel */ }
|
|
};
|
|
MODULE_DEVICE_TABLE(of, st7703_of_match);
|
|
|
|
static struct mipi_dsi_driver st7703_driver = {
|
|
.probe = st7703_probe,
|
|
.remove = st7703_remove,
|
|
.shutdown = st7703_shutdown,
|
|
.driver = {
|
|
.name = DRV_NAME,
|
|
.of_match_table = st7703_of_match,
|
|
},
|
|
};
|
|
module_mipi_dsi_driver(st7703_driver);
|
|
|
|
MODULE_AUTHOR("Guido Günther <agx@sigxcpu.org>");
|
|
MODULE_DESCRIPTION("DRM driver for Sitronix ST7703 based MIPI DSI panels");
|
|
MODULE_LICENSE("GPL v2");
|