133 lines
3.1 KiB
C
133 lines
3.1 KiB
C
// SPDX-License-Identifier: MIT
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/*
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* Copyright © 2022 Intel Corporation
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*/
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#include "intel_ggtt_gmch.h"
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#include <drm/intel-gtt.h>
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#include <drm/i915_drm.h>
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#include <linux/agp_backend.h>
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#include "i915_drv.h"
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#include "i915_utils.h"
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#include "intel_gtt.h"
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#include "intel_gt_regs.h"
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#include "intel_gt.h"
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static void gmch_ggtt_insert_page(struct i915_address_space *vm,
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dma_addr_t addr,
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u64 offset,
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enum i915_cache_level cache_level,
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u32 unused)
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{
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unsigned int flags = (cache_level == I915_CACHE_NONE) ?
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AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY;
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intel_gmch_gtt_insert_page(addr, offset >> PAGE_SHIFT, flags);
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}
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static void gmch_ggtt_insert_entries(struct i915_address_space *vm,
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struct i915_vma_resource *vma_res,
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enum i915_cache_level cache_level,
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u32 unused)
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{
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unsigned int flags = (cache_level == I915_CACHE_NONE) ?
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AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY;
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intel_gmch_gtt_insert_sg_entries(vma_res->bi.pages, vma_res->start >> PAGE_SHIFT,
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flags);
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}
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static void gmch_ggtt_invalidate(struct i915_ggtt *ggtt)
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{
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intel_gmch_gtt_flush();
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}
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static void gmch_ggtt_clear_range(struct i915_address_space *vm,
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u64 start, u64 length)
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{
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intel_gmch_gtt_clear_range(start >> PAGE_SHIFT, length >> PAGE_SHIFT);
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}
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static void gmch_ggtt_remove(struct i915_address_space *vm)
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{
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intel_gmch_remove();
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}
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/*
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* Certain Gen5 chipsets require idling the GPU before unmapping anything from
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* the GTT when VT-d is enabled.
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*/
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static bool needs_idle_maps(struct drm_i915_private *i915)
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{
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/*
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* Query intel_iommu to see if we need the workaround. Presumably that
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* was loaded first.
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*/
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if (!i915_vtd_active(i915))
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return false;
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if (GRAPHICS_VER(i915) == 5 && IS_MOBILE(i915))
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return true;
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return false;
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}
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int intel_ggtt_gmch_probe(struct i915_ggtt *ggtt)
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{
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struct drm_i915_private *i915 = ggtt->vm.i915;
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phys_addr_t gmadr_base;
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int ret;
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ret = intel_gmch_probe(i915->bridge_dev, to_pci_dev(i915->drm.dev), NULL);
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if (!ret) {
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drm_err(&i915->drm, "failed to set up gmch\n");
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return -EIO;
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}
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intel_gmch_gtt_get(&ggtt->vm.total, &gmadr_base, &ggtt->mappable_end);
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ggtt->gmadr =
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(struct resource)DEFINE_RES_MEM(gmadr_base, ggtt->mappable_end);
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ggtt->vm.alloc_pt_dma = alloc_pt_dma;
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ggtt->vm.alloc_scratch_dma = alloc_pt_dma;
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if (needs_idle_maps(i915)) {
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drm_notice(&i915->drm,
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"Flushing DMA requests before IOMMU unmaps; performance may be degraded\n");
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ggtt->do_idle_maps = true;
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}
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ggtt->vm.insert_page = gmch_ggtt_insert_page;
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ggtt->vm.insert_entries = gmch_ggtt_insert_entries;
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ggtt->vm.clear_range = gmch_ggtt_clear_range;
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ggtt->vm.cleanup = gmch_ggtt_remove;
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ggtt->invalidate = gmch_ggtt_invalidate;
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ggtt->vm.vma_ops.bind_vma = intel_ggtt_bind_vma;
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ggtt->vm.vma_ops.unbind_vma = intel_ggtt_unbind_vma;
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if (unlikely(ggtt->do_idle_maps))
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drm_notice(&i915->drm,
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"Applying Ironlake quirks for intel_iommu\n");
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return 0;
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}
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int intel_ggtt_gmch_enable_hw(struct drm_i915_private *i915)
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{
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if (!intel_gmch_enable_gtt())
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return -EIO;
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return 0;
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}
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void intel_ggtt_gmch_flush(void)
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{
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intel_gmch_gtt_flush();
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}
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