259 lines
12 KiB
C
259 lines
12 KiB
C
/* SPDX-License-Identifier: MIT */
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/*
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* Copyright © 2022 Intel Corporation
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*/
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#ifndef __INTEL_ENGINE_REGS__
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#define __INTEL_ENGINE_REGS__
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#include "i915_reg_defs.h"
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#define RING_EXCC(base) _MMIO((base) + 0x28)
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#define RING_TAIL(base) _MMIO((base) + 0x30)
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#define TAIL_ADDR 0x001FFFF8
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#define RING_HEAD(base) _MMIO((base) + 0x34)
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#define HEAD_WRAP_COUNT 0xFFE00000
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#define HEAD_WRAP_ONE 0x00200000
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#define HEAD_ADDR 0x001FFFFC
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#define RING_START(base) _MMIO((base) + 0x38)
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#define RING_CTL(base) _MMIO((base) + 0x3c)
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#define RING_CTL_SIZE(size) ((size) - PAGE_SIZE) /* in bytes -> pages */
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#define RING_NR_PAGES 0x001FF000
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#define RING_REPORT_MASK 0x00000006
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#define RING_REPORT_64K 0x00000002
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#define RING_REPORT_128K 0x00000004
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#define RING_NO_REPORT 0x00000000
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#define RING_VALID_MASK 0x00000001
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#define RING_VALID 0x00000001
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#define RING_INVALID 0x00000000
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#define RING_WAIT_I8XX (1 << 0) /* gen2, PRBx_HEAD */
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#define RING_WAIT (1 << 11) /* gen3+, PRBx_CTL */
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#define RING_WAIT_SEMAPHORE (1 << 10) /* gen6+ */
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#define RING_SYNC_0(base) _MMIO((base) + 0x40)
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#define RING_SYNC_1(base) _MMIO((base) + 0x44)
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#define RING_SYNC_2(base) _MMIO((base) + 0x48)
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#define GEN6_RVSYNC (RING_SYNC_0(RENDER_RING_BASE))
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#define GEN6_RBSYNC (RING_SYNC_1(RENDER_RING_BASE))
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#define GEN6_RVESYNC (RING_SYNC_2(RENDER_RING_BASE))
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#define GEN6_VBSYNC (RING_SYNC_0(GEN6_BSD_RING_BASE))
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#define GEN6_VRSYNC (RING_SYNC_1(GEN6_BSD_RING_BASE))
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#define GEN6_VVESYNC (RING_SYNC_2(GEN6_BSD_RING_BASE))
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#define GEN6_BRSYNC (RING_SYNC_0(BLT_RING_BASE))
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#define GEN6_BVSYNC (RING_SYNC_1(BLT_RING_BASE))
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#define GEN6_BVESYNC (RING_SYNC_2(BLT_RING_BASE))
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#define GEN6_VEBSYNC (RING_SYNC_0(VEBOX_RING_BASE))
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#define GEN6_VERSYNC (RING_SYNC_1(VEBOX_RING_BASE))
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#define GEN6_VEVSYNC (RING_SYNC_2(VEBOX_RING_BASE))
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#define RING_PSMI_CTL(base) _MMIO((base) + 0x50)
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#define GEN8_RC_SEMA_IDLE_MSG_DISABLE REG_BIT(12)
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#define GEN8_FF_DOP_CLOCK_GATE_DISABLE REG_BIT(10)
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#define GEN12_WAIT_FOR_EVENT_POWER_DOWN_DISABLE REG_BIT(7)
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#define GEN6_BSD_GO_INDICATOR REG_BIT(4)
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#define GEN6_BSD_SLEEP_INDICATOR REG_BIT(3)
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#define GEN6_BSD_SLEEP_FLUSH_DISABLE REG_BIT(2)
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#define GEN6_PSMI_SLEEP_MSG_DISABLE REG_BIT(0)
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#define RING_MAX_IDLE(base) _MMIO((base) + 0x54)
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#define PWRCTX_MAXCNT(base) _MMIO((base) + 0x54)
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#define IDLE_TIME_MASK 0xFFFFF
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#define RING_ACTHD_UDW(base) _MMIO((base) + 0x5c)
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#define RING_DMA_FADD_UDW(base) _MMIO((base) + 0x60) /* gen8+ */
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#define RING_IPEIR(base) _MMIO((base) + 0x64)
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#define RING_IPEHR(base) _MMIO((base) + 0x68)
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#define RING_INSTDONE(base) _MMIO((base) + 0x6c)
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#define RING_INSTPS(base) _MMIO((base) + 0x70)
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#define RING_DMA_FADD(base) _MMIO((base) + 0x78)
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#define RING_ACTHD(base) _MMIO((base) + 0x74)
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#define RING_HWS_PGA(base) _MMIO((base) + 0x80)
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#define RING_CMD_BUF_CCTL(base) _MMIO((base) + 0x84)
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#define IPEIR(base) _MMIO((base) + 0x88)
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#define IPEHR(base) _MMIO((base) + 0x8c)
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#define RING_ID(base) _MMIO((base) + 0x8c)
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#define RING_NOPID(base) _MMIO((base) + 0x94)
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#define RING_HWSTAM(base) _MMIO((base) + 0x98)
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#define RING_MI_MODE(base) _MMIO((base) + 0x9c)
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#define ASYNC_FLIP_PERF_DISABLE REG_BIT(14)
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#define MI_FLUSH_ENABLE REG_BIT(12)
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#define TGL_NESTED_BB_EN REG_BIT(12)
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#define MODE_IDLE REG_BIT(9)
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#define STOP_RING REG_BIT(8)
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#define VS_TIMER_DISPATCH REG_BIT(6)
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#define RING_IMR(base) _MMIO((base) + 0xa8)
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#define RING_EIR(base) _MMIO((base) + 0xb0)
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#define RING_EMR(base) _MMIO((base) + 0xb4)
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#define RING_ESR(base) _MMIO((base) + 0xb8)
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#define RING_INSTPM(base) _MMIO((base) + 0xc0)
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#define RING_CMD_CCTL(base) _MMIO((base) + 0xc4)
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#define ACTHD(base) _MMIO((base) + 0xc8)
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#define GEN8_R_PWR_CLK_STATE(base) _MMIO((base) + 0xc8)
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#define GEN8_RPCS_ENABLE (1 << 31)
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#define GEN8_RPCS_S_CNT_ENABLE (1 << 18)
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#define GEN8_RPCS_S_CNT_SHIFT 15
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#define GEN8_RPCS_S_CNT_MASK (0x7 << GEN8_RPCS_S_CNT_SHIFT)
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#define GEN11_RPCS_S_CNT_SHIFT 12
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#define GEN11_RPCS_S_CNT_MASK (0x3f << GEN11_RPCS_S_CNT_SHIFT)
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#define GEN8_RPCS_SS_CNT_ENABLE (1 << 11)
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#define GEN8_RPCS_SS_CNT_SHIFT 8
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#define GEN8_RPCS_SS_CNT_MASK (0x7 << GEN8_RPCS_SS_CNT_SHIFT)
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#define GEN8_RPCS_EU_MAX_SHIFT 4
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#define GEN8_RPCS_EU_MAX_MASK (0xf << GEN8_RPCS_EU_MAX_SHIFT)
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#define GEN8_RPCS_EU_MIN_SHIFT 0
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#define GEN8_RPCS_EU_MIN_MASK (0xf << GEN8_RPCS_EU_MIN_SHIFT)
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#define RING_RESET_CTL(base) _MMIO((base) + 0xd0)
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#define RESET_CTL_CAT_ERROR REG_BIT(2)
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#define RESET_CTL_READY_TO_RESET REG_BIT(1)
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#define RESET_CTL_REQUEST_RESET REG_BIT(0)
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#define DMA_FADD_I8XX(base) _MMIO((base) + 0xd0)
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#define RING_BBSTATE(base) _MMIO((base) + 0x110)
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#define RING_BB_PPGTT (1 << 5)
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#define RING_SBBADDR(base) _MMIO((base) + 0x114) /* hsw+ */
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#define RING_SBBSTATE(base) _MMIO((base) + 0x118) /* hsw+ */
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#define RING_SBBADDR_UDW(base) _MMIO((base) + 0x11c) /* gen8+ */
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#define RING_BBADDR(base) _MMIO((base) + 0x140)
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#define RING_BB_OFFSET(base) _MMIO((base) + 0x158)
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#define RING_BBADDR_UDW(base) _MMIO((base) + 0x168) /* gen8+ */
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#define CCID(base) _MMIO((base) + 0x180)
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#define CCID_EN BIT(0)
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#define CCID_EXTENDED_STATE_RESTORE BIT(2)
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#define CCID_EXTENDED_STATE_SAVE BIT(3)
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#define RING_BB_PER_CTX_PTR(base) _MMIO((base) + 0x1c0) /* gen8+ */
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#define RING_INDIRECT_CTX(base) _MMIO((base) + 0x1c4) /* gen8+ */
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#define RING_INDIRECT_CTX_OFFSET(base) _MMIO((base) + 0x1c8) /* gen8+ */
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#define ECOSKPD(base) _MMIO((base) + 0x1d0)
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#define ECO_CONSTANT_BUFFER_SR_DISABLE REG_BIT(4)
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#define ECO_GATING_CX_ONLY REG_BIT(3)
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#define GEN6_BLITTER_FBC_NOTIFY REG_BIT(3)
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#define ECO_FLIP_DONE REG_BIT(0)
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#define GEN6_BLITTER_LOCK_SHIFT 16
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#define BLIT_CCTL(base) _MMIO((base) + 0x204)
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#define BLIT_CCTL_DST_MOCS_MASK REG_GENMASK(14, 8)
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#define BLIT_CCTL_SRC_MOCS_MASK REG_GENMASK(6, 0)
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#define BLIT_CCTL_MASK (BLIT_CCTL_DST_MOCS_MASK | \
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BLIT_CCTL_SRC_MOCS_MASK)
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#define BLIT_CCTL_MOCS(dst, src) \
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(REG_FIELD_PREP(BLIT_CCTL_DST_MOCS_MASK, (dst) << 1) | \
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REG_FIELD_PREP(BLIT_CCTL_SRC_MOCS_MASK, (src) << 1))
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#define RING_CSCMDOP(base) _MMIO((base) + 0x20c)
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/*
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* CMD_CCTL read/write fields take a MOCS value and _not_ a table index.
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* The lsb of each can be considered a separate enabling bit for encryption.
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* 6:0 == default MOCS value for reads => 6:1 == table index for reads.
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* 13:7 == default MOCS value for writes => 13:8 == table index for writes.
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* 15:14 == Reserved => 31:30 are set to 0.
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*/
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#define CMD_CCTL_WRITE_OVERRIDE_MASK REG_GENMASK(13, 7)
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#define CMD_CCTL_READ_OVERRIDE_MASK REG_GENMASK(6, 0)
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#define CMD_CCTL_MOCS_MASK (CMD_CCTL_WRITE_OVERRIDE_MASK | \
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CMD_CCTL_READ_OVERRIDE_MASK)
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#define CMD_CCTL_MOCS_OVERRIDE(write, read) \
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(REG_FIELD_PREP(CMD_CCTL_WRITE_OVERRIDE_MASK, (write) << 1) | \
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REG_FIELD_PREP(CMD_CCTL_READ_OVERRIDE_MASK, (read) << 1))
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#define RING_PREDICATE_RESULT(base) _MMIO((base) + 0x3b8) /* gen12+ */
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#define MI_PREDICATE_RESULT_2(base) _MMIO((base) + 0x3bc)
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#define LOWER_SLICE_ENABLED (1 << 0)
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#define LOWER_SLICE_DISABLED (0 << 0)
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#define MI_PREDICATE_SRC0(base) _MMIO((base) + 0x400)
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#define MI_PREDICATE_SRC0_UDW(base) _MMIO((base) + 0x400 + 4)
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#define MI_PREDICATE_SRC1(base) _MMIO((base) + 0x408)
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#define MI_PREDICATE_SRC1_UDW(base) _MMIO((base) + 0x408 + 4)
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#define MI_PREDICATE_DATA(base) _MMIO((base) + 0x410)
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#define MI_PREDICATE_RESULT(base) _MMIO((base) + 0x418)
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#define MI_PREDICATE_RESULT_1(base) _MMIO((base) + 0x41c)
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#define RING_PP_DIR_DCLV(base) _MMIO((base) + 0x220)
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#define PP_DIR_DCLV_2G 0xffffffff
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#define RING_PP_DIR_BASE(base) _MMIO((base) + 0x228)
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#define RING_ELSP(base) _MMIO((base) + 0x230)
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#define RING_EXECLIST_STATUS_LO(base) _MMIO((base) + 0x234)
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#define RING_EXECLIST_STATUS_HI(base) _MMIO((base) + 0x234 + 4)
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#define RING_CONTEXT_CONTROL(base) _MMIO((base) + 0x244)
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#define CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT REG_BIT(0)
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#define CTX_CTRL_RS_CTX_ENABLE REG_BIT(1)
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#define CTX_CTRL_ENGINE_CTX_SAVE_INHIBIT REG_BIT(2)
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#define CTX_CTRL_INHIBIT_SYN_CTX_SWITCH REG_BIT(3)
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#define GEN12_CTX_CTRL_OAR_CONTEXT_ENABLE REG_BIT(8)
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#define RING_CTX_SR_CTL(base) _MMIO((base) + 0x244)
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#define RING_SEMA_WAIT_POLL(base) _MMIO((base) + 0x24c)
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#define GEN8_RING_PDP_UDW(base, n) _MMIO((base) + 0x270 + (n) * 8 + 4)
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#define GEN8_RING_PDP_LDW(base, n) _MMIO((base) + 0x270 + (n) * 8)
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#define RING_MODE_GEN7(base) _MMIO((base) + 0x29c)
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#define GFX_RUN_LIST_ENABLE (1 << 15)
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#define GFX_INTERRUPT_STEERING (1 << 14)
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#define GFX_TLB_INVALIDATE_EXPLICIT (1 << 13)
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#define GFX_SURFACE_FAULT_ENABLE (1 << 12)
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#define GFX_REPLAY_MODE (1 << 11)
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#define GFX_PSMI_GRANULARITY (1 << 10)
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#define GEN12_GFX_PREFETCH_DISABLE REG_BIT(10)
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#define GFX_PPGTT_ENABLE (1 << 9)
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#define GEN8_GFX_PPGTT_48B (1 << 7)
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#define GFX_FORWARD_VBLANK_MASK (3 << 5)
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#define GFX_FORWARD_VBLANK_NEVER (0 << 5)
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#define GFX_FORWARD_VBLANK_ALWAYS (1 << 5)
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#define GFX_FORWARD_VBLANK_COND (2 << 5)
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#define GEN11_GFX_DISABLE_LEGACY_MODE (1 << 3)
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#define RING_TIMESTAMP(base) _MMIO((base) + 0x358)
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#define RING_TIMESTAMP_UDW(base) _MMIO((base) + 0x358 + 4)
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#define RING_CONTEXT_STATUS_PTR(base) _MMIO((base) + 0x3a0)
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#define RING_CTX_TIMESTAMP(base) _MMIO((base) + 0x3a8) /* gen8+ */
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#define RING_PREDICATE_RESULT(base) _MMIO((base) + 0x3b8)
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#define RING_FORCE_TO_NONPRIV(base, i) _MMIO(((base) + 0x4D0) + (i) * 4)
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#define RING_FORCE_TO_NONPRIV_DENY REG_BIT(30)
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#define RING_FORCE_TO_NONPRIV_ADDRESS_MASK REG_GENMASK(25, 2)
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#define RING_FORCE_TO_NONPRIV_ACCESS_RW (0 << 28) /* CFL+ & Gen11+ */
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#define RING_FORCE_TO_NONPRIV_ACCESS_RD (1 << 28)
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#define RING_FORCE_TO_NONPRIV_ACCESS_WR (2 << 28)
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#define RING_FORCE_TO_NONPRIV_ACCESS_INVALID (3 << 28)
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#define RING_FORCE_TO_NONPRIV_ACCESS_MASK (3 << 28)
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#define RING_FORCE_TO_NONPRIV_RANGE_1 (0 << 0) /* CFL+ & Gen11+ */
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#define RING_FORCE_TO_NONPRIV_RANGE_4 (1 << 0)
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#define RING_FORCE_TO_NONPRIV_RANGE_16 (2 << 0)
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#define RING_FORCE_TO_NONPRIV_RANGE_64 (3 << 0)
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#define RING_FORCE_TO_NONPRIV_RANGE_MASK (3 << 0)
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#define RING_FORCE_TO_NONPRIV_MASK_VALID \
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(RING_FORCE_TO_NONPRIV_RANGE_MASK | \
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RING_FORCE_TO_NONPRIV_ACCESS_MASK | \
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RING_FORCE_TO_NONPRIV_DENY)
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#define RING_MAX_NONPRIV_SLOTS 12
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#define RING_EXECLIST_SQ_CONTENTS(base) _MMIO((base) + 0x510)
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#define RING_PP_DIR_BASE_READ(base) _MMIO((base) + 0x518)
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#define RING_EXECLIST_CONTROL(base) _MMIO((base) + 0x550)
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#define EL_CTRL_LOAD REG_BIT(0)
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/* There are 16 64-bit CS General Purpose Registers per-engine on Gen8+ */
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#define GEN8_RING_CS_GPR(base, n) _MMIO((base) + 0x600 + (n) * 8)
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#define GEN8_RING_CS_GPR_UDW(base, n) _MMIO((base) + 0x600 + (n) * 8 + 4)
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#define GEN11_VCS_SFC_FORCED_LOCK(base) _MMIO((base) + 0x88c)
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#define GEN11_VCS_SFC_FORCED_LOCK_BIT (1 << 0)
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#define GEN11_VCS_SFC_LOCK_STATUS(base) _MMIO((base) + 0x890)
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#define GEN11_VCS_SFC_USAGE_BIT (1 << 0)
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#define GEN11_VCS_SFC_LOCK_ACK_BIT (1 << 1)
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#define GEN11_VECS_SFC_FORCED_LOCK(base) _MMIO((base) + 0x201c)
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#define GEN11_VECS_SFC_FORCED_LOCK_BIT (1 << 0)
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#define GEN11_VECS_SFC_LOCK_ACK(base) _MMIO((base) + 0x2018)
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#define GEN11_VECS_SFC_LOCK_ACK_BIT (1 << 0)
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#define GEN11_VECS_SFC_USAGE(base) _MMIO((base) + 0x2014)
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#define GEN11_VECS_SFC_USAGE_BIT (1 << 0)
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#define RING_HWS_PGA_GEN6(base) _MMIO((base) + 0x2080)
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#define GEN12_HCP_SFC_LOCK_STATUS(base) _MMIO((base) + 0x2914)
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#define GEN12_HCP_SFC_LOCK_ACK_BIT REG_BIT(1)
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#define GEN12_HCP_SFC_USAGE_BIT REG_BIT(0)
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#define VDBOX_CGCTL3F10(base) _MMIO((base) + 0x3f10)
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#define IECPUNIT_CLKGATE_DIS REG_BIT(22)
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#define VDBOX_CGCTL3F18(base) _MMIO((base) + 0x3f18)
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#define ALNUNIT_CLKGATE_DIS REG_BIT(13)
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#endif /* __INTEL_ENGINE_REGS__ */
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