515 lines
12 KiB
C
515 lines
12 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2019-2020 NVIDIA Corporation. All rights reserved.
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*/
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#include <linux/clocksource.h>
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#include <linux/module.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/pm.h>
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#include <linux/watchdog.h>
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/* shared registers */
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#define TKETSC0 0x000
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#define TKETSC1 0x004
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#define TKEUSEC 0x008
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#define TKEOSC 0x00c
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#define TKEIE(x) (0x100 + ((x) * 4))
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#define TKEIE_WDT_MASK(x, y) ((y) << (16 + 4 * (x)))
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/* timer registers */
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#define TMRCR 0x000
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#define TMRCR_ENABLE BIT(31)
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#define TMRCR_PERIODIC BIT(30)
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#define TMRCR_PTV(x) ((x) & 0x0fffffff)
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#define TMRSR 0x004
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#define TMRSR_INTR_CLR BIT(30)
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#define TMRCSSR 0x008
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#define TMRCSSR_SRC_USEC (0 << 0)
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/* watchdog registers */
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#define WDTCR 0x000
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#define WDTCR_SYSTEM_POR_RESET_ENABLE BIT(16)
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#define WDTCR_SYSTEM_DEBUG_RESET_ENABLE BIT(15)
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#define WDTCR_REMOTE_INT_ENABLE BIT(14)
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#define WDTCR_LOCAL_FIQ_ENABLE BIT(13)
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#define WDTCR_LOCAL_INT_ENABLE BIT(12)
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#define WDTCR_PERIOD_MASK (0xff << 4)
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#define WDTCR_PERIOD(x) (((x) & 0xff) << 4)
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#define WDTCR_TIMER_SOURCE_MASK 0xf
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#define WDTCR_TIMER_SOURCE(x) ((x) & 0xf)
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#define WDTCMDR 0x008
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#define WDTCMDR_DISABLE_COUNTER BIT(1)
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#define WDTCMDR_START_COUNTER BIT(0)
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#define WDTUR 0x00c
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#define WDTUR_UNLOCK_PATTERN 0x0000c45a
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struct tegra186_timer_soc {
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unsigned int num_timers;
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unsigned int num_wdts;
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};
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struct tegra186_tmr {
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struct tegra186_timer *parent;
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void __iomem *regs;
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unsigned int index;
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unsigned int hwirq;
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};
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struct tegra186_wdt {
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struct watchdog_device base;
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void __iomem *regs;
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unsigned int index;
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bool locked;
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struct tegra186_tmr *tmr;
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};
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static inline struct tegra186_wdt *to_tegra186_wdt(struct watchdog_device *wdd)
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{
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return container_of(wdd, struct tegra186_wdt, base);
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}
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struct tegra186_timer {
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const struct tegra186_timer_soc *soc;
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struct device *dev;
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void __iomem *regs;
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struct tegra186_wdt *wdt;
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struct clocksource usec;
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struct clocksource tsc;
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struct clocksource osc;
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};
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static void tmr_writel(struct tegra186_tmr *tmr, u32 value, unsigned int offset)
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{
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writel_relaxed(value, tmr->regs + offset);
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}
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static void wdt_writel(struct tegra186_wdt *wdt, u32 value, unsigned int offset)
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{
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writel_relaxed(value, wdt->regs + offset);
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}
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static u32 wdt_readl(struct tegra186_wdt *wdt, unsigned int offset)
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{
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return readl_relaxed(wdt->regs + offset);
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}
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static struct tegra186_tmr *tegra186_tmr_create(struct tegra186_timer *tegra,
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unsigned int index)
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{
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unsigned int offset = 0x10000 + index * 0x10000;
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struct tegra186_tmr *tmr;
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tmr = devm_kzalloc(tegra->dev, sizeof(*tmr), GFP_KERNEL);
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if (!tmr)
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return ERR_PTR(-ENOMEM);
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tmr->parent = tegra;
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tmr->regs = tegra->regs + offset;
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tmr->index = index;
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tmr->hwirq = 0;
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return tmr;
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}
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static const struct watchdog_info tegra186_wdt_info = {
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.options = WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE | WDIOF_KEEPALIVEPING,
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.identity = "NVIDIA Tegra186 WDT",
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};
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static void tegra186_wdt_disable(struct tegra186_wdt *wdt)
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{
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/* unlock and disable the watchdog */
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wdt_writel(wdt, WDTUR_UNLOCK_PATTERN, WDTUR);
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wdt_writel(wdt, WDTCMDR_DISABLE_COUNTER, WDTCMDR);
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/* disable timer */
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tmr_writel(wdt->tmr, 0, TMRCR);
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}
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static void tegra186_wdt_enable(struct tegra186_wdt *wdt)
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{
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struct tegra186_timer *tegra = wdt->tmr->parent;
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u32 value;
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/* unmask hardware IRQ, this may have been lost across powergate */
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value = TKEIE_WDT_MASK(wdt->index, 1);
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writel(value, tegra->regs + TKEIE(wdt->tmr->hwirq));
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/* clear interrupt */
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tmr_writel(wdt->tmr, TMRSR_INTR_CLR, TMRSR);
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/* select microsecond source */
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tmr_writel(wdt->tmr, TMRCSSR_SRC_USEC, TMRCSSR);
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/* configure timer (system reset happens on the fifth expiration) */
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value = TMRCR_PTV(wdt->base.timeout * USEC_PER_SEC / 5) |
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TMRCR_PERIODIC | TMRCR_ENABLE;
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tmr_writel(wdt->tmr, value, TMRCR);
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if (!wdt->locked) {
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value = wdt_readl(wdt, WDTCR);
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/* select the proper timer source */
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value &= ~WDTCR_TIMER_SOURCE_MASK;
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value |= WDTCR_TIMER_SOURCE(wdt->tmr->index);
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/* single timer period since that's already configured */
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value &= ~WDTCR_PERIOD_MASK;
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value |= WDTCR_PERIOD(1);
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/* enable local interrupt for WDT petting */
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value |= WDTCR_LOCAL_INT_ENABLE;
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/* enable local FIQ and remote interrupt for debug dump */
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if (0)
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value |= WDTCR_REMOTE_INT_ENABLE |
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WDTCR_LOCAL_FIQ_ENABLE;
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/* enable system debug reset (doesn't properly reboot) */
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if (0)
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value |= WDTCR_SYSTEM_DEBUG_RESET_ENABLE;
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/* enable system POR reset */
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value |= WDTCR_SYSTEM_POR_RESET_ENABLE;
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wdt_writel(wdt, value, WDTCR);
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}
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wdt_writel(wdt, WDTCMDR_START_COUNTER, WDTCMDR);
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}
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static int tegra186_wdt_start(struct watchdog_device *wdd)
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{
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struct tegra186_wdt *wdt = to_tegra186_wdt(wdd);
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tegra186_wdt_enable(wdt);
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return 0;
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}
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static int tegra186_wdt_stop(struct watchdog_device *wdd)
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{
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struct tegra186_wdt *wdt = to_tegra186_wdt(wdd);
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tegra186_wdt_disable(wdt);
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return 0;
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}
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static int tegra186_wdt_ping(struct watchdog_device *wdd)
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{
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struct tegra186_wdt *wdt = to_tegra186_wdt(wdd);
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tegra186_wdt_disable(wdt);
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tegra186_wdt_enable(wdt);
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return 0;
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}
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static int tegra186_wdt_set_timeout(struct watchdog_device *wdd,
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unsigned int timeout)
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{
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struct tegra186_wdt *wdt = to_tegra186_wdt(wdd);
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if (watchdog_active(&wdt->base))
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tegra186_wdt_disable(wdt);
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wdt->base.timeout = timeout;
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if (watchdog_active(&wdt->base))
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tegra186_wdt_enable(wdt);
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return 0;
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}
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static const struct watchdog_ops tegra186_wdt_ops = {
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.owner = THIS_MODULE,
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.start = tegra186_wdt_start,
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.stop = tegra186_wdt_stop,
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.ping = tegra186_wdt_ping,
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.set_timeout = tegra186_wdt_set_timeout,
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};
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static struct tegra186_wdt *tegra186_wdt_create(struct tegra186_timer *tegra,
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unsigned int index)
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{
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unsigned int offset = 0x10000, source;
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struct tegra186_wdt *wdt;
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u32 value;
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int err;
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offset += tegra->soc->num_timers * 0x10000 + index * 0x10000;
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wdt = devm_kzalloc(tegra->dev, sizeof(*wdt), GFP_KERNEL);
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if (!wdt)
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return ERR_PTR(-ENOMEM);
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wdt->regs = tegra->regs + offset;
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wdt->index = index;
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/* read the watchdog configuration since it might be locked down */
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value = wdt_readl(wdt, WDTCR);
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if (value & WDTCR_LOCAL_INT_ENABLE)
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wdt->locked = true;
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source = value & WDTCR_TIMER_SOURCE_MASK;
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wdt->tmr = tegra186_tmr_create(tegra, source);
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if (IS_ERR(wdt->tmr))
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return ERR_CAST(wdt->tmr);
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wdt->base.info = &tegra186_wdt_info;
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wdt->base.ops = &tegra186_wdt_ops;
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wdt->base.min_timeout = 1;
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wdt->base.max_timeout = 255;
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wdt->base.parent = tegra->dev;
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err = watchdog_init_timeout(&wdt->base, 5, tegra->dev);
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if (err < 0) {
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dev_err(tegra->dev, "failed to initialize timeout: %d\n", err);
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return ERR_PTR(err);
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}
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err = devm_watchdog_register_device(tegra->dev, &wdt->base);
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if (err < 0) {
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dev_err(tegra->dev, "failed to register WDT: %d\n", err);
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return ERR_PTR(err);
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}
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return wdt;
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}
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static u64 tegra186_timer_tsc_read(struct clocksource *cs)
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{
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struct tegra186_timer *tegra = container_of(cs, struct tegra186_timer,
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tsc);
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u32 hi, lo, ss;
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hi = readl_relaxed(tegra->regs + TKETSC1);
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/*
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* The 56-bit value of the TSC is spread across two registers that are
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* not synchronized. In order to read them atomically, ensure that the
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* high 24 bits match before and after reading the low 32 bits.
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*/
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do {
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/* snapshot the high 24 bits */
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ss = hi;
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lo = readl_relaxed(tegra->regs + TKETSC0);
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hi = readl_relaxed(tegra->regs + TKETSC1);
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} while (hi != ss);
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return (u64)hi << 32 | lo;
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}
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static int tegra186_timer_tsc_init(struct tegra186_timer *tegra)
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{
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tegra->tsc.name = "tsc";
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tegra->tsc.rating = 300;
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tegra->tsc.read = tegra186_timer_tsc_read;
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tegra->tsc.mask = CLOCKSOURCE_MASK(56);
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tegra->tsc.flags = CLOCK_SOURCE_IS_CONTINUOUS;
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return clocksource_register_hz(&tegra->tsc, 31250000);
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}
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static u64 tegra186_timer_osc_read(struct clocksource *cs)
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{
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struct tegra186_timer *tegra = container_of(cs, struct tegra186_timer,
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osc);
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return readl_relaxed(tegra->regs + TKEOSC);
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}
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static int tegra186_timer_osc_init(struct tegra186_timer *tegra)
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{
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tegra->osc.name = "osc";
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tegra->osc.rating = 300;
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tegra->osc.read = tegra186_timer_osc_read;
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tegra->osc.mask = CLOCKSOURCE_MASK(32);
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tegra->osc.flags = CLOCK_SOURCE_IS_CONTINUOUS;
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return clocksource_register_hz(&tegra->osc, 38400000);
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}
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static u64 tegra186_timer_usec_read(struct clocksource *cs)
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{
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struct tegra186_timer *tegra = container_of(cs, struct tegra186_timer,
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usec);
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return readl_relaxed(tegra->regs + TKEUSEC);
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}
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static int tegra186_timer_usec_init(struct tegra186_timer *tegra)
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{
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tegra->usec.name = "usec";
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tegra->usec.rating = 300;
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tegra->usec.read = tegra186_timer_usec_read;
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tegra->usec.mask = CLOCKSOURCE_MASK(32);
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tegra->usec.flags = CLOCK_SOURCE_IS_CONTINUOUS;
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return clocksource_register_hz(&tegra->usec, USEC_PER_SEC);
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}
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static irqreturn_t tegra186_timer_irq(int irq, void *data)
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{
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struct tegra186_timer *tegra = data;
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if (watchdog_active(&tegra->wdt->base)) {
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tegra186_wdt_disable(tegra->wdt);
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tegra186_wdt_enable(tegra->wdt);
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}
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return IRQ_HANDLED;
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}
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static int tegra186_timer_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct tegra186_timer *tegra;
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unsigned int irq;
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int err;
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tegra = devm_kzalloc(dev, sizeof(*tegra), GFP_KERNEL);
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if (!tegra)
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return -ENOMEM;
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tegra->soc = of_device_get_match_data(dev);
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dev_set_drvdata(dev, tegra);
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tegra->dev = dev;
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tegra->regs = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(tegra->regs))
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return PTR_ERR(tegra->regs);
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err = platform_get_irq(pdev, 0);
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if (err < 0)
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return err;
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irq = err;
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/* create a watchdog using a preconfigured timer */
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tegra->wdt = tegra186_wdt_create(tegra, 0);
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if (IS_ERR(tegra->wdt)) {
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err = PTR_ERR(tegra->wdt);
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dev_err(dev, "failed to create WDT: %d\n", err);
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return err;
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}
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err = tegra186_timer_tsc_init(tegra);
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if (err < 0) {
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dev_err(dev, "failed to register TSC counter: %d\n", err);
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return err;
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}
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err = tegra186_timer_osc_init(tegra);
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if (err < 0) {
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dev_err(dev, "failed to register OSC counter: %d\n", err);
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goto unregister_tsc;
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}
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err = tegra186_timer_usec_init(tegra);
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if (err < 0) {
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dev_err(dev, "failed to register USEC counter: %d\n", err);
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goto unregister_osc;
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}
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err = devm_request_irq(dev, irq, tegra186_timer_irq, 0,
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"tegra186-timer", tegra);
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if (err < 0) {
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dev_err(dev, "failed to request IRQ#%u: %d\n", irq, err);
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goto unregister_usec;
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}
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return 0;
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unregister_usec:
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clocksource_unregister(&tegra->usec);
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unregister_osc:
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clocksource_unregister(&tegra->osc);
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unregister_tsc:
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clocksource_unregister(&tegra->tsc);
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return err;
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}
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static int tegra186_timer_remove(struct platform_device *pdev)
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{
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struct tegra186_timer *tegra = platform_get_drvdata(pdev);
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clocksource_unregister(&tegra->usec);
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clocksource_unregister(&tegra->osc);
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clocksource_unregister(&tegra->tsc);
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return 0;
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}
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static int __maybe_unused tegra186_timer_suspend(struct device *dev)
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{
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struct tegra186_timer *tegra = dev_get_drvdata(dev);
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if (watchdog_active(&tegra->wdt->base))
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tegra186_wdt_disable(tegra->wdt);
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return 0;
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}
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static int __maybe_unused tegra186_timer_resume(struct device *dev)
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{
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struct tegra186_timer *tegra = dev_get_drvdata(dev);
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if (watchdog_active(&tegra->wdt->base))
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tegra186_wdt_enable(tegra->wdt);
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return 0;
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}
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static SIMPLE_DEV_PM_OPS(tegra186_timer_pm_ops, tegra186_timer_suspend,
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tegra186_timer_resume);
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static const struct tegra186_timer_soc tegra186_timer = {
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.num_timers = 10,
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.num_wdts = 3,
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};
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static const struct tegra186_timer_soc tegra234_timer = {
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.num_timers = 16,
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.num_wdts = 3,
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};
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static const struct of_device_id tegra186_timer_of_match[] = {
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{ .compatible = "nvidia,tegra186-timer", .data = &tegra186_timer },
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{ .compatible = "nvidia,tegra234-timer", .data = &tegra234_timer },
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{ }
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};
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MODULE_DEVICE_TABLE(of, tegra186_timer_of_match);
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static struct platform_driver tegra186_wdt_driver = {
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.driver = {
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.name = "tegra186-timer",
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.pm = &tegra186_timer_pm_ops,
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.of_match_table = tegra186_timer_of_match,
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},
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.probe = tegra186_timer_probe,
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.remove = tegra186_timer_remove,
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};
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module_platform_driver(tegra186_wdt_driver);
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MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>");
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MODULE_DESCRIPTION("NVIDIA Tegra186 timers driver");
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MODULE_LICENSE("GPL v2");
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