524 lines
14 KiB
C
524 lines
14 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/* pci_fire.c: Sun4u platform PCI-E controller support.
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*
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* Copyright (C) 2007 David S. Miller (davem@davemloft.net)
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*/
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#include <linux/kernel.h>
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#include <linux/pci.h>
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#include <linux/slab.h>
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#include <linux/init.h>
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#include <linux/msi.h>
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#include <linux/export.h>
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#include <linux/irq.h>
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#include <linux/of_device.h>
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#include <linux/numa.h>
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#include <asm/prom.h>
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#include <asm/irq.h>
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#include <asm/upa.h>
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#include "pci_impl.h"
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#define DRIVER_NAME "fire"
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#define PFX DRIVER_NAME ": "
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#define FIRE_IOMMU_CONTROL 0x40000UL
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#define FIRE_IOMMU_TSBBASE 0x40008UL
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#define FIRE_IOMMU_FLUSH 0x40100UL
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#define FIRE_IOMMU_FLUSHINV 0x40108UL
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static int pci_fire_pbm_iommu_init(struct pci_pbm_info *pbm)
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{
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struct iommu *iommu = pbm->iommu;
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u32 vdma[2], dma_mask;
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u64 control;
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int tsbsize, err;
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/* No virtual-dma property on these guys, use largest size. */
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vdma[0] = 0xc0000000; /* base */
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vdma[1] = 0x40000000; /* size */
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dma_mask = 0xffffffff;
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tsbsize = 128;
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/* Register addresses. */
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iommu->iommu_control = pbm->pbm_regs + FIRE_IOMMU_CONTROL;
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iommu->iommu_tsbbase = pbm->pbm_regs + FIRE_IOMMU_TSBBASE;
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iommu->iommu_flush = pbm->pbm_regs + FIRE_IOMMU_FLUSH;
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iommu->iommu_flushinv = pbm->pbm_regs + FIRE_IOMMU_FLUSHINV;
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/* We use the main control/status register of FIRE as the write
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* completion register.
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*/
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iommu->write_complete_reg = pbm->controller_regs + 0x410000UL;
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/*
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* Invalidate TLB Entries.
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*/
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upa_writeq(~(u64)0, iommu->iommu_flushinv);
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err = iommu_table_init(iommu, tsbsize * 8 * 1024, vdma[0], dma_mask,
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pbm->numa_node);
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if (err)
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return err;
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upa_writeq(__pa(iommu->page_table) | 0x7UL, iommu->iommu_tsbbase);
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control = upa_readq(iommu->iommu_control);
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control |= (0x00000400 /* TSB cache snoop enable */ |
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0x00000300 /* Cache mode */ |
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0x00000002 /* Bypass enable */ |
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0x00000001 /* Translation enable */);
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upa_writeq(control, iommu->iommu_control);
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return 0;
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}
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#ifdef CONFIG_PCI_MSI
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struct pci_msiq_entry {
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u64 word0;
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#define MSIQ_WORD0_RESV 0x8000000000000000UL
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#define MSIQ_WORD0_FMT_TYPE 0x7f00000000000000UL
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#define MSIQ_WORD0_FMT_TYPE_SHIFT 56
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#define MSIQ_WORD0_LEN 0x00ffc00000000000UL
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#define MSIQ_WORD0_LEN_SHIFT 46
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#define MSIQ_WORD0_ADDR0 0x00003fff00000000UL
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#define MSIQ_WORD0_ADDR0_SHIFT 32
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#define MSIQ_WORD0_RID 0x00000000ffff0000UL
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#define MSIQ_WORD0_RID_SHIFT 16
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#define MSIQ_WORD0_DATA0 0x000000000000ffffUL
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#define MSIQ_WORD0_DATA0_SHIFT 0
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#define MSIQ_TYPE_MSG 0x6
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#define MSIQ_TYPE_MSI32 0xb
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#define MSIQ_TYPE_MSI64 0xf
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u64 word1;
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#define MSIQ_WORD1_ADDR1 0xffffffffffff0000UL
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#define MSIQ_WORD1_ADDR1_SHIFT 16
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#define MSIQ_WORD1_DATA1 0x000000000000ffffUL
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#define MSIQ_WORD1_DATA1_SHIFT 0
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u64 resv[6];
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};
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/* All MSI registers are offset from pbm->pbm_regs */
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#define EVENT_QUEUE_BASE_ADDR_REG 0x010000UL
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#define EVENT_QUEUE_BASE_ADDR_ALL_ONES 0xfffc000000000000UL
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#define EVENT_QUEUE_CONTROL_SET(EQ) (0x011000UL + (EQ) * 0x8UL)
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#define EVENT_QUEUE_CONTROL_SET_OFLOW 0x0200000000000000UL
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#define EVENT_QUEUE_CONTROL_SET_EN 0x0000100000000000UL
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#define EVENT_QUEUE_CONTROL_CLEAR(EQ) (0x011200UL + (EQ) * 0x8UL)
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#define EVENT_QUEUE_CONTROL_CLEAR_OF 0x0200000000000000UL
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#define EVENT_QUEUE_CONTROL_CLEAR_E2I 0x0000800000000000UL
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#define EVENT_QUEUE_CONTROL_CLEAR_DIS 0x0000100000000000UL
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#define EVENT_QUEUE_STATE(EQ) (0x011400UL + (EQ) * 0x8UL)
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#define EVENT_QUEUE_STATE_MASK 0x0000000000000007UL
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#define EVENT_QUEUE_STATE_IDLE 0x0000000000000001UL
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#define EVENT_QUEUE_STATE_ACTIVE 0x0000000000000002UL
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#define EVENT_QUEUE_STATE_ERROR 0x0000000000000004UL
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#define EVENT_QUEUE_TAIL(EQ) (0x011600UL + (EQ) * 0x8UL)
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#define EVENT_QUEUE_TAIL_OFLOW 0x0200000000000000UL
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#define EVENT_QUEUE_TAIL_VAL 0x000000000000007fUL
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#define EVENT_QUEUE_HEAD(EQ) (0x011800UL + (EQ) * 0x8UL)
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#define EVENT_QUEUE_HEAD_VAL 0x000000000000007fUL
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#define MSI_MAP(MSI) (0x020000UL + (MSI) * 0x8UL)
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#define MSI_MAP_VALID 0x8000000000000000UL
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#define MSI_MAP_EQWR_N 0x4000000000000000UL
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#define MSI_MAP_EQNUM 0x000000000000003fUL
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#define MSI_CLEAR(MSI) (0x028000UL + (MSI) * 0x8UL)
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#define MSI_CLEAR_EQWR_N 0x4000000000000000UL
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#define IMONDO_DATA0 0x02C000UL
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#define IMONDO_DATA0_DATA 0xffffffffffffffc0UL
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#define IMONDO_DATA1 0x02C008UL
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#define IMONDO_DATA1_DATA 0xffffffffffffffffUL
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#define MSI_32BIT_ADDR 0x034000UL
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#define MSI_32BIT_ADDR_VAL 0x00000000ffff0000UL
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#define MSI_64BIT_ADDR 0x034008UL
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#define MSI_64BIT_ADDR_VAL 0xffffffffffff0000UL
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static int pci_fire_get_head(struct pci_pbm_info *pbm, unsigned long msiqid,
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unsigned long *head)
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{
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*head = upa_readq(pbm->pbm_regs + EVENT_QUEUE_HEAD(msiqid));
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return 0;
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}
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static int pci_fire_dequeue_msi(struct pci_pbm_info *pbm, unsigned long msiqid,
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unsigned long *head, unsigned long *msi)
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{
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unsigned long type_fmt, type, msi_num;
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struct pci_msiq_entry *base, *ep;
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base = (pbm->msi_queues + ((msiqid - pbm->msiq_first) * 8192));
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ep = &base[*head];
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if ((ep->word0 & MSIQ_WORD0_FMT_TYPE) == 0)
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return 0;
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type_fmt = ((ep->word0 & MSIQ_WORD0_FMT_TYPE) >>
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MSIQ_WORD0_FMT_TYPE_SHIFT);
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type = (type_fmt >> 3);
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if (unlikely(type != MSIQ_TYPE_MSI32 &&
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type != MSIQ_TYPE_MSI64))
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return -EINVAL;
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*msi = msi_num = ((ep->word0 & MSIQ_WORD0_DATA0) >>
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MSIQ_WORD0_DATA0_SHIFT);
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upa_writeq(MSI_CLEAR_EQWR_N, pbm->pbm_regs + MSI_CLEAR(msi_num));
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/* Clear the entry. */
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ep->word0 &= ~MSIQ_WORD0_FMT_TYPE;
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/* Go to next entry in ring. */
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(*head)++;
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if (*head >= pbm->msiq_ent_count)
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*head = 0;
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return 1;
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}
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static int pci_fire_set_head(struct pci_pbm_info *pbm, unsigned long msiqid,
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unsigned long head)
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{
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upa_writeq(head, pbm->pbm_regs + EVENT_QUEUE_HEAD(msiqid));
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return 0;
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}
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static int pci_fire_msi_setup(struct pci_pbm_info *pbm, unsigned long msiqid,
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unsigned long msi, int is_msi64)
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{
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u64 val;
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val = upa_readq(pbm->pbm_regs + MSI_MAP(msi));
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val &= ~(MSI_MAP_EQNUM);
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val |= msiqid;
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upa_writeq(val, pbm->pbm_regs + MSI_MAP(msi));
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upa_writeq(MSI_CLEAR_EQWR_N, pbm->pbm_regs + MSI_CLEAR(msi));
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val = upa_readq(pbm->pbm_regs + MSI_MAP(msi));
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val |= MSI_MAP_VALID;
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upa_writeq(val, pbm->pbm_regs + MSI_MAP(msi));
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return 0;
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}
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static int pci_fire_msi_teardown(struct pci_pbm_info *pbm, unsigned long msi)
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{
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u64 val;
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val = upa_readq(pbm->pbm_regs + MSI_MAP(msi));
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val &= ~MSI_MAP_VALID;
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upa_writeq(val, pbm->pbm_regs + MSI_MAP(msi));
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return 0;
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}
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static int pci_fire_msiq_alloc(struct pci_pbm_info *pbm)
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{
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unsigned long pages, order, i;
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order = get_order(512 * 1024);
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pages = __get_free_pages(GFP_KERNEL | __GFP_COMP, order);
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if (pages == 0UL) {
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printk(KERN_ERR "MSI: Cannot allocate MSI queues (o=%lu).\n",
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order);
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return -ENOMEM;
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}
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memset((char *)pages, 0, PAGE_SIZE << order);
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pbm->msi_queues = (void *) pages;
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upa_writeq((EVENT_QUEUE_BASE_ADDR_ALL_ONES |
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__pa(pbm->msi_queues)),
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pbm->pbm_regs + EVENT_QUEUE_BASE_ADDR_REG);
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upa_writeq(pbm->portid << 6, pbm->pbm_regs + IMONDO_DATA0);
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upa_writeq(0, pbm->pbm_regs + IMONDO_DATA1);
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upa_writeq(pbm->msi32_start, pbm->pbm_regs + MSI_32BIT_ADDR);
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upa_writeq(pbm->msi64_start, pbm->pbm_regs + MSI_64BIT_ADDR);
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for (i = 0; i < pbm->msiq_num; i++) {
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upa_writeq(0, pbm->pbm_regs + EVENT_QUEUE_HEAD(i));
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upa_writeq(0, pbm->pbm_regs + EVENT_QUEUE_TAIL(i));
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}
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return 0;
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}
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static void pci_fire_msiq_free(struct pci_pbm_info *pbm)
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{
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unsigned long pages, order;
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order = get_order(512 * 1024);
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pages = (unsigned long) pbm->msi_queues;
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free_pages(pages, order);
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pbm->msi_queues = NULL;
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}
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static int pci_fire_msiq_build_irq(struct pci_pbm_info *pbm,
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unsigned long msiqid,
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unsigned long devino)
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{
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unsigned long cregs = (unsigned long) pbm->pbm_regs;
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unsigned long imap_reg, iclr_reg, int_ctrlr;
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unsigned int irq;
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int fixup;
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u64 val;
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imap_reg = cregs + (0x001000UL + (devino * 0x08UL));
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iclr_reg = cregs + (0x001400UL + (devino * 0x08UL));
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/* XXX iterate amongst the 4 IRQ controllers XXX */
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int_ctrlr = (1UL << 6);
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val = upa_readq(imap_reg);
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val |= (1UL << 63) | int_ctrlr;
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upa_writeq(val, imap_reg);
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fixup = ((pbm->portid << 6) | devino) - int_ctrlr;
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irq = build_irq(fixup, iclr_reg, imap_reg);
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if (!irq)
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return -ENOMEM;
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upa_writeq(EVENT_QUEUE_CONTROL_SET_EN,
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pbm->pbm_regs + EVENT_QUEUE_CONTROL_SET(msiqid));
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return irq;
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}
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static const struct sparc64_msiq_ops pci_fire_msiq_ops = {
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.get_head = pci_fire_get_head,
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.dequeue_msi = pci_fire_dequeue_msi,
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.set_head = pci_fire_set_head,
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.msi_setup = pci_fire_msi_setup,
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.msi_teardown = pci_fire_msi_teardown,
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.msiq_alloc = pci_fire_msiq_alloc,
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.msiq_free = pci_fire_msiq_free,
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.msiq_build_irq = pci_fire_msiq_build_irq,
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};
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static void pci_fire_msi_init(struct pci_pbm_info *pbm)
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{
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sparc64_pbm_msi_init(pbm, &pci_fire_msiq_ops);
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}
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#else /* CONFIG_PCI_MSI */
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static void pci_fire_msi_init(struct pci_pbm_info *pbm)
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{
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}
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#endif /* !(CONFIG_PCI_MSI) */
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/* Based at pbm->controller_regs */
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#define FIRE_PARITY_CONTROL 0x470010UL
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#define FIRE_PARITY_ENAB 0x8000000000000000UL
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#define FIRE_FATAL_RESET_CTL 0x471028UL
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#define FIRE_FATAL_RESET_SPARE 0x0000000004000000UL
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#define FIRE_FATAL_RESET_MB 0x0000000002000000UL
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#define FIRE_FATAL_RESET_CPE 0x0000000000008000UL
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#define FIRE_FATAL_RESET_APE 0x0000000000004000UL
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#define FIRE_FATAL_RESET_PIO 0x0000000000000040UL
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#define FIRE_FATAL_RESET_JW 0x0000000000000004UL
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#define FIRE_FATAL_RESET_JI 0x0000000000000002UL
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#define FIRE_FATAL_RESET_JR 0x0000000000000001UL
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#define FIRE_CORE_INTR_ENABLE 0x471800UL
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/* Based at pbm->pbm_regs */
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#define FIRE_TLU_CTRL 0x80000UL
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#define FIRE_TLU_CTRL_TIM 0x00000000da000000UL
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#define FIRE_TLU_CTRL_QDET 0x0000000000000100UL
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#define FIRE_TLU_CTRL_CFG 0x0000000000000001UL
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#define FIRE_TLU_DEV_CTRL 0x90008UL
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#define FIRE_TLU_LINK_CTRL 0x90020UL
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#define FIRE_TLU_LINK_CTRL_CLK 0x0000000000000040UL
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#define FIRE_LPU_RESET 0xe2008UL
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#define FIRE_LPU_LLCFG 0xe2200UL
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#define FIRE_LPU_LLCFG_VC0 0x0000000000000100UL
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#define FIRE_LPU_FCTRL_UCTRL 0xe2240UL
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#define FIRE_LPU_FCTRL_UCTRL_N 0x0000000000000002UL
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#define FIRE_LPU_FCTRL_UCTRL_P 0x0000000000000001UL
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#define FIRE_LPU_TXL_FIFOP 0xe2430UL
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#define FIRE_LPU_LTSSM_CFG2 0xe2788UL
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#define FIRE_LPU_LTSSM_CFG3 0xe2790UL
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#define FIRE_LPU_LTSSM_CFG4 0xe2798UL
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#define FIRE_LPU_LTSSM_CFG5 0xe27a0UL
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#define FIRE_DMC_IENAB 0x31800UL
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#define FIRE_DMC_DBG_SEL_A 0x53000UL
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#define FIRE_DMC_DBG_SEL_B 0x53008UL
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#define FIRE_PEC_IENAB 0x51800UL
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static void pci_fire_hw_init(struct pci_pbm_info *pbm)
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{
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u64 val;
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upa_writeq(FIRE_PARITY_ENAB,
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pbm->controller_regs + FIRE_PARITY_CONTROL);
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upa_writeq((FIRE_FATAL_RESET_SPARE |
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FIRE_FATAL_RESET_MB |
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FIRE_FATAL_RESET_CPE |
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FIRE_FATAL_RESET_APE |
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FIRE_FATAL_RESET_PIO |
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FIRE_FATAL_RESET_JW |
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FIRE_FATAL_RESET_JI |
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FIRE_FATAL_RESET_JR),
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pbm->controller_regs + FIRE_FATAL_RESET_CTL);
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upa_writeq(~(u64)0, pbm->controller_regs + FIRE_CORE_INTR_ENABLE);
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val = upa_readq(pbm->pbm_regs + FIRE_TLU_CTRL);
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val |= (FIRE_TLU_CTRL_TIM |
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FIRE_TLU_CTRL_QDET |
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FIRE_TLU_CTRL_CFG);
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upa_writeq(val, pbm->pbm_regs + FIRE_TLU_CTRL);
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upa_writeq(0, pbm->pbm_regs + FIRE_TLU_DEV_CTRL);
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upa_writeq(FIRE_TLU_LINK_CTRL_CLK,
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pbm->pbm_regs + FIRE_TLU_LINK_CTRL);
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upa_writeq(0, pbm->pbm_regs + FIRE_LPU_RESET);
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upa_writeq(FIRE_LPU_LLCFG_VC0, pbm->pbm_regs + FIRE_LPU_LLCFG);
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upa_writeq((FIRE_LPU_FCTRL_UCTRL_N | FIRE_LPU_FCTRL_UCTRL_P),
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pbm->pbm_regs + FIRE_LPU_FCTRL_UCTRL);
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upa_writeq(((0xffff << 16) | (0x0000 << 0)),
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pbm->pbm_regs + FIRE_LPU_TXL_FIFOP);
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upa_writeq(3000000, pbm->pbm_regs + FIRE_LPU_LTSSM_CFG2);
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upa_writeq(500000, pbm->pbm_regs + FIRE_LPU_LTSSM_CFG3);
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upa_writeq((2 << 16) | (140 << 8),
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pbm->pbm_regs + FIRE_LPU_LTSSM_CFG4);
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upa_writeq(0, pbm->pbm_regs + FIRE_LPU_LTSSM_CFG5);
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upa_writeq(~(u64)0, pbm->pbm_regs + FIRE_DMC_IENAB);
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upa_writeq(0, pbm->pbm_regs + FIRE_DMC_DBG_SEL_A);
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upa_writeq(0, pbm->pbm_regs + FIRE_DMC_DBG_SEL_B);
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upa_writeq(~(u64)0, pbm->pbm_regs + FIRE_PEC_IENAB);
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}
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static int pci_fire_pbm_init(struct pci_pbm_info *pbm,
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struct platform_device *op, u32 portid)
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{
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const struct linux_prom64_registers *regs;
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struct device_node *dp = op->dev.of_node;
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int err;
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pbm->numa_node = NUMA_NO_NODE;
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pbm->pci_ops = &sun4u_pci_ops;
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pbm->config_space_reg_bits = 12;
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pbm->index = pci_num_pbms++;
|
|
|
|
pbm->portid = portid;
|
|
pbm->op = op;
|
|
pbm->name = dp->full_name;
|
|
|
|
regs = of_get_property(dp, "reg", NULL);
|
|
pbm->pbm_regs = regs[0].phys_addr;
|
|
pbm->controller_regs = regs[1].phys_addr - 0x410000UL;
|
|
|
|
printk("%s: SUN4U PCIE Bus Module\n", pbm->name);
|
|
|
|
pci_determine_mem_io_space(pbm);
|
|
|
|
pci_get_pbm_props(pbm);
|
|
|
|
pci_fire_hw_init(pbm);
|
|
|
|
err = pci_fire_pbm_iommu_init(pbm);
|
|
if (err)
|
|
return err;
|
|
|
|
pci_fire_msi_init(pbm);
|
|
|
|
pbm->pci_bus = pci_scan_one_pbm(pbm, &op->dev);
|
|
|
|
/* XXX register error interrupt handlers XXX */
|
|
|
|
pbm->next = pci_pbm_root;
|
|
pci_pbm_root = pbm;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int fire_probe(struct platform_device *op)
|
|
{
|
|
struct device_node *dp = op->dev.of_node;
|
|
struct pci_pbm_info *pbm;
|
|
struct iommu *iommu;
|
|
u32 portid;
|
|
int err;
|
|
|
|
portid = of_getintprop_default(dp, "portid", 0xff);
|
|
|
|
err = -ENOMEM;
|
|
pbm = kzalloc(sizeof(*pbm), GFP_KERNEL);
|
|
if (!pbm) {
|
|
printk(KERN_ERR PFX "Cannot allocate pci_pbminfo.\n");
|
|
goto out_err;
|
|
}
|
|
|
|
iommu = kzalloc(sizeof(struct iommu), GFP_KERNEL);
|
|
if (!iommu) {
|
|
printk(KERN_ERR PFX "Cannot allocate PBM iommu.\n");
|
|
goto out_free_controller;
|
|
}
|
|
|
|
pbm->iommu = iommu;
|
|
|
|
err = pci_fire_pbm_init(pbm, op, portid);
|
|
if (err)
|
|
goto out_free_iommu;
|
|
|
|
dev_set_drvdata(&op->dev, pbm);
|
|
|
|
return 0;
|
|
|
|
out_free_iommu:
|
|
kfree(pbm->iommu);
|
|
|
|
out_free_controller:
|
|
kfree(pbm);
|
|
|
|
out_err:
|
|
return err;
|
|
}
|
|
|
|
static const struct of_device_id fire_match[] = {
|
|
{
|
|
.name = "pci",
|
|
.compatible = "pciex108e,80f0",
|
|
},
|
|
{},
|
|
};
|
|
|
|
static struct platform_driver fire_driver = {
|
|
.driver = {
|
|
.name = DRIVER_NAME,
|
|
.of_match_table = fire_match,
|
|
},
|
|
.probe = fire_probe,
|
|
};
|
|
|
|
static int __init fire_init(void)
|
|
{
|
|
return platform_driver_register(&fire_driver);
|
|
}
|
|
|
|
subsys_initcall(fire_init);
|