336 lines
8.1 KiB
C
336 lines
8.1 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Access to PCI I/O memory from user space programs.
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*
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* Copyright IBM Corp. 2014
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* Author(s): Alexey Ishchuk <aishchuk@linux.vnet.ibm.com>
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*/
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#include <linux/kernel.h>
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#include <linux/syscalls.h>
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#include <linux/init.h>
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#include <linux/mm.h>
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#include <linux/errno.h>
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#include <linux/pci.h>
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#include <asm/asm-extable.h>
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#include <asm/pci_io.h>
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#include <asm/pci_debug.h>
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static inline void zpci_err_mmio(u8 cc, u8 status, u64 offset)
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{
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struct {
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u64 offset;
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u8 cc;
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u8 status;
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} data = {offset, cc, status};
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zpci_err_hex(&data, sizeof(data));
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}
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static inline int __pcistb_mio_inuser(
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void __iomem *ioaddr, const void __user *src,
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u64 len, u8 *status)
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{
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int cc = -ENXIO;
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asm volatile (
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" sacf 256\n"
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"0: .insn rsy,0xeb00000000d4,%[len],%[ioaddr],%[src]\n"
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"1: ipm %[cc]\n"
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" srl %[cc],28\n"
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"2: sacf 768\n"
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EX_TABLE(0b, 2b) EX_TABLE(1b, 2b)
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: [cc] "+d" (cc), [len] "+d" (len)
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: [ioaddr] "a" (ioaddr), [src] "Q" (*((u8 __force *)src))
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: "cc", "memory");
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*status = len >> 24 & 0xff;
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return cc;
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}
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static inline int __pcistg_mio_inuser(
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void __iomem *ioaddr, const void __user *src,
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u64 ulen, u8 *status)
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{
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union register_pair ioaddr_len = {.even = (u64 __force)ioaddr, .odd = ulen};
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int cc = -ENXIO;
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u64 val = 0;
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u64 cnt = ulen;
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u8 tmp;
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/*
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* copy 0 < @len <= 8 bytes from @src into the right most bytes of
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* a register, then store it to PCI at @ioaddr while in secondary
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* address space. pcistg then uses the user mappings.
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*/
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asm volatile (
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" sacf 256\n"
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"0: llgc %[tmp],0(%[src])\n"
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"4: sllg %[val],%[val],8\n"
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" aghi %[src],1\n"
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" ogr %[val],%[tmp]\n"
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" brctg %[cnt],0b\n"
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"1: .insn rre,0xb9d40000,%[val],%[ioaddr_len]\n"
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"2: ipm %[cc]\n"
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" srl %[cc],28\n"
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"3: sacf 768\n"
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EX_TABLE(0b, 3b) EX_TABLE(4b, 3b) EX_TABLE(1b, 3b) EX_TABLE(2b, 3b)
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:
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[src] "+a" (src), [cnt] "+d" (cnt),
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[val] "+d" (val), [tmp] "=d" (tmp),
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[cc] "+d" (cc), [ioaddr_len] "+&d" (ioaddr_len.pair)
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:: "cc", "memory");
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*status = ioaddr_len.odd >> 24 & 0xff;
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/* did we read everything from user memory? */
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if (!cc && cnt != 0)
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cc = -EFAULT;
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return cc;
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}
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static inline int __memcpy_toio_inuser(void __iomem *dst,
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const void __user *src, size_t n)
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{
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int size, rc = 0;
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u8 status = 0;
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if (!src)
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return -EINVAL;
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while (n > 0) {
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size = zpci_get_max_write_size((u64 __force) dst,
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(u64 __force) src, n,
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ZPCI_MAX_WRITE_SIZE);
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if (size > 8) /* main path */
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rc = __pcistb_mio_inuser(dst, src, size, &status);
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else
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rc = __pcistg_mio_inuser(dst, src, size, &status);
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if (rc)
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break;
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src += size;
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dst += size;
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n -= size;
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}
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if (rc)
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zpci_err_mmio(rc, status, (__force u64) dst);
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return rc;
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}
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SYSCALL_DEFINE3(s390_pci_mmio_write, unsigned long, mmio_addr,
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const void __user *, user_buffer, size_t, length)
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{
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u8 local_buf[64];
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void __iomem *io_addr;
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void *buf;
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struct vm_area_struct *vma;
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pte_t *ptep;
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spinlock_t *ptl;
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long ret;
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if (!zpci_is_enabled())
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return -ENODEV;
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if (length <= 0 || PAGE_SIZE - (mmio_addr & ~PAGE_MASK) < length)
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return -EINVAL;
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/*
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* We only support write access to MIO capable devices if we are on
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* a MIO enabled system. Otherwise we would have to check for every
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* address if it is a special ZPCI_ADDR and would have to do
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* a pfn lookup which we don't need for MIO capable devices. Currently
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* ISM devices are the only devices without MIO support and there is no
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* known need for accessing these from userspace.
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*/
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if (static_branch_likely(&have_mio)) {
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ret = __memcpy_toio_inuser((void __iomem *) mmio_addr,
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user_buffer,
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length);
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return ret;
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}
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if (length > 64) {
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buf = kmalloc(length, GFP_KERNEL);
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if (!buf)
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return -ENOMEM;
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} else
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buf = local_buf;
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ret = -EFAULT;
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if (copy_from_user(buf, user_buffer, length))
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goto out_free;
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mmap_read_lock(current->mm);
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ret = -EINVAL;
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vma = vma_lookup(current->mm, mmio_addr);
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if (!vma)
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goto out_unlock_mmap;
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if (!(vma->vm_flags & (VM_IO | VM_PFNMAP)))
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goto out_unlock_mmap;
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ret = -EACCES;
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if (!(vma->vm_flags & VM_WRITE))
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goto out_unlock_mmap;
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ret = follow_pte(vma->vm_mm, mmio_addr, &ptep, &ptl);
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if (ret)
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goto out_unlock_mmap;
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io_addr = (void __iomem *)((pte_pfn(*ptep) << PAGE_SHIFT) |
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(mmio_addr & ~PAGE_MASK));
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if ((unsigned long) io_addr < ZPCI_IOMAP_ADDR_BASE)
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goto out_unlock_pt;
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ret = zpci_memcpy_toio(io_addr, buf, length);
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out_unlock_pt:
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pte_unmap_unlock(ptep, ptl);
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out_unlock_mmap:
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mmap_read_unlock(current->mm);
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out_free:
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if (buf != local_buf)
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kfree(buf);
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return ret;
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}
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static inline int __pcilg_mio_inuser(
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void __user *dst, const void __iomem *ioaddr,
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u64 ulen, u8 *status)
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{
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union register_pair ioaddr_len = {.even = (u64 __force)ioaddr, .odd = ulen};
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u64 cnt = ulen;
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int shift = ulen * 8;
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int cc = -ENXIO;
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u64 val, tmp;
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/*
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* read 0 < @len <= 8 bytes from the PCI memory mapped at @ioaddr (in
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* user space) into a register using pcilg then store these bytes at
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* user address @dst
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*/
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asm volatile (
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" sacf 256\n"
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"0: .insn rre,0xb9d60000,%[val],%[ioaddr_len]\n"
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"1: ipm %[cc]\n"
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" srl %[cc],28\n"
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" ltr %[cc],%[cc]\n"
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" jne 4f\n"
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"2: ahi %[shift],-8\n"
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" srlg %[tmp],%[val],0(%[shift])\n"
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"3: stc %[tmp],0(%[dst])\n"
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"5: aghi %[dst],1\n"
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" brctg %[cnt],2b\n"
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"4: sacf 768\n"
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EX_TABLE(0b, 4b) EX_TABLE(1b, 4b) EX_TABLE(3b, 4b) EX_TABLE(5b, 4b)
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:
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[ioaddr_len] "+&d" (ioaddr_len.pair),
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[cc] "+d" (cc), [val] "=d" (val),
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[dst] "+a" (dst), [cnt] "+d" (cnt), [tmp] "=d" (tmp),
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[shift] "+d" (shift)
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:: "cc", "memory");
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/* did we write everything to the user space buffer? */
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if (!cc && cnt != 0)
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cc = -EFAULT;
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*status = ioaddr_len.odd >> 24 & 0xff;
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return cc;
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}
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static inline int __memcpy_fromio_inuser(void __user *dst,
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const void __iomem *src,
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unsigned long n)
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{
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int size, rc = 0;
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u8 status;
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while (n > 0) {
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size = zpci_get_max_write_size((u64 __force) src,
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(u64 __force) dst, n,
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ZPCI_MAX_READ_SIZE);
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rc = __pcilg_mio_inuser(dst, src, size, &status);
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if (rc)
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break;
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src += size;
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dst += size;
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n -= size;
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}
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if (rc)
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zpci_err_mmio(rc, status, (__force u64) dst);
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return rc;
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}
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SYSCALL_DEFINE3(s390_pci_mmio_read, unsigned long, mmio_addr,
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void __user *, user_buffer, size_t, length)
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{
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u8 local_buf[64];
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void __iomem *io_addr;
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void *buf;
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struct vm_area_struct *vma;
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pte_t *ptep;
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spinlock_t *ptl;
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long ret;
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if (!zpci_is_enabled())
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return -ENODEV;
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if (length <= 0 || PAGE_SIZE - (mmio_addr & ~PAGE_MASK) < length)
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return -EINVAL;
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/*
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* We only support read access to MIO capable devices if we are on
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* a MIO enabled system. Otherwise we would have to check for every
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* address if it is a special ZPCI_ADDR and would have to do
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* a pfn lookup which we don't need for MIO capable devices. Currently
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* ISM devices are the only devices without MIO support and there is no
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* known need for accessing these from userspace.
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*/
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if (static_branch_likely(&have_mio)) {
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ret = __memcpy_fromio_inuser(
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user_buffer, (const void __iomem *)mmio_addr,
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length);
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return ret;
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}
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if (length > 64) {
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buf = kmalloc(length, GFP_KERNEL);
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if (!buf)
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return -ENOMEM;
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} else {
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buf = local_buf;
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}
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mmap_read_lock(current->mm);
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ret = -EINVAL;
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vma = vma_lookup(current->mm, mmio_addr);
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if (!vma)
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goto out_unlock_mmap;
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if (!(vma->vm_flags & (VM_IO | VM_PFNMAP)))
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goto out_unlock_mmap;
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ret = -EACCES;
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if (!(vma->vm_flags & VM_WRITE))
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goto out_unlock_mmap;
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ret = follow_pte(vma->vm_mm, mmio_addr, &ptep, &ptl);
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if (ret)
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goto out_unlock_mmap;
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io_addr = (void __iomem *)((pte_pfn(*ptep) << PAGE_SHIFT) |
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(mmio_addr & ~PAGE_MASK));
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if ((unsigned long) io_addr < ZPCI_IOMAP_ADDR_BASE) {
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ret = -EFAULT;
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goto out_unlock_pt;
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}
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ret = zpci_memcpy_fromio(buf, io_addr, length);
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out_unlock_pt:
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pte_unmap_unlock(ptep, ptl);
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out_unlock_mmap:
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mmap_read_unlock(current->mm);
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if (!ret && copy_to_user(user_buffer, buf, length))
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ret = -EFAULT;
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if (buf != local_buf)
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kfree(buf);
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return ret;
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}
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