690 lines
20 KiB
C
690 lines
20 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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#ifndef _ASM_POWERPC_INTERRUPT_H
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#define _ASM_POWERPC_INTERRUPT_H
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/* BookE/4xx */
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#define INTERRUPT_CRITICAL_INPUT 0x100
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/* BookE */
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#define INTERRUPT_DEBUG 0xd00
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#ifdef CONFIG_BOOKE
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#define INTERRUPT_PERFMON 0x260
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#define INTERRUPT_DOORBELL 0x280
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#endif
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/* BookS/4xx/8xx */
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#define INTERRUPT_MACHINE_CHECK 0x200
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/* BookS/8xx */
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#define INTERRUPT_SYSTEM_RESET 0x100
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/* BookS */
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#define INTERRUPT_DATA_SEGMENT 0x380
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#define INTERRUPT_INST_SEGMENT 0x480
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#define INTERRUPT_TRACE 0xd00
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#define INTERRUPT_H_DATA_STORAGE 0xe00
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#define INTERRUPT_HMI 0xe60
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#define INTERRUPT_H_FAC_UNAVAIL 0xf80
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#ifdef CONFIG_PPC_BOOK3S
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#define INTERRUPT_DOORBELL 0xa00
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#define INTERRUPT_PERFMON 0xf00
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#define INTERRUPT_ALTIVEC_UNAVAIL 0xf20
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#endif
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/* BookE/BookS/4xx/8xx */
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#define INTERRUPT_DATA_STORAGE 0x300
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#define INTERRUPT_INST_STORAGE 0x400
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#define INTERRUPT_EXTERNAL 0x500
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#define INTERRUPT_ALIGNMENT 0x600
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#define INTERRUPT_PROGRAM 0x700
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#define INTERRUPT_SYSCALL 0xc00
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#define INTERRUPT_TRACE 0xd00
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/* BookE/BookS/44x */
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#define INTERRUPT_FP_UNAVAIL 0x800
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/* BookE/BookS/44x/8xx */
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#define INTERRUPT_DECREMENTER 0x900
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#ifndef INTERRUPT_PERFMON
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#define INTERRUPT_PERFMON 0x0
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#endif
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/* 8xx */
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#define INTERRUPT_SOFT_EMU_8xx 0x1000
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#define INTERRUPT_INST_TLB_MISS_8xx 0x1100
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#define INTERRUPT_DATA_TLB_MISS_8xx 0x1200
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#define INTERRUPT_INST_TLB_ERROR_8xx 0x1300
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#define INTERRUPT_DATA_TLB_ERROR_8xx 0x1400
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#define INTERRUPT_DATA_BREAKPOINT_8xx 0x1c00
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#define INTERRUPT_INST_BREAKPOINT_8xx 0x1d00
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/* 603 */
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#define INTERRUPT_INST_TLB_MISS_603 0x1000
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#define INTERRUPT_DATA_LOAD_TLB_MISS_603 0x1100
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#define INTERRUPT_DATA_STORE_TLB_MISS_603 0x1200
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#ifndef __ASSEMBLY__
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#include <linux/context_tracking.h>
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#include <linux/hardirq.h>
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#include <asm/cputime.h>
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#include <asm/firmware.h>
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#include <asm/ftrace.h>
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#include <asm/kprobes.h>
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#include <asm/runlatch.h>
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#ifdef CONFIG_PPC64
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/*
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* WARN/BUG is handled with a program interrupt so minimise checks here to
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* avoid recursion and maximise the chance of getting the first oops handled.
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*/
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#define INT_SOFT_MASK_BUG_ON(regs, cond) \
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do { \
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if (IS_ENABLED(CONFIG_PPC_IRQ_SOFT_MASK_DEBUG) && \
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(user_mode(regs) || (TRAP(regs) != INTERRUPT_PROGRAM))) \
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BUG_ON(cond); \
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} while (0)
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#endif
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#ifdef CONFIG_PPC_BOOK3S_64
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extern char __end_soft_masked[];
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bool search_kernel_soft_mask_table(unsigned long addr);
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unsigned long search_kernel_restart_table(unsigned long addr);
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DECLARE_STATIC_KEY_FALSE(interrupt_exit_not_reentrant);
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static inline bool is_implicit_soft_masked(struct pt_regs *regs)
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{
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if (regs->msr & MSR_PR)
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return false;
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if (regs->nip >= (unsigned long)__end_soft_masked)
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return false;
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return search_kernel_soft_mask_table(regs->nip);
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}
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static inline void srr_regs_clobbered(void)
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{
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local_paca->srr_valid = 0;
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local_paca->hsrr_valid = 0;
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}
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#else
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static inline unsigned long search_kernel_restart_table(unsigned long addr)
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{
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return 0;
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}
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static inline bool is_implicit_soft_masked(struct pt_regs *regs)
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{
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return false;
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}
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static inline void srr_regs_clobbered(void)
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{
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}
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#endif
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static inline void nap_adjust_return(struct pt_regs *regs)
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{
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#ifdef CONFIG_PPC_970_NAP
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if (unlikely(test_thread_local_flags(_TLF_NAPPING))) {
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/* Can avoid a test-and-clear because NMIs do not call this */
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clear_thread_local_flags(_TLF_NAPPING);
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regs_set_return_ip(regs, (unsigned long)power4_idle_nap_return);
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}
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#endif
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}
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static inline void booke_restore_dbcr0(void)
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{
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#ifdef CONFIG_PPC_ADV_DEBUG_REGS
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unsigned long dbcr0 = current->thread.debug.dbcr0;
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if (IS_ENABLED(CONFIG_PPC32) && unlikely(dbcr0 & DBCR0_IDM)) {
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mtspr(SPRN_DBSR, -1);
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mtspr(SPRN_DBCR0, global_dbcr0[smp_processor_id()]);
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}
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#endif
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}
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static inline void interrupt_enter_prepare(struct pt_regs *regs)
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{
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#ifdef CONFIG_PPC32
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if (!arch_irq_disabled_regs(regs))
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trace_hardirqs_off();
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if (user_mode(regs))
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kuap_lock();
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else
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kuap_save_and_lock(regs);
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if (user_mode(regs))
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account_cpu_user_entry();
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#endif
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#ifdef CONFIG_PPC64
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bool trace_enable = false;
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if (IS_ENABLED(CONFIG_TRACE_IRQFLAGS)) {
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if (irq_soft_mask_set_return(IRQS_ALL_DISABLED) == IRQS_ENABLED)
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trace_enable = true;
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} else {
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irq_soft_mask_set(IRQS_ALL_DISABLED);
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}
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/*
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* If the interrupt was taken with HARD_DIS clear, then enable MSR[EE].
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* Asynchronous interrupts get here with HARD_DIS set (see below), so
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* this enables MSR[EE] for synchronous interrupts. IRQs remain
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* soft-masked. The interrupt handler may later call
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* interrupt_cond_local_irq_enable() to achieve a regular process
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* context.
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*/
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if (!(local_paca->irq_happened & PACA_IRQ_HARD_DIS)) {
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INT_SOFT_MASK_BUG_ON(regs, !(regs->msr & MSR_EE));
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__hard_irq_enable();
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} else {
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__hard_RI_enable();
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}
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/* Do this when RI=1 because it can cause SLB faults */
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if (trace_enable)
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trace_hardirqs_off();
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if (user_mode(regs)) {
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kuap_lock();
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CT_WARN_ON(ct_state() != CONTEXT_USER);
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user_exit_irqoff();
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account_cpu_user_entry();
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account_stolen_time();
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} else {
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kuap_save_and_lock(regs);
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/*
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* CT_WARN_ON comes here via program_check_exception,
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* so avoid recursion.
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*/
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if (TRAP(regs) != INTERRUPT_PROGRAM)
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CT_WARN_ON(ct_state() != CONTEXT_KERNEL &&
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ct_state() != CONTEXT_IDLE);
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INT_SOFT_MASK_BUG_ON(regs, is_implicit_soft_masked(regs));
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INT_SOFT_MASK_BUG_ON(regs, arch_irq_disabled_regs(regs) &&
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search_kernel_restart_table(regs->nip));
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}
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INT_SOFT_MASK_BUG_ON(regs, !arch_irq_disabled_regs(regs) &&
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!(regs->msr & MSR_EE));
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#endif
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booke_restore_dbcr0();
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}
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/*
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* Care should be taken to note that interrupt_exit_prepare and
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* interrupt_async_exit_prepare do not necessarily return immediately to
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* regs context (e.g., if regs is usermode, we don't necessarily return to
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* user mode). Other interrupts might be taken between here and return,
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* context switch / preemption may occur in the exit path after this, or a
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* signal may be delivered, etc.
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*
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* The real interrupt exit code is platform specific, e.g.,
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* interrupt_exit_user_prepare / interrupt_exit_kernel_prepare for 64s.
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*
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* However interrupt_nmi_exit_prepare does return directly to regs, because
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* NMIs do not do "exit work" or replay soft-masked interrupts.
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*/
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static inline void interrupt_exit_prepare(struct pt_regs *regs)
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{
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}
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static inline void interrupt_async_enter_prepare(struct pt_regs *regs)
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{
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#ifdef CONFIG_PPC64
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/* Ensure interrupt_enter_prepare does not enable MSR[EE] */
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local_paca->irq_happened |= PACA_IRQ_HARD_DIS;
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#endif
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interrupt_enter_prepare(regs);
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#ifdef CONFIG_PPC_BOOK3S_64
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/*
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* RI=1 is set by interrupt_enter_prepare, so this thread flags access
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* has to come afterward (it can cause SLB faults).
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*/
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if (cpu_has_feature(CPU_FTR_CTRL) &&
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!test_thread_local_flags(_TLF_RUNLATCH))
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__ppc64_runlatch_on();
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#endif
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irq_enter();
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}
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static inline void interrupt_async_exit_prepare(struct pt_regs *regs)
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{
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/*
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* Adjust at exit so the main handler sees the true NIA. This must
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* come before irq_exit() because irq_exit can enable interrupts, and
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* if another interrupt is taken before nap_adjust_return has run
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* here, then that interrupt would return directly to idle nap return.
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*/
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nap_adjust_return(regs);
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irq_exit();
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interrupt_exit_prepare(regs);
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}
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struct interrupt_nmi_state {
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#ifdef CONFIG_PPC64
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u8 irq_soft_mask;
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u8 irq_happened;
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u8 ftrace_enabled;
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u64 softe;
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#endif
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};
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static inline bool nmi_disables_ftrace(struct pt_regs *regs)
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{
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/* Allow DEC and PMI to be traced when they are soft-NMI */
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if (IS_ENABLED(CONFIG_PPC_BOOK3S_64)) {
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if (TRAP(regs) == INTERRUPT_DECREMENTER)
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return false;
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if (TRAP(regs) == INTERRUPT_PERFMON)
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return false;
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}
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if (IS_ENABLED(CONFIG_PPC_BOOK3E_64)) {
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if (TRAP(regs) == INTERRUPT_PERFMON)
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return false;
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}
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return true;
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}
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static inline void interrupt_nmi_enter_prepare(struct pt_regs *regs, struct interrupt_nmi_state *state)
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{
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#ifdef CONFIG_PPC64
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state->irq_soft_mask = local_paca->irq_soft_mask;
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state->irq_happened = local_paca->irq_happened;
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state->softe = regs->softe;
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/*
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* Set IRQS_ALL_DISABLED unconditionally so irqs_disabled() does
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* the right thing, and set IRQ_HARD_DIS. We do not want to reconcile
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* because that goes through irq tracing which we don't want in NMI.
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*/
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local_paca->irq_soft_mask = IRQS_ALL_DISABLED;
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local_paca->irq_happened |= PACA_IRQ_HARD_DIS;
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if (!(regs->msr & MSR_EE) || is_implicit_soft_masked(regs)) {
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/*
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* Adjust regs->softe to be soft-masked if it had not been
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* reconcied (e.g., interrupt entry with MSR[EE]=0 but softe
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* not yet set disabled), or if it was in an implicit soft
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* masked state. This makes arch_irq_disabled_regs(regs)
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* behave as expected.
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*/
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regs->softe = IRQS_ALL_DISABLED;
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}
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__hard_RI_enable();
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/* Don't do any per-CPU operations until interrupt state is fixed */
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if (nmi_disables_ftrace(regs)) {
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state->ftrace_enabled = this_cpu_get_ftrace_enabled();
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this_cpu_set_ftrace_enabled(0);
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}
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#endif
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/* If data relocations are enabled, it's safe to use nmi_enter() */
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if (mfmsr() & MSR_DR) {
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nmi_enter();
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return;
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}
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/*
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* But do not use nmi_enter() for pseries hash guest taking a real-mode
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* NMI because not everything it touches is within the RMA limit.
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*/
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if (IS_ENABLED(CONFIG_PPC_BOOK3S_64) &&
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firmware_has_feature(FW_FEATURE_LPAR) &&
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!radix_enabled())
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return;
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/*
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* Likewise, don't use it if we have some form of instrumentation (like
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* KASAN shadow) that is not safe to access in real mode (even on radix)
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*/
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if (IS_ENABLED(CONFIG_KASAN))
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return;
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/* Otherwise, it should be safe to call it */
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nmi_enter();
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}
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static inline void interrupt_nmi_exit_prepare(struct pt_regs *regs, struct interrupt_nmi_state *state)
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{
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if (mfmsr() & MSR_DR) {
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// nmi_exit if relocations are on
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nmi_exit();
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} else if (IS_ENABLED(CONFIG_PPC_BOOK3S_64) &&
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firmware_has_feature(FW_FEATURE_LPAR) &&
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!radix_enabled()) {
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// no nmi_exit for a pseries hash guest taking a real mode exception
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} else if (IS_ENABLED(CONFIG_KASAN)) {
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// no nmi_exit for KASAN in real mode
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} else {
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nmi_exit();
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}
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/*
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* nmi does not call nap_adjust_return because nmi should not create
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* new work to do (must use irq_work for that).
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*/
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#ifdef CONFIG_PPC64
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#ifdef CONFIG_PPC_BOOK3S
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if (arch_irq_disabled_regs(regs)) {
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unsigned long rst = search_kernel_restart_table(regs->nip);
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if (rst)
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regs_set_return_ip(regs, rst);
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}
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#endif
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if (nmi_disables_ftrace(regs))
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this_cpu_set_ftrace_enabled(state->ftrace_enabled);
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/* Check we didn't change the pending interrupt mask. */
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WARN_ON_ONCE((state->irq_happened | PACA_IRQ_HARD_DIS) != local_paca->irq_happened);
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regs->softe = state->softe;
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local_paca->irq_happened = state->irq_happened;
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local_paca->irq_soft_mask = state->irq_soft_mask;
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#endif
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}
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/*
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* Don't use noinstr here like x86, but rather add NOKPROBE_SYMBOL to each
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* function definition. The reason for this is the noinstr section is placed
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* after the main text section, i.e., very far away from the interrupt entry
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* asm. That creates problems with fitting linker stubs when building large
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* kernels.
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*/
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#define interrupt_handler __visible noinline notrace __no_kcsan __no_sanitize_address
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/**
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* DECLARE_INTERRUPT_HANDLER_RAW - Declare raw interrupt handler function
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* @func: Function name of the entry point
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* @returns: Returns a value back to asm caller
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*/
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#define DECLARE_INTERRUPT_HANDLER_RAW(func) \
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__visible long func(struct pt_regs *regs)
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/**
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* DEFINE_INTERRUPT_HANDLER_RAW - Define raw interrupt handler function
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* @func: Function name of the entry point
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* @returns: Returns a value back to asm caller
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*
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* @func is called from ASM entry code.
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*
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* This is a plain function which does no tracing, reconciling, etc.
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* The macro is written so it acts as function definition. Append the
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* body with a pair of curly brackets.
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*
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* raw interrupt handlers must not enable or disable interrupts, or
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* schedule, tracing and instrumentation (ftrace, lockdep, etc) would
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* not be advisable either, although may be possible in a pinch, the
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* trace will look odd at least.
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*
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* A raw handler may call one of the other interrupt handler functions
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* to be converted into that interrupt context without these restrictions.
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*
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* On PPC64, _RAW handlers may return with fast_interrupt_return.
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*
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* Specific handlers may have additional restrictions.
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*/
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#define DEFINE_INTERRUPT_HANDLER_RAW(func) \
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static __always_inline __no_sanitize_address __no_kcsan long \
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____##func(struct pt_regs *regs); \
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\
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interrupt_handler long func(struct pt_regs *regs) \
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{ \
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long ret; \
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\
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__hard_RI_enable(); \
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\
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ret = ____##func (regs); \
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\
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return ret; \
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} \
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NOKPROBE_SYMBOL(func); \
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\
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static __always_inline __no_sanitize_address __no_kcsan long \
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____##func(struct pt_regs *regs)
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/**
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* DECLARE_INTERRUPT_HANDLER - Declare synchronous interrupt handler function
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* @func: Function name of the entry point
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*/
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#define DECLARE_INTERRUPT_HANDLER(func) \
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__visible void func(struct pt_regs *regs)
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/**
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* DEFINE_INTERRUPT_HANDLER - Define synchronous interrupt handler function
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* @func: Function name of the entry point
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*
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* @func is called from ASM entry code.
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*
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* The macro is written so it acts as function definition. Append the
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* body with a pair of curly brackets.
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*/
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#define DEFINE_INTERRUPT_HANDLER(func) \
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static __always_inline void ____##func(struct pt_regs *regs); \
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\
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interrupt_handler void func(struct pt_regs *regs) \
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{ \
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interrupt_enter_prepare(regs); \
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\
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____##func (regs); \
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\
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interrupt_exit_prepare(regs); \
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} \
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NOKPROBE_SYMBOL(func); \
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\
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static __always_inline void ____##func(struct pt_regs *regs)
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/**
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* DECLARE_INTERRUPT_HANDLER_RET - Declare synchronous interrupt handler function
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* @func: Function name of the entry point
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* @returns: Returns a value back to asm caller
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*/
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#define DECLARE_INTERRUPT_HANDLER_RET(func) \
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__visible long func(struct pt_regs *regs)
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/**
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* DEFINE_INTERRUPT_HANDLER_RET - Define synchronous interrupt handler function
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* @func: Function name of the entry point
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* @returns: Returns a value back to asm caller
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*
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* @func is called from ASM entry code.
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*
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* The macro is written so it acts as function definition. Append the
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* body with a pair of curly brackets.
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*/
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#define DEFINE_INTERRUPT_HANDLER_RET(func) \
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static __always_inline long ____##func(struct pt_regs *regs); \
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\
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interrupt_handler long func(struct pt_regs *regs) \
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{ \
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long ret; \
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\
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interrupt_enter_prepare(regs); \
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\
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ret = ____##func (regs); \
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\
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interrupt_exit_prepare(regs); \
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\
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return ret; \
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} \
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NOKPROBE_SYMBOL(func); \
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\
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static __always_inline long ____##func(struct pt_regs *regs)
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/**
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* DECLARE_INTERRUPT_HANDLER_ASYNC - Declare asynchronous interrupt handler function
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* @func: Function name of the entry point
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*/
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#define DECLARE_INTERRUPT_HANDLER_ASYNC(func) \
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__visible void func(struct pt_regs *regs)
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/**
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* DEFINE_INTERRUPT_HANDLER_ASYNC - Define asynchronous interrupt handler function
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* @func: Function name of the entry point
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*
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* @func is called from ASM entry code.
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*
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* The macro is written so it acts as function definition. Append the
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* body with a pair of curly brackets.
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*/
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#define DEFINE_INTERRUPT_HANDLER_ASYNC(func) \
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static __always_inline void ____##func(struct pt_regs *regs); \
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\
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interrupt_handler void func(struct pt_regs *regs) \
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{ \
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interrupt_async_enter_prepare(regs); \
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\
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____##func (regs); \
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\
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interrupt_async_exit_prepare(regs); \
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} \
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NOKPROBE_SYMBOL(func); \
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\
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static __always_inline void ____##func(struct pt_regs *regs)
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/**
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* DECLARE_INTERRUPT_HANDLER_NMI - Declare NMI interrupt handler function
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* @func: Function name of the entry point
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* @returns: Returns a value back to asm caller
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*/
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#define DECLARE_INTERRUPT_HANDLER_NMI(func) \
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__visible long func(struct pt_regs *regs)
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/**
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* DEFINE_INTERRUPT_HANDLER_NMI - Define NMI interrupt handler function
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* @func: Function name of the entry point
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* @returns: Returns a value back to asm caller
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*
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* @func is called from ASM entry code.
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*
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* The macro is written so it acts as function definition. Append the
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* body with a pair of curly brackets.
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*/
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#define DEFINE_INTERRUPT_HANDLER_NMI(func) \
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static __always_inline __no_sanitize_address __no_kcsan long \
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____##func(struct pt_regs *regs); \
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\
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interrupt_handler long func(struct pt_regs *regs) \
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{ \
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struct interrupt_nmi_state state; \
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long ret; \
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\
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interrupt_nmi_enter_prepare(regs, &state); \
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\
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ret = ____##func (regs); \
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\
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interrupt_nmi_exit_prepare(regs, &state); \
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\
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return ret; \
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} \
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NOKPROBE_SYMBOL(func); \
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\
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static __always_inline __no_sanitize_address __no_kcsan long \
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____##func(struct pt_regs *regs)
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/* Interrupt handlers */
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/* kernel/traps.c */
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DECLARE_INTERRUPT_HANDLER_NMI(system_reset_exception);
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#ifdef CONFIG_PPC_BOOK3S_64
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DECLARE_INTERRUPT_HANDLER_RAW(machine_check_early_boot);
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DECLARE_INTERRUPT_HANDLER_ASYNC(machine_check_exception_async);
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#endif
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DECLARE_INTERRUPT_HANDLER_NMI(machine_check_exception);
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DECLARE_INTERRUPT_HANDLER(SMIException);
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DECLARE_INTERRUPT_HANDLER(handle_hmi_exception);
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DECLARE_INTERRUPT_HANDLER(unknown_exception);
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DECLARE_INTERRUPT_HANDLER_ASYNC(unknown_async_exception);
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DECLARE_INTERRUPT_HANDLER_NMI(unknown_nmi_exception);
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DECLARE_INTERRUPT_HANDLER(instruction_breakpoint_exception);
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DECLARE_INTERRUPT_HANDLER(RunModeException);
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DECLARE_INTERRUPT_HANDLER(single_step_exception);
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DECLARE_INTERRUPT_HANDLER(program_check_exception);
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DECLARE_INTERRUPT_HANDLER(emulation_assist_interrupt);
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DECLARE_INTERRUPT_HANDLER(alignment_exception);
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DECLARE_INTERRUPT_HANDLER(StackOverflow);
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DECLARE_INTERRUPT_HANDLER(stack_overflow_exception);
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DECLARE_INTERRUPT_HANDLER(kernel_fp_unavailable_exception);
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DECLARE_INTERRUPT_HANDLER(altivec_unavailable_exception);
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DECLARE_INTERRUPT_HANDLER(vsx_unavailable_exception);
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DECLARE_INTERRUPT_HANDLER(facility_unavailable_exception);
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DECLARE_INTERRUPT_HANDLER(fp_unavailable_tm);
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DECLARE_INTERRUPT_HANDLER(altivec_unavailable_tm);
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DECLARE_INTERRUPT_HANDLER(vsx_unavailable_tm);
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DECLARE_INTERRUPT_HANDLER_NMI(performance_monitor_exception_nmi);
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DECLARE_INTERRUPT_HANDLER_ASYNC(performance_monitor_exception_async);
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DECLARE_INTERRUPT_HANDLER_RAW(performance_monitor_exception);
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DECLARE_INTERRUPT_HANDLER(DebugException);
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DECLARE_INTERRUPT_HANDLER(altivec_assist_exception);
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DECLARE_INTERRUPT_HANDLER(CacheLockingException);
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DECLARE_INTERRUPT_HANDLER(SPEFloatingPointException);
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DECLARE_INTERRUPT_HANDLER(SPEFloatingPointRoundException);
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DECLARE_INTERRUPT_HANDLER_NMI(WatchdogException);
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DECLARE_INTERRUPT_HANDLER(kernel_bad_stack);
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/* slb.c */
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DECLARE_INTERRUPT_HANDLER_RAW(do_slb_fault);
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DECLARE_INTERRUPT_HANDLER(do_bad_segment_interrupt);
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/* hash_utils.c */
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DECLARE_INTERRUPT_HANDLER(do_hash_fault);
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/* fault.c */
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DECLARE_INTERRUPT_HANDLER(do_page_fault);
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DECLARE_INTERRUPT_HANDLER(do_bad_page_fault_segv);
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/* process.c */
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DECLARE_INTERRUPT_HANDLER(do_break);
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/* time.c */
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DECLARE_INTERRUPT_HANDLER_ASYNC(timer_interrupt);
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/* mce.c */
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DECLARE_INTERRUPT_HANDLER_NMI(machine_check_early);
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DECLARE_INTERRUPT_HANDLER_NMI(hmi_exception_realmode);
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DECLARE_INTERRUPT_HANDLER_ASYNC(TAUException);
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/* irq.c */
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DECLARE_INTERRUPT_HANDLER_ASYNC(do_IRQ);
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void __noreturn unrecoverable_exception(struct pt_regs *regs);
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void replay_system_reset(void);
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void replay_soft_interrupts(void);
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static inline void interrupt_cond_local_irq_enable(struct pt_regs *regs)
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{
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if (!arch_irq_disabled_regs(regs))
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local_irq_enable();
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}
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long system_call_exception(struct pt_regs *regs, unsigned long r0);
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notrace unsigned long syscall_exit_prepare(unsigned long r3, struct pt_regs *regs, long scv);
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notrace unsigned long interrupt_exit_user_prepare(struct pt_regs *regs);
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notrace unsigned long interrupt_exit_kernel_prepare(struct pt_regs *regs);
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#ifdef CONFIG_PPC64
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unsigned long syscall_exit_restart(unsigned long r3, struct pt_regs *regs);
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unsigned long interrupt_exit_user_restart(struct pt_regs *regs);
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unsigned long interrupt_exit_kernel_restart(struct pt_regs *regs);
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#endif
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#endif /* __ASSEMBLY__ */
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#endif /* _ASM_POWERPC_INTERRUPT_H */
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