358 lines
11 KiB
C
358 lines
11 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Linux/PA-RISC Project (http://www.parisc-linux.org/)
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*
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* Floating-point emulation code
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* Copyright (C) 2001 Hewlett-Packard (Paul Bame) <bame@debian.org>
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*/
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/*
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* BEGIN_DESC
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*
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* File:
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* @(#) pa/fp/decode_exc.c $ Revision: $
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*
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* Purpose:
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* <<please update with a synopsis of the functionality provided by this file>>
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*
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* External Interfaces:
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* <<the following list was autogenerated, please review>>
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* decode_fpu(Fpu_register, trap_counts)
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*
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* Internal Interfaces:
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* <<please update>>
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*
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* Theory:
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* <<please update with a overview of the operation of this file>>
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*
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* END_DESC
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*/
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#include <linux/kernel.h>
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#include "float.h"
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#include "sgl_float.h"
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#include "dbl_float.h"
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#include "cnv_float.h"
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/* #include "types.h" */
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#include <asm/signal.h>
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#include <asm/siginfo.h>
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/* #include <machine/sys/mdep_private.h> */
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#undef Fpustatus_register
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#define Fpustatus_register Fpu_register[0]
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/* General definitions */
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#define DOESTRAP 1
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#define NOTRAP 0
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#define SIGNALCODE(signal, code) ((signal) << 24 | (code))
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#define copropbit 1<<31-2 /* bit position 2 */
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#define opclass 9 /* bits 21 & 22 */
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#define fmtbits 11 /* bits 19 & 20 */
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#define df 13 /* bits 17 & 18 */
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#define twobits 3 /* mask low-order 2 bits */
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#define fivebits 31 /* mask low-order 5 bits */
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#define MAX_EXCP_REG 7 /* number of excpeption registers to check */
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/* Exception register definitions */
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#define Excp_type(index) Exceptiontype(Fpu_register[index])
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#define Excp_instr(index) Instructionfield(Fpu_register[index])
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#define Clear_excp_register(index) Allexception(Fpu_register[index]) = 0
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#define Excp_format() \
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(current_ir >> ((current_ir>>opclass & twobits) == 1 ? df : fmtbits) & twobits)
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/* Miscellaneous definitions */
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#define Fpu_sgl(index) Fpu_register[index*2]
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#define Fpu_dblp1(index) Fpu_register[index*2]
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#define Fpu_dblp2(index) Fpu_register[(index*2)+1]
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#define Fpu_quadp1(index) Fpu_register[index*2]
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#define Fpu_quadp2(index) Fpu_register[(index*2)+1]
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#define Fpu_quadp3(index) Fpu_register[(index*2)+2]
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#define Fpu_quadp4(index) Fpu_register[(index*2)+3]
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/* Single precision floating-point definitions */
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#ifndef Sgl_decrement
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# define Sgl_decrement(sgl_value) Sall(sgl_value)--
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#endif
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/* Double precision floating-point definitions */
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#ifndef Dbl_decrement
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# define Dbl_decrement(dbl_valuep1,dbl_valuep2) \
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if ((Dallp2(dbl_valuep2)--) == 0) Dallp1(dbl_valuep1)--
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#endif
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#define update_trap_counts(Fpu_register, aflags, bflags, trap_counts) { \
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aflags=(Fpu_register[0])>>27; /* assumes zero fill. 32 bit */ \
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Fpu_register[0] |= bflags; \
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}
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u_int
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decode_fpu(unsigned int Fpu_register[], unsigned int trap_counts[])
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{
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unsigned int current_ir, excp;
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int target, exception_index = 1;
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boolean inexact;
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unsigned int aflags;
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unsigned int bflags;
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unsigned int excptype;
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/* Keep stats on how many floating point exceptions (based on type)
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* that happen. Want to keep this overhead low, but still provide
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* some information to the customer. All exits from this routine
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* need to restore Fpu_register[0]
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*/
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bflags=(Fpu_register[0] & 0xf8000000);
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Fpu_register[0] &= 0x07ffffff;
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/* exception_index is used to index the exception register queue. It
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* always points at the last register that contains a valid exception. A
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* zero value implies no exceptions (also the initialized value). Setting
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* the T-bit resets the exception_index to zero.
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*/
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/*
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* Check for reserved-op exception. A reserved-op exception does not
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* set any exception registers nor does it set the T-bit. If the T-bit
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* is not set then a reserved-op exception occurred.
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*
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* At some point, we may want to report reserved op exceptions as
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* illegal instructions.
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*/
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if (!Is_tbit_set()) {
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update_trap_counts(Fpu_register, aflags, bflags, trap_counts);
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return SIGNALCODE(SIGILL, ILL_COPROC);
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}
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/*
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* Is a coprocessor op.
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*
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* Now we need to determine what type of exception occurred.
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*/
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for (exception_index=1; exception_index<=MAX_EXCP_REG; exception_index++) {
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current_ir = Excp_instr(exception_index);
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/*
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* On PA89: there are 5 different unimplemented exception
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* codes: 0x1, 0x9, 0xb, 0x3, and 0x23. PA-RISC 2.0 adds
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* another, 0x2b. Only these have the low order bit set.
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*/
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excptype = Excp_type(exception_index);
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if (excptype & UNIMPLEMENTEDEXCEPTION) {
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/*
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* Clear T-bit and exception register so that
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* we can tell if a trap really occurs while
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* emulating the instruction.
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*/
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Clear_tbit();
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Clear_excp_register(exception_index);
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/*
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* Now emulate this instruction. If a trap occurs,
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* fpudispatch will return a non-zero number
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*/
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excp = fpudispatch(current_ir,excptype,0,Fpu_register);
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/* accumulate the status flags, don't lose them as in hpux */
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if (excp) {
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/*
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* We now need to make sure that the T-bit and the
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* exception register contain the correct values
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* before continuing.
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*/
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/*
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* Set t-bit since it might still be needed for a
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* subsequent real trap (I don't understand fully -PB)
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*/
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Set_tbit();
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/* some of the following code uses
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* Excp_type(exception_index) so fix that up */
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Set_exceptiontype_and_instr_field(excp,current_ir,
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Fpu_register[exception_index]);
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if (excp == UNIMPLEMENTEDEXCEPTION) {
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/*
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* it is really unimplemented, so restore the
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* TIMEX extended unimplemented exception code
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*/
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excp = excptype;
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update_trap_counts(Fpu_register, aflags, bflags,
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trap_counts);
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return SIGNALCODE(SIGILL, ILL_COPROC);
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}
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/* some of the following code uses excptype, so
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* fix that up too */
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excptype = excp;
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}
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/* handle exceptions other than the real UNIMPLIMENTED the
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* same way as if the hardware had caused them */
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if (excp == NOEXCEPTION)
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/* For now use 'break', should technically be 'continue' */
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break;
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}
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/*
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* In PA89, the underflow exception has been extended to encode
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* additional information. The exception looks like pp01x0,
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* where x is 1 if inexact and pp represent the inexact bit (I)
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* and the round away bit (RA)
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*/
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if (excptype & UNDERFLOWEXCEPTION) {
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/* check for underflow trap enabled */
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if (Is_underflowtrap_enabled()) {
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update_trap_counts(Fpu_register, aflags, bflags,
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trap_counts);
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return SIGNALCODE(SIGFPE, FPE_FLTUND);
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} else {
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/*
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* Isn't a real trap; we need to
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* return the default value.
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*/
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target = current_ir & fivebits;
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#ifndef lint
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if (Ibit(Fpu_register[exception_index])) inexact = TRUE;
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else inexact = FALSE;
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#endif
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switch (Excp_format()) {
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case SGL:
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/*
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* If ra (round-away) is set, will
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* want to undo the rounding done
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* by the hardware.
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*/
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if (Rabit(Fpu_register[exception_index]))
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Sgl_decrement(Fpu_sgl(target));
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/* now denormalize */
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sgl_denormalize(&Fpu_sgl(target),&inexact,Rounding_mode());
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break;
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case DBL:
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/*
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* If ra (round-away) is set, will
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* want to undo the rounding done
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* by the hardware.
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*/
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if (Rabit(Fpu_register[exception_index]))
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Dbl_decrement(Fpu_dblp1(target),Fpu_dblp2(target));
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/* now denormalize */
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dbl_denormalize(&Fpu_dblp1(target),&Fpu_dblp2(target),
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&inexact,Rounding_mode());
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break;
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}
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if (inexact) Set_underflowflag();
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/*
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* Underflow can generate an inexact
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* exception. If inexact trap is enabled,
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* want to do an inexact trap, otherwise
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* set inexact flag.
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*/
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if (inexact && Is_inexacttrap_enabled()) {
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/*
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* Set exception field of exception register
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* to inexact, parm field to zero.
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* Underflow bit should be cleared.
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*/
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Set_exceptiontype(Fpu_register[exception_index],
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INEXACTEXCEPTION);
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Set_parmfield(Fpu_register[exception_index],0);
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update_trap_counts(Fpu_register, aflags, bflags,
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trap_counts);
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return SIGNALCODE(SIGFPE, FPE_FLTRES);
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}
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else {
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/*
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* Exception register needs to be cleared.
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* Inexact flag needs to be set if inexact.
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*/
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Clear_excp_register(exception_index);
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if (inexact) Set_inexactflag();
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}
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}
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continue;
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}
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switch(Excp_type(exception_index)) {
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case OVERFLOWEXCEPTION:
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case OVERFLOWEXCEPTION | INEXACTEXCEPTION:
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/* check for overflow trap enabled */
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update_trap_counts(Fpu_register, aflags, bflags,
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trap_counts);
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if (Is_overflowtrap_enabled()) {
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update_trap_counts(Fpu_register, aflags, bflags,
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trap_counts);
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return SIGNALCODE(SIGFPE, FPE_FLTOVF);
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} else {
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/*
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* Isn't a real trap; we need to
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* return the default value.
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*/
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target = current_ir & fivebits;
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switch (Excp_format()) {
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case SGL:
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Sgl_setoverflow(Fpu_sgl(target));
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break;
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case DBL:
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Dbl_setoverflow(Fpu_dblp1(target),Fpu_dblp2(target));
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break;
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}
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Set_overflowflag();
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/*
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* Overflow always generates an inexact
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* exception. If inexact trap is enabled,
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* want to do an inexact trap, otherwise
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* set inexact flag.
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*/
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if (Is_inexacttrap_enabled()) {
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/*
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* Set exception field of exception
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* register to inexact. Overflow
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* bit should be cleared.
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*/
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Set_exceptiontype(Fpu_register[exception_index],
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INEXACTEXCEPTION);
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update_trap_counts(Fpu_register, aflags, bflags,
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trap_counts);
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return SIGNALCODE(SIGFPE, FPE_FLTRES);
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}
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else {
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/*
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* Exception register needs to be cleared.
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* Inexact flag needs to be set.
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*/
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Clear_excp_register(exception_index);
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Set_inexactflag();
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}
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}
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break;
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case INVALIDEXCEPTION:
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case OPC_2E_INVALIDEXCEPTION:
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update_trap_counts(Fpu_register, aflags, bflags, trap_counts);
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return SIGNALCODE(SIGFPE, FPE_FLTINV);
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case DIVISIONBYZEROEXCEPTION:
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update_trap_counts(Fpu_register, aflags, bflags, trap_counts);
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Clear_excp_register(exception_index);
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return SIGNALCODE(SIGFPE, FPE_FLTDIV);
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case INEXACTEXCEPTION:
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update_trap_counts(Fpu_register, aflags, bflags, trap_counts);
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return SIGNALCODE(SIGFPE, FPE_FLTRES);
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default:
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update_trap_counts(Fpu_register, aflags, bflags, trap_counts);
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printk("%s(%d) Unknown FPU exception 0x%x\n", __FILE__,
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__LINE__, Excp_type(exception_index));
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return SIGNALCODE(SIGILL, ILL_COPROC);
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case NOEXCEPTION: /* no exception */
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/*
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* Clear exception register in case
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* other fields are non-zero.
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*/
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Clear_excp_register(exception_index);
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break;
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}
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}
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/*
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* No real exceptions occurred.
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*/
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Clear_tbit();
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update_trap_counts(Fpu_register, aflags, bflags, trap_counts);
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return(NOTRAP);
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}
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