489 lines
14 KiB
C
489 lines
14 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* ip28-berr.c: Bus error handling.
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*
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* Copyright (C) 2002, 2003 Ladislav Michl (ladis@linux-mips.org)
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* Copyright (C) 2005 Peter Fuerst (pf@net.alphadv.de) - IP28
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*/
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/mm.h>
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#include <linux/sched.h>
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#include <linux/sched/debug.h>
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#include <linux/sched/signal.h>
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#include <linux/seq_file.h>
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#include <asm/addrspace.h>
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#include <asm/traps.h>
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#include <asm/branch.h>
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#include <asm/irq_regs.h>
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#include <asm/sgi/mc.h>
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#include <asm/sgi/hpc3.h>
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#include <asm/sgi/ioc.h>
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#include <asm/sgi/ip22.h>
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#include <asm/r4kcache.h>
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#include <linux/uaccess.h>
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#include <asm/bootinfo.h>
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static unsigned int count_be_is_fixup;
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static unsigned int count_be_handler;
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static unsigned int count_be_interrupt;
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static int debug_be_interrupt;
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static unsigned int cpu_err_stat; /* Status reg for CPU */
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static unsigned int gio_err_stat; /* Status reg for GIO */
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static unsigned int cpu_err_addr; /* Error address reg for CPU */
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static unsigned int gio_err_addr; /* Error address reg for GIO */
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static unsigned int extio_stat;
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static unsigned int hpc3_berr_stat; /* Bus error interrupt status */
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struct hpc3_stat {
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unsigned long addr;
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unsigned int ctrl;
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unsigned int cbp;
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unsigned int ndptr;
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};
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static struct {
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struct hpc3_stat pbdma[8];
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struct hpc3_stat scsi[2];
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struct hpc3_stat ethrx, ethtx;
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} hpc3;
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static struct {
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unsigned long err_addr;
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struct {
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u32 lo;
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u32 hi;
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} tags[1][2], tagd[4][2], tagi[4][2]; /* Way 0/1 */
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} cache_tags;
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static inline void save_cache_tags(unsigned busaddr)
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{
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unsigned long addr = CAC_BASE | busaddr;
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int i;
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cache_tags.err_addr = addr;
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/*
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* Starting with a bus-address, save secondary cache (indexed by
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* PA[23..18:7..6]) tags first.
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*/
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addr &= ~1L;
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#define tag cache_tags.tags[0]
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cache_op(Index_Load_Tag_S, addr);
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tag[0].lo = read_c0_taglo(); /* PA[35:18], VA[13:12] */
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tag[0].hi = read_c0_taghi(); /* PA[39:36] */
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cache_op(Index_Load_Tag_S, addr | 1L);
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tag[1].lo = read_c0_taglo(); /* PA[35:18], VA[13:12] */
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tag[1].hi = read_c0_taghi(); /* PA[39:36] */
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#undef tag
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/*
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* Save all primary data cache (indexed by VA[13:5]) tags which
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* might fit to this bus-address, knowing that VA[11:0] == PA[11:0].
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* Saving all tags and evaluating them later is easier and safer
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* than relying on VA[13:12] from the secondary cache tags to pick
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* matching primary tags here already.
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*/
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addr &= (0xffL << 56) | ((1 << 12) - 1);
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#define tag cache_tags.tagd[i]
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for (i = 0; i < 4; ++i, addr += (1 << 12)) {
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cache_op(Index_Load_Tag_D, addr);
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tag[0].lo = read_c0_taglo(); /* PA[35:12] */
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tag[0].hi = read_c0_taghi(); /* PA[39:36] */
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cache_op(Index_Load_Tag_D, addr | 1L);
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tag[1].lo = read_c0_taglo(); /* PA[35:12] */
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tag[1].hi = read_c0_taghi(); /* PA[39:36] */
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}
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#undef tag
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/*
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* Save primary instruction cache (indexed by VA[13:6]) tags
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* the same way.
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*/
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addr &= (0xffL << 56) | ((1 << 12) - 1);
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#define tag cache_tags.tagi[i]
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for (i = 0; i < 4; ++i, addr += (1 << 12)) {
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cache_op(Index_Load_Tag_I, addr);
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tag[0].lo = read_c0_taglo(); /* PA[35:12] */
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tag[0].hi = read_c0_taghi(); /* PA[39:36] */
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cache_op(Index_Load_Tag_I, addr | 1L);
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tag[1].lo = read_c0_taglo(); /* PA[35:12] */
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tag[1].hi = read_c0_taghi(); /* PA[39:36] */
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}
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#undef tag
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}
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#define GIO_ERRMASK 0xff00
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#define CPU_ERRMASK 0x3f00
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static void save_and_clear_buserr(void)
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{
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int i;
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/* save status registers */
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cpu_err_addr = sgimc->cerr;
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cpu_err_stat = sgimc->cstat;
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gio_err_addr = sgimc->gerr;
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gio_err_stat = sgimc->gstat;
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extio_stat = sgioc->extio;
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hpc3_berr_stat = hpc3c0->bestat;
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hpc3.scsi[0].addr = (unsigned long)&hpc3c0->scsi_chan0;
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hpc3.scsi[0].ctrl = hpc3c0->scsi_chan0.ctrl; /* HPC3_SCTRL_ACTIVE ? */
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hpc3.scsi[0].cbp = hpc3c0->scsi_chan0.cbptr;
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hpc3.scsi[0].ndptr = hpc3c0->scsi_chan0.ndptr;
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hpc3.scsi[1].addr = (unsigned long)&hpc3c0->scsi_chan1;
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hpc3.scsi[1].ctrl = hpc3c0->scsi_chan1.ctrl; /* HPC3_SCTRL_ACTIVE ? */
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hpc3.scsi[1].cbp = hpc3c0->scsi_chan1.cbptr;
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hpc3.scsi[1].ndptr = hpc3c0->scsi_chan1.ndptr;
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hpc3.ethrx.addr = (unsigned long)&hpc3c0->ethregs.rx_cbptr;
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hpc3.ethrx.ctrl = hpc3c0->ethregs.rx_ctrl; /* HPC3_ERXCTRL_ACTIVE ? */
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hpc3.ethrx.cbp = hpc3c0->ethregs.rx_cbptr;
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hpc3.ethrx.ndptr = hpc3c0->ethregs.rx_ndptr;
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hpc3.ethtx.addr = (unsigned long)&hpc3c0->ethregs.tx_cbptr;
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hpc3.ethtx.ctrl = hpc3c0->ethregs.tx_ctrl; /* HPC3_ETXCTRL_ACTIVE ? */
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hpc3.ethtx.cbp = hpc3c0->ethregs.tx_cbptr;
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hpc3.ethtx.ndptr = hpc3c0->ethregs.tx_ndptr;
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for (i = 0; i < 8; ++i) {
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/* HPC3_PDMACTRL_ISACT ? */
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hpc3.pbdma[i].addr = (unsigned long)&hpc3c0->pbdma[i];
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hpc3.pbdma[i].ctrl = hpc3c0->pbdma[i].pbdma_ctrl;
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hpc3.pbdma[i].cbp = hpc3c0->pbdma[i].pbdma_bptr;
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hpc3.pbdma[i].ndptr = hpc3c0->pbdma[i].pbdma_dptr;
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}
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i = 0;
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if (gio_err_stat & CPU_ERRMASK)
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i = gio_err_addr;
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if (cpu_err_stat & CPU_ERRMASK)
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i = cpu_err_addr;
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save_cache_tags(i);
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sgimc->cstat = sgimc->gstat = 0;
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}
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static void print_cache_tags(void)
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{
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u32 scb, scw;
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int i;
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printk(KERN_ERR "Cache tags @ %08x:\n", (unsigned)cache_tags.err_addr);
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/* PA[31:12] shifted to PTag0 (PA[35:12]) format */
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scw = (cache_tags.err_addr >> 4) & 0x0fffff00;
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scb = cache_tags.err_addr & ((1 << 12) - 1) & ~((1 << 5) - 1);
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for (i = 0; i < 4; ++i) { /* for each possible VA[13:12] value */
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if ((cache_tags.tagd[i][0].lo & 0x0fffff00) != scw &&
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(cache_tags.tagd[i][1].lo & 0x0fffff00) != scw)
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continue;
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printk(KERN_ERR
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"D: 0: %08x %08x, 1: %08x %08x (VA[13:5] %04x)\n",
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cache_tags.tagd[i][0].hi, cache_tags.tagd[i][0].lo,
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cache_tags.tagd[i][1].hi, cache_tags.tagd[i][1].lo,
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scb | (1 << 12)*i);
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}
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scb = cache_tags.err_addr & ((1 << 12) - 1) & ~((1 << 6) - 1);
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for (i = 0; i < 4; ++i) { /* for each possible VA[13:12] value */
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if ((cache_tags.tagi[i][0].lo & 0x0fffff00) != scw &&
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(cache_tags.tagi[i][1].lo & 0x0fffff00) != scw)
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continue;
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printk(KERN_ERR
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"I: 0: %08x %08x, 1: %08x %08x (VA[13:6] %04x)\n",
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cache_tags.tagi[i][0].hi, cache_tags.tagi[i][0].lo,
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cache_tags.tagi[i][1].hi, cache_tags.tagi[i][1].lo,
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scb | (1 << 12)*i);
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}
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i = read_c0_config();
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scb = i & (1 << 13) ? 7:6; /* scblksize = 2^[7..6] */
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scw = ((i >> 16) & 7) + 19 - 1; /* scwaysize = 2^[24..19] / 2 */
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i = ((1 << scw) - 1) & ~((1 << scb) - 1);
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printk(KERN_ERR "S: 0: %08x %08x, 1: %08x %08x (PA[%u:%u] %05x)\n",
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cache_tags.tags[0][0].hi, cache_tags.tags[0][0].lo,
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cache_tags.tags[0][1].hi, cache_tags.tags[0][1].lo,
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scw-1, scb, i & (unsigned)cache_tags.err_addr);
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}
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static inline const char *cause_excode_text(int cause)
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{
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static const char *txt[32] =
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{ "Interrupt",
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"TLB modification",
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"TLB (load or instruction fetch)",
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"TLB (store)",
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"Address error (load or instruction fetch)",
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"Address error (store)",
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"Bus error (instruction fetch)",
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"Bus error (data: load or store)",
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"Syscall",
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"Breakpoint",
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"Reserved instruction",
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"Coprocessor unusable",
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"Arithmetic Overflow",
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"Trap",
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"14",
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"Floating-Point",
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"16", "17", "18", "19", "20", "21", "22",
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"Watch Hi/Lo",
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"24", "25", "26", "27", "28", "29", "30", "31",
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};
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return txt[(cause & 0x7c) >> 2];
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}
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static void print_buserr(const struct pt_regs *regs)
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{
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const int field = 2 * sizeof(unsigned long);
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int error = 0;
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if (extio_stat & EXTIO_MC_BUSERR) {
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printk(KERN_ERR "MC Bus Error\n");
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error |= 1;
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}
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if (extio_stat & EXTIO_HPC3_BUSERR) {
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printk(KERN_ERR "HPC3 Bus Error 0x%x:<id=0x%x,%s,lane=0x%x>\n",
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hpc3_berr_stat,
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(hpc3_berr_stat & HPC3_BESTAT_PIDMASK) >>
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HPC3_BESTAT_PIDSHIFT,
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(hpc3_berr_stat & HPC3_BESTAT_CTYPE) ? "PIO" : "DMA",
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hpc3_berr_stat & HPC3_BESTAT_BLMASK);
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error |= 2;
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}
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if (extio_stat & EXTIO_EISA_BUSERR) {
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printk(KERN_ERR "EISA Bus Error\n");
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error |= 4;
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}
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if (cpu_err_stat & CPU_ERRMASK) {
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printk(KERN_ERR "CPU error 0x%x<%s%s%s%s%s%s> @ 0x%08x\n",
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cpu_err_stat,
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cpu_err_stat & SGIMC_CSTAT_RD ? "RD " : "",
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cpu_err_stat & SGIMC_CSTAT_PAR ? "PAR " : "",
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cpu_err_stat & SGIMC_CSTAT_ADDR ? "ADDR " : "",
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cpu_err_stat & SGIMC_CSTAT_SYSAD_PAR ? "SYSAD " : "",
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cpu_err_stat & SGIMC_CSTAT_SYSCMD_PAR ? "SYSCMD " : "",
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cpu_err_stat & SGIMC_CSTAT_BAD_DATA ? "BAD_DATA " : "",
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cpu_err_addr);
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error |= 8;
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}
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if (gio_err_stat & GIO_ERRMASK) {
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printk(KERN_ERR "GIO error 0x%x:<%s%s%s%s%s%s%s%s> @ 0x%08x\n",
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gio_err_stat,
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gio_err_stat & SGIMC_GSTAT_RD ? "RD " : "",
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gio_err_stat & SGIMC_GSTAT_WR ? "WR " : "",
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gio_err_stat & SGIMC_GSTAT_TIME ? "TIME " : "",
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gio_err_stat & SGIMC_GSTAT_PROM ? "PROM " : "",
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gio_err_stat & SGIMC_GSTAT_ADDR ? "ADDR " : "",
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gio_err_stat & SGIMC_GSTAT_BC ? "BC " : "",
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gio_err_stat & SGIMC_GSTAT_PIO_RD ? "PIO_RD " : "",
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gio_err_stat & SGIMC_GSTAT_PIO_WR ? "PIO_WR " : "",
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gio_err_addr);
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error |= 16;
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}
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if (!error)
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printk(KERN_ERR "MC: Hmm, didn't find any error condition.\n");
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else {
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printk(KERN_ERR "CP0: config %08x, "
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"MC: cpuctrl0/1: %08x/%05x, giopar: %04x\n"
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"MC: cpu/gio_memacc: %08x/%05x, memcfg0/1: %08x/%08x\n",
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read_c0_config(),
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sgimc->cpuctrl0, sgimc->cpuctrl0, sgimc->giopar,
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sgimc->cmacc, sgimc->gmacc,
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sgimc->mconfig0, sgimc->mconfig1);
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print_cache_tags();
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}
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printk(KERN_ALERT "%s, epc == %0*lx, ra == %0*lx\n",
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cause_excode_text(regs->cp0_cause),
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field, regs->cp0_epc, field, regs->regs[31]);
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}
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static int check_microtlb(u32 hi, u32 lo, unsigned long vaddr)
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{
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/* This is likely rather similar to correct code ;-) */
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vaddr &= 0x7fffffff; /* Doc. states that top bit is ignored */
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/* If tlb-entry is valid and VPN-high (bits [30:21] ?) matches... */
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if ((lo & 2) && (vaddr >> 21) == ((hi<<1) >> 22)) {
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u32 ctl = sgimc->dma_ctrl;
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if (ctl & 1) {
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unsigned int pgsz = (ctl & 2) ? 14:12; /* 16k:4k */
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/* PTEIndex is VPN-low (bits [22:14]/[20:12] ?) */
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unsigned long pte = (lo >> 6) << 12; /* PTEBase */
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pte += 8*((vaddr >> pgsz) & 0x1ff);
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if (page_is_ram(PFN_DOWN(pte))) {
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/*
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* Note: Since DMA hardware does look up
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* translation on its own, this PTE *must*
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* match the TLB/EntryLo-register format !
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*/
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unsigned long a = *(unsigned long *)
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PHYS_TO_XKSEG_UNCACHED(pte);
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a = (a & 0x3f) << 6; /* PFN */
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a += vaddr & ((1 << pgsz) - 1);
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return cpu_err_addr == a;
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}
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}
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}
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return 0;
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}
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static int check_vdma_memaddr(void)
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{
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if (cpu_err_stat & CPU_ERRMASK) {
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u32 a = sgimc->maddronly;
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if (!(sgimc->dma_ctrl & 0x100)) /* Xlate-bit clear ? */
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return cpu_err_addr == a;
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if (check_microtlb(sgimc->dtlb_hi0, sgimc->dtlb_lo0, a) ||
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check_microtlb(sgimc->dtlb_hi1, sgimc->dtlb_lo1, a) ||
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check_microtlb(sgimc->dtlb_hi2, sgimc->dtlb_lo2, a) ||
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check_microtlb(sgimc->dtlb_hi3, sgimc->dtlb_lo3, a))
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return 1;
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}
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return 0;
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}
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static int check_vdma_gioaddr(void)
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{
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if (gio_err_stat & GIO_ERRMASK) {
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u32 a = sgimc->gio_dma_trans;
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a = (sgimc->gmaddronly & ~a) | (sgimc->gio_dma_sbits & a);
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return gio_err_addr == a;
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}
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return 0;
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}
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/*
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* MC sends an interrupt whenever bus or parity errors occur. In addition,
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* if the error happened during a CPU read, it also asserts the bus error
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* pin on the R4K. Code in bus error handler save the MC bus error registers
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* and then clear the interrupt when this happens.
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*/
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static int ip28_be_interrupt(const struct pt_regs *regs)
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{
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int i;
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save_and_clear_buserr();
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/*
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* Try to find out, whether we got here by a mispredicted speculative
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* load/store operation. If so, it's not fatal, we can go on.
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*/
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/* Any cause other than "Interrupt" (ExcCode 0) is fatal. */
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if (regs->cp0_cause & CAUSEF_EXCCODE)
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goto mips_be_fatal;
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/* Any cause other than "Bus error interrupt" (IP6) is weird. */
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if ((regs->cp0_cause & CAUSEF_IP6) != CAUSEF_IP6)
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goto mips_be_fatal;
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if (extio_stat & (EXTIO_HPC3_BUSERR | EXTIO_EISA_BUSERR))
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goto mips_be_fatal;
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/* Any state other than "Memory bus error" is fatal. */
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if (cpu_err_stat & CPU_ERRMASK & ~SGIMC_CSTAT_ADDR)
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goto mips_be_fatal;
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/* GIO errors other than timeouts are fatal */
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if (gio_err_stat & GIO_ERRMASK & ~SGIMC_GSTAT_TIME)
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goto mips_be_fatal;
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/*
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* Now we have an asynchronous bus error, speculatively or DMA caused.
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* Need to search all DMA descriptors for the error address.
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*/
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for (i = 0; i < sizeof(hpc3)/sizeof(struct hpc3_stat); ++i) {
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struct hpc3_stat *hp = (struct hpc3_stat *)&hpc3 + i;
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if ((cpu_err_stat & CPU_ERRMASK) &&
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(cpu_err_addr == hp->ndptr || cpu_err_addr == hp->cbp))
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break;
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if ((gio_err_stat & GIO_ERRMASK) &&
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(gio_err_addr == hp->ndptr || gio_err_addr == hp->cbp))
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break;
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}
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if (i < sizeof(hpc3)/sizeof(struct hpc3_stat)) {
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struct hpc3_stat *hp = (struct hpc3_stat *)&hpc3 + i;
|
|
printk(KERN_ERR "at DMA addresses: HPC3 @ %08lx:"
|
|
" ctl %08x, ndp %08x, cbp %08x\n",
|
|
CPHYSADDR(hp->addr), hp->ctrl, hp->ndptr, hp->cbp);
|
|
goto mips_be_fatal;
|
|
}
|
|
/* Check MC's virtual DMA stuff. */
|
|
if (check_vdma_memaddr()) {
|
|
printk(KERN_ERR "at GIO DMA: mem address 0x%08x.\n",
|
|
sgimc->maddronly);
|
|
goto mips_be_fatal;
|
|
}
|
|
if (check_vdma_gioaddr()) {
|
|
printk(KERN_ERR "at GIO DMA: gio address 0x%08x.\n",
|
|
sgimc->gmaddronly);
|
|
goto mips_be_fatal;
|
|
}
|
|
/* A speculative bus error... */
|
|
if (debug_be_interrupt) {
|
|
print_buserr(regs);
|
|
printk(KERN_ERR "discarded!\n");
|
|
}
|
|
return MIPS_BE_DISCARD;
|
|
|
|
mips_be_fatal:
|
|
print_buserr(regs);
|
|
return MIPS_BE_FATAL;
|
|
}
|
|
|
|
void ip22_be_interrupt(int irq)
|
|
{
|
|
struct pt_regs *regs = get_irq_regs();
|
|
|
|
count_be_interrupt++;
|
|
|
|
if (ip28_be_interrupt(regs) != MIPS_BE_DISCARD) {
|
|
/* Assume it would be too dangerous to continue ... */
|
|
die_if_kernel("Oops", regs);
|
|
force_sig(SIGBUS);
|
|
} else if (debug_be_interrupt)
|
|
show_regs(regs);
|
|
}
|
|
|
|
static int ip28_be_handler(struct pt_regs *regs, int is_fixup)
|
|
{
|
|
/*
|
|
* We arrive here only in the unusual case of do_be() invocation,
|
|
* i.e. by a bus error exception without a bus error interrupt.
|
|
*/
|
|
if (is_fixup) {
|
|
count_be_is_fixup++;
|
|
save_and_clear_buserr();
|
|
return MIPS_BE_FIXUP;
|
|
}
|
|
count_be_handler++;
|
|
return ip28_be_interrupt(regs);
|
|
}
|
|
|
|
void __init ip22_be_init(void)
|
|
{
|
|
mips_set_be_handler(ip28_be_handler);
|
|
}
|
|
|
|
int ip28_show_be_info(struct seq_file *m)
|
|
{
|
|
seq_printf(m, "IP28 be fixups\t\t: %u\n", count_be_is_fixup);
|
|
seq_printf(m, "IP28 be interrupts\t: %u\n", count_be_interrupt);
|
|
seq_printf(m, "IP28 be handler\t\t: %u\n", count_be_handler);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int __init debug_be_setup(char *str)
|
|
{
|
|
debug_be_interrupt++;
|
|
return 1;
|
|
}
|
|
__setup("ip28_debug_be", debug_be_setup);
|