143 lines
4.5 KiB
C
143 lines
4.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Based on arch/arm/include/asm/cacheflush.h
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*
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* Copyright (C) 1999-2002 Russell King.
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* Copyright (C) 2012 ARM Ltd.
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*/
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#ifndef __ASM_CACHEFLUSH_H
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#define __ASM_CACHEFLUSH_H
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#include <linux/kgdb.h>
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#include <linux/mm.h>
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/*
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* This flag is used to indicate that the page pointed to by a pte is clean
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* and does not require cleaning before returning it to the user.
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*/
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#define PG_dcache_clean PG_arch_1
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/*
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* MM Cache Management
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* ===================
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*
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* The arch/arm64/mm/cache.S implements these methods.
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*
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* Start addresses are inclusive and end addresses are exclusive; start
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* addresses should be rounded down, end addresses up.
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*
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* See Documentation/core-api/cachetlb.rst for more information. Please note that
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* the implementation assumes non-aliasing VIPT D-cache and (aliasing)
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* VIPT I-cache.
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*
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* All functions below apply to the interval [start, end)
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* - start - virtual start address (inclusive)
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* - end - virtual end address (exclusive)
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*
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* caches_clean_inval_pou(start, end)
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*
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* Ensure coherency between the I-cache and the D-cache region to
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* the Point of Unification.
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*
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* caches_clean_inval_user_pou(start, end)
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*
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* Ensure coherency between the I-cache and the D-cache region to
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* the Point of Unification.
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* Use only if the region might access user memory.
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*
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* icache_inval_pou(start, end)
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*
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* Invalidate I-cache region to the Point of Unification.
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*
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* dcache_clean_inval_poc(start, end)
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*
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* Clean and invalidate D-cache region to the Point of Coherency.
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*
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* dcache_inval_poc(start, end)
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*
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* Invalidate D-cache region to the Point of Coherency.
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*
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* dcache_clean_poc(start, end)
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*
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* Clean D-cache region to the Point of Coherency.
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*
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* dcache_clean_pop(start, end)
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*
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* Clean D-cache region to the Point of Persistence.
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*
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* dcache_clean_pou(start, end)
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*
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* Clean D-cache region to the Point of Unification.
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*/
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extern void caches_clean_inval_pou(unsigned long start, unsigned long end);
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extern void icache_inval_pou(unsigned long start, unsigned long end);
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extern void dcache_clean_inval_poc(unsigned long start, unsigned long end);
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extern void dcache_inval_poc(unsigned long start, unsigned long end);
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extern void dcache_clean_poc(unsigned long start, unsigned long end);
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extern void dcache_clean_pop(unsigned long start, unsigned long end);
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extern void dcache_clean_pou(unsigned long start, unsigned long end);
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extern long caches_clean_inval_user_pou(unsigned long start, unsigned long end);
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extern void sync_icache_aliases(unsigned long start, unsigned long end);
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static inline void flush_icache_range(unsigned long start, unsigned long end)
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{
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caches_clean_inval_pou(start, end);
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/*
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* IPI all online CPUs so that they undergo a context synchronization
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* event and are forced to refetch the new instructions.
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*/
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/*
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* KGDB performs cache maintenance with interrupts disabled, so we
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* will deadlock trying to IPI the secondary CPUs. In theory, we can
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* set CACHE_FLUSH_IS_SAFE to 0 to avoid this known issue, but that
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* just means that KGDB will elide the maintenance altogether! As it
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* turns out, KGDB uses IPIs to round-up the secondary CPUs during
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* the patching operation, so we don't need extra IPIs here anyway.
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* In which case, add a KGDB-specific bodge and return early.
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*/
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if (in_dbg_master())
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return;
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kick_all_cpus_sync();
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}
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#define flush_icache_range flush_icache_range
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/*
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* Copy user data from/to a page which is mapped into a different
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* processes address space. Really, we want to allow our "user
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* space" model to handle this.
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*/
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extern void copy_to_user_page(struct vm_area_struct *, struct page *,
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unsigned long, void *, const void *, unsigned long);
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#define copy_to_user_page copy_to_user_page
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/*
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* flush_dcache_page is used when the kernel has written to the page
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* cache page at virtual address page->virtual.
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*
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* If this page isn't mapped (ie, page_mapping == NULL), or it might
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* have userspace mappings, then we _must_ always clean + invalidate
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* the dcache entries associated with the kernel mapping.
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*
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* Otherwise we can defer the operation, and clean the cache when we are
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* about to change to user space. This is the same method as used on SPARC64.
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* See update_mmu_cache for the user space part.
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*/
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#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1
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extern void flush_dcache_page(struct page *);
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static __always_inline void icache_inval_all_pou(void)
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{
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if (cpus_have_const_cap(ARM64_HAS_CACHE_DIC))
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return;
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asm("ic ialluis");
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dsb(ish);
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}
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#include <asm-generic/cacheflush.h>
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#endif /* __ASM_CACHEFLUSH_H */
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