143 lines
3.8 KiB
Plaintext
143 lines
3.8 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2019~2020, 2022 NXP
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*/
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/delete-node/ &enet1_lpcg;
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/delete-node/ &fec2;
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&conn_subsys {
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conn_enet0_root_clk: clock-conn-enet0-root {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <250000000>;
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clock-output-names = "conn_enet0_root_clk";
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};
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eqos: ethernet@5b050000 {
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compatible = "nxp,imx8dxl-dwmac-eqos", "snps,dwmac-5.10a";
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reg = <0x5b050000 0x10000>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "eth_wake_irq", "macirq";
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clocks = <&eqos_lpcg IMX_LPCG_CLK_4>,
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<&eqos_lpcg IMX_LPCG_CLK_6>,
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<&eqos_lpcg IMX_LPCG_CLK_0>,
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<&eqos_lpcg IMX_LPCG_CLK_5>,
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<&eqos_lpcg IMX_LPCG_CLK_2>;
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clock-names = "stmmaceth", "pclk", "ptp_ref", "tx", "mem";
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assigned-clocks = <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>;
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assigned-clock-rates = <125000000>;
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power-domains = <&pd IMX_SC_R_ENET_1>;
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status = "disabled";
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};
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usbotg2: usb@5b0e0000 {
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compatible = "fsl,imx8dxl-usb", "fsl,imx7ulp-usb";
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reg = <0x5b0e0000 0x200>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
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fsl,usbphy = <&usbphy2>;
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fsl,usbmisc = <&usbmisc2 0>;
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/*
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* usbotg1 and usbotg2 share one clcok.
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* scu firmware disables the access to the clock and keeps
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* it always on in case other core (M4) uses one of these.
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*/
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clocks = <&clk_dummy>;
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ahb-burst-config = <0x0>;
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tx-burst-size-dword = <0x10>;
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rx-burst-size-dword = <0x10>;
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#stream-id-cells = <1>;
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power-domains = <&pd IMX_SC_R_USB_1>;
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status = "disabled";
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clk_dummy: clock-dummy {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <0>;
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clock-output-names = "clk_dummy";
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};
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};
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usbmisc2: usbmisc@5b0e0200 {
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#index-cells = <1>;
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compatible = "fsl,imx7ulp-usbmisc";
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reg = <0x5b0e0200 0x200>;
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};
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usbphy2: usbphy@0x5b110000 {
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compatible = "fsl,imx8dxl-usbphy", "fsl,imx7ulp-usbphy";
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reg = <0x5b110000 0x1000>;
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clocks = <&usb2_2_lpcg IMX_LPCG_CLK_7>;
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power-domains = <&pd IMX_SC_R_USB_1_PHY>;
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status = "disabled";
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};
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eqos_lpcg: clock-controller@5b240000 {
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compatible = "fsl,imx8qxp-lpcg";
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reg = <0x5b240000 0x10000>;
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#clock-cells = <1>;
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clocks = <&conn_enet0_root_clk>,
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<&conn_axi_clk>,
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<&conn_axi_clk>,
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<&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>,
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<&conn_ipg_clk>;
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clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_2>,
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<IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>,
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<IMX_LPCG_CLK_6>;
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clock-output-names = "eqos_ptp",
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"eqos_mem_clk",
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"eqos_aclk",
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"eqos_clk",
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"eqos_csr_clk";
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power-domains = <&pd IMX_SC_R_ENET_1>;
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};
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usb2_2_lpcg: clock-controller@5b280000 {
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compatible = "fsl,imx8qxp-lpcg";
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reg = <0x5b280000 0x10000>;
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#clock-cells = <1>;
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clock-indices = <IMX_LPCG_CLK_7>;
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clocks = <&conn_ipg_clk>;
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clock-output-names = "usboh3_2_phy_ipg_clk";
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power-domains = <&pd IMX_SC_R_USB_1_PHY>;
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};
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};
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&enet0_lpcg {
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clocks = <&conn_enet0_root_clk>,
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<&conn_enet0_root_clk>,
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<&conn_axi_clk>,
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<&clk IMX_SC_R_ENET_0 IMX_SC_C_TXCLK>,
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<&conn_ipg_clk>,
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<&conn_ipg_clk>;
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};
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&fec1 {
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compatible = "fsl,imx8qm-fec";
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interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
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assigned-clocks = <&clk IMX_SC_R_ENET_0 IMX_SC_C_CLKDIV>;
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assigned-clock-rates = <125000000>;
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};
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&usdhc1 {
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compatible = "fsl,imx8dxl-usdhc", "fsl,imx8qxp-usdhc";
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interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
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};
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&usdhc2 {
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compatible = "fsl,imx8dxl-usdhc", "fsl,imx8qxp-usdhc";
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interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
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};
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&usdhc3 {
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compatible = "fsl,imx8dxl-usdhc", "fsl,imx8qxp-usdhc";
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interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
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};
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