165 lines
3.7 KiB
Plaintext
165 lines
3.7 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2012 Marvell Technology Group Ltd.
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* Author: Haojian Zhuang <haojian.zhuang@marvell.com>
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*/
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#include <dt-bindings/clock/marvell,pxa168.h>
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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aliases {
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serial0 = &uart1;
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serial1 = &uart2;
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serial2 = &uart3;
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i2c0 = &twsi1;
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i2c1 = &twsi2;
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};
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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interrupt-parent = <&intc>;
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ranges;
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axi@d4200000 { /* AXI */
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compatible = "mrvl,axi-bus", "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0xd4200000 0x00200000>;
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ranges;
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intc: interrupt-controller@d4282000 {
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compatible = "mrvl,mmp-intc";
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interrupt-controller;
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#interrupt-cells = <1>;
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reg = <0xd4282000 0x1000>;
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mrvl,intc-nr-irqs = <64>;
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};
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};
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apb@d4000000 { /* APB */
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compatible = "mrvl,apb-bus", "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0xd4000000 0x00200000>;
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ranges;
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timer0: timer@d4014000 {
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compatible = "mrvl,mmp-timer";
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reg = <0xd4014000 0x100>;
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interrupts = <13>;
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};
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uart1: serial@d4017000 {
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compatible = "mrvl,mmp-uart", "intel,xscale-uart";
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reg = <0xd4017000 0x1000>;
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reg-shift = <2>;
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interrupts = <27>;
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clocks = <&soc_clocks PXA168_CLK_UART0>;
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resets = <&soc_clocks PXA168_CLK_UART0>;
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status = "disabled";
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};
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uart2: serial@d4018000 {
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compatible = "mrvl,mmp-uart", "intel,xscale-uart";
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reg = <0xd4018000 0x1000>;
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reg-shift = <2>;
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interrupts = <28>;
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clocks = <&soc_clocks PXA168_CLK_UART1>;
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resets = <&soc_clocks PXA168_CLK_UART1>;
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status = "disabled";
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};
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uart3: serial@d4026000 {
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compatible = "mrvl,mmp-uart", "intel,xscale-uart";
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reg = <0xd4026000 0x1000>;
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reg-shift = <2>;
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interrupts = <29>;
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clocks = <&soc_clocks PXA168_CLK_UART2>;
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resets = <&soc_clocks PXA168_CLK_UART2>;
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status = "disabled";
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};
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gpio@d4019000 {
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compatible = "marvell,mmp-gpio";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0xd4019000 0x1000>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupts = <49>;
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clocks = <&soc_clocks PXA168_CLK_GPIO>;
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resets = <&soc_clocks PXA168_CLK_GPIO>;
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interrupt-names = "gpio_mux";
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interrupt-controller;
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#interrupt-cells = <2>;
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ranges;
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gcb0: gpio@d4019000 {
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reg = <0xd4019000 0x4>;
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};
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gcb1: gpio@d4019004 {
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reg = <0xd4019004 0x4>;
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};
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gcb2: gpio@d4019008 {
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reg = <0xd4019008 0x4>;
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};
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gcb3: gpio@d4019100 {
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reg = <0xd4019100 0x4>;
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};
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};
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twsi1: i2c@d4011000 {
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compatible = "mrvl,mmp-twsi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0xd4011000 0x1000>;
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interrupts = <7>;
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clocks = <&soc_clocks PXA168_CLK_TWSI0>;
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resets = <&soc_clocks PXA168_CLK_TWSI0>;
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mrvl,i2c-fast-mode;
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status = "disabled";
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};
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twsi2: i2c@d4025000 {
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compatible = "mrvl,mmp-twsi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0xd4025000 0x1000>;
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interrupts = <58>;
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clocks = <&soc_clocks PXA168_CLK_TWSI1>;
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resets = <&soc_clocks PXA168_CLK_TWSI1>;
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status = "disabled";
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};
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rtc: rtc@d4010000 {
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compatible = "mrvl,mmp-rtc";
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reg = <0xd4010000 0x1000>;
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interrupts = <5>, <6>;
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interrupt-names = "rtc 1Hz", "rtc alarm";
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clocks = <&soc_clocks PXA168_CLK_RTC>;
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resets = <&soc_clocks PXA168_CLK_RTC>;
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status = "disabled";
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};
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};
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soc_clocks: clocks{
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compatible = "marvell,pxa168-clock";
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reg = <0xd4050000 0x1000>,
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<0xd4282800 0x400>,
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<0xd4015000 0x1000>;
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reg-names = "mpmu", "apmu", "apbc";
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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};
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};
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